#include "swrast/swrast.h"
#include "main/simple_list.h"
+#include "radeon_cs.h"
#include "r200_context.h"
+#include "common_cmdbuf.h"
#include "r200_state.h"
#include "r200_ioctl.h"
#include "r200_tcl.h"
fprintf(stderr, "Returning to r200EmitState\n");
}
+static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty)
+{
+ BATCH_LOCALS(&r200->radeon);
+ struct radeon_state_atom *atom;
+ int dwords;
+
+ /* Emit actual atoms */
+ foreach(atom, &r200->hw.atomlist) {
+ if ((atom->dirty || r200->hw.all_dirty) == dirty) {
+ dwords = (*atom->check) (r200->radeon.glCtx, atom);
+ if (dwords) {
+ // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
+ // r300PrintStateAtom(r300, atom);
+ // }
+ if (atom->emit) {
+ (*atom->emit)(r200->radeon.glCtx, atom);
+ } else {
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
+ OUT_BATCH_TABLE(atom->cmd, dwords);
+ END_BATCH();
+ }
+ atom->dirty = GL_FALSE;
+ } else {
+ // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
+ // fprintf(stderr, " skip state %s\n",
+ // atom->name);
+ // }
+ }
+ }
+ }
+
+ COMMIT_BATCH();
+}
+
void r200EmitState( r200ContextPtr rmesa )
{
char *dest;
rmesa->save_on_next_emit = GL_FALSE;
}
- if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
- return;
+ if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
+ return;
mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
* for enough space for the case of emitting all state, and inline the
* r200AllocCmdBuf code here without all the checks.
*/
- r200EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size );
-
- /* we need to calculate dest after EnsureCmdBufSpace
- as we may flush the buffer - airlied */
- dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
- if (R200_DEBUG & DEBUG_STATE) {
- foreach( atom, &rmesa->hw.atomlist ) {
- if ( atom->dirty || rmesa->hw.all_dirty ) {
- dwords = atom->check( rmesa->radeon.glCtx, atom );
- if ( dwords )
- print_state_atom( atom );
- else
- fprintf(stderr, "skip state %s\n", atom->name);
- }
- }
- }
+ rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__);
- foreach( atom, &rmesa->hw.atomlist ) {
- if ( rmesa->hw.all_dirty )
- atom->dirty = GL_TRUE;
- if ( atom->dirty ) {
- dwords = atom->check( rmesa->radeon.glCtx, atom );
- if ( dwords ) {
- int size = atom->cmd_size * 4;
- if (atom->emit) {
- (*atom->emit)(rmesa->radeon.glCtx, atom);
- } else {
- memcpy( dest, atom->cmd, size);
- dest += size;
- rmesa->store.cmd_used += size;
- }
- atom->dirty = GL_FALSE;
- }
- }
+ if (!rmesa->radeon.cmdbuf.cs->cdw) {
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "Begin reemit state\n");
+
+ r200EmitAtoms(rmesa, GL_FALSE);
}
- assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ );
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "Begin dirty state\n");
+ r200EmitAtoms(rmesa, GL_TRUE);
rmesa->hw.is_dirty = GL_FALSE;
rmesa->hw.all_dirty = GL_FALSE;
}
GLuint vertex_nr )
{
drm_radeon_cmd_header_t *cmd;
+ BATCH_LOCALS(&rmesa->radeon);
assert(!(primitive & R200_VF_PRIM_WALK_IND));
if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
rmesa->store.cmd_used/4, primitive, vertex_nr);
-
+
+ BEGIN_BATCH(3);
+ OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
+ OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
+ (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
+ END_BATCH();
+#if 0
cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ,
__FUNCTION__ );
cmd[0].i = 0;
R200_VF_PRIM_WALK_LIST |
R200_VF_COLOR_ORDER_RGBA |
(vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
+#endif
}
r200EmitState( rmesa );
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr),
- __FUNCTION__ );
+ // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr),
+ // __FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2;
void r200EmitVertexAOS( r200ContextPtr rmesa,
- GLuint vertex_size,
- GLuint offset )
+ GLuint vertex_size,
+ struct radeon_bo *bo,
+ GLuint offset )
{
- drm_radeon_cmd_header_t *cmd;
+ BATCH_LOCALS(&rmesa->radeon);
if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ,
- __FUNCTION__ );
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16);
- cmd[2].i = 1;
- cmd[3].i = vertex_size | (vertex_size << 8);
- cmd[4].i = offset;
+ BEGIN_BATCH(5);
+ OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
+ OUT_BATCH(1);
+ OUT_BATCH(vertex_size | (vertex_size << 8));
+ OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
+ END_BATCH();
}
-
+void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
+{
+ BATCH_LOCALS(&rmesa->radeon);
+ uint32_t voffset;
+ int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
+ int i;
+
+ if (RADEON_DEBUG & DEBUG_VERTS)
+ fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
+ offset);
+
+ BEGIN_BATCH(sz+2);
+ OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1);
+ OUT_BATCH(nr);
+
+
+ if (!rmesa->radeon.radeonScreen->kernel_mm) {
+ for (i = 0; i + 1 < nr; i += 2) {
+ OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
+ (rmesa->tcl.aos[i].stride << 8) |
+ (rmesa->tcl.aos[i + 1].components << 16) |
+ (rmesa->tcl.aos[i + 1].stride << 24));
+
+ voffset = rmesa->tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ OUT_BATCH_RELOC(voffset,
+ rmesa->tcl.aos[i].bo,
+ voffset,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ voffset = rmesa->tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ OUT_BATCH_RELOC(voffset,
+ rmesa->tcl.aos[i+1].bo,
+ voffset,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+
+ if (nr & 1) {
+ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
+ (rmesa->tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH_RELOC(voffset,
+ rmesa->tcl.aos[nr - 1].bo,
+ voffset,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+ } else {
+ for (i = 0; i + 1 < nr; i += 2) {
+ OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
+ (rmesa->tcl.aos[i].stride << 8) |
+ (rmesa->tcl.aos[i + 1].components << 16) |
+ (rmesa->tcl.aos[i + 1].stride << 24));
+
+ voffset = rmesa->tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ OUT_BATCH(voffset);
+ voffset = rmesa->tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ OUT_BATCH(voffset);
+ }
+
+ if (nr & 1) {
+ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
+ (rmesa->tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH(voffset);
+ }
+ for (i = 0; i + 1 < nr; i += 2) {
+ voffset = rmesa->tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->tcl.aos[i+0].bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ voffset = rmesa->tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->tcl.aos[i+1].bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+ if (nr & 1) {
+ voffset = rmesa->tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->tcl.aos[nr-1].bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+ }
+ END_BATCH();
+}
+
+#if 0
void r200EmitAOS( r200ContextPtr rmesa,
struct radeon_dma_region **component,
GLuint nr,
fprintf(stderr, " %d: %x\n", i, tmp[i]);
}
}
+#endif
void r200EmitBlit( r200ContextPtr rmesa,
GLuint color_fmt,
assert( w < (1<<16) );
assert( h < (1<<16) );
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
- __FUNCTION__ );
+ // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
+ // __FUNCTION__ );
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
- __FUNCTION__ );
+ // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
+ // __FUNCTION__ );
cmd[0].i = 0;
cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
cmd[0].wait.flags = flags;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
struct dd_function_table functions;
r200ContextPtr rmesa;
- GLcontext *ctx, *shareCtx;
+ GLcontext *ctx;
int i;
- int tcl_mode, fthrottle_mode;
+ int tcl_mode;
assert(glVisual);
assert(driContextPriv);
r200InitTextureFuncs(&functions);
r200InitShaderFuncs(&functions);
- /* Allocate and initialize the Mesa context */
- if (sharedContextPrivate)
- shareCtx = ((r200ContextPtr) sharedContextPrivate)->radeon.glCtx;
- else
- shareCtx = NULL;
- rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx,
- &functions, (void *) rmesa);
- if (!rmesa->radeon.glCtx) {
- FREE(rmesa);
- return GL_FALSE;
+ if (!radeonInitContext(&rmesa->radeon, &functions,
+ glVisual, driContextPriv,
+ sharedContextPrivate)) {
+ FREE(rmesa);
+ return GL_FALSE;
}
- driContextPriv->driverPrivate = rmesa;
-
- /* Init r200 context data */
- rmesa->radeon.dri.context = driContextPriv;
- rmesa->radeon.dri.screen = sPriv;
- rmesa->radeon.dri.drawable = NULL; /* Set by XMesaMakeCurrent */
- rmesa->radeon.dri.hwContext = driContextPriv->hHWContext;
- rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock;
- rmesa->radeon.dri.fd = sPriv->fd;
- rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor;
-
- rmesa->radeon.radeonScreen = screen;
- rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
- screen->sarea_priv_offset);
rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address;
r200InitState( rmesa );
r200InitSwtcl( ctx );
- fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
- rmesa->radeon.iw.irq_seq = -1;
- rmesa->radeon.irqsEmitted = 0;
- rmesa->radeon.do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
- rmesa->radeon.radeonScreen->irq);
-
- rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
-
- if (!rmesa->radeon.do_irqs)
- fprintf(stderr,
- "IRQ's not enabled, falling back to %s: %d %d\n",
- rmesa->radeon.do_usleeps ? "usleeps" : "busy waits",
- fthrottle_mode,
- rmesa->radeon.radeonScreen->irq);
-
rmesa->prefer_gart_client_texturing =
(getenv("R200_GART_CLIENT_TEXTURES") != 0);
- (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
-
-
#if DO_DEBUG
R200_DEBUG = driParseDebugString( getenv( "R200_DEBUG" ),
debug_control );
r200ReleaseArrays( rmesa->radeon.glCtx, ~0 );
if (rmesa->dma.current.buf) {
- r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
- r200FlushCmdBuf( rmesa, __FUNCTION__ );
+ // r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
+ rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
}
if (rmesa->radeon.state.scissor.pClipRects) {
rmesa->radeon.state.scissor.pClipRects = NULL;
}
+
if ( release_texture_heaps ) {
/* This share group is about to go away, free our private
* texture object data.
assert( is_empty_list( & rmesa->radeon.swapped ) );
}
- /* free the Mesa context */
- rmesa->radeon.glCtx->DriverCtx = NULL;
- _mesa_destroy_context( rmesa->radeon.glCtx );
-
- /* free the option cache */
- driDestroyOptionCache (&rmesa->radeon.optionCache);
+ radeonCleanupContext(&rmesa->radeon);
FREE( rmesa );
}
}
-/* Force the context `c' to be the current context and associate with it
- * buffer `b'.
- */
-GLboolean
-r200MakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv )
-{
- if ( driContextPriv ) {
- r200ContextPtr newCtx =
- (r200ContextPtr) driContextPriv->driverPrivate;
-
- if (R200_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->radeon.glCtx);
-
- newCtx->radeon.dri.readable = driReadPriv;
-
- if ( newCtx->radeon.dri.drawable != driDrawPriv ||
- newCtx->radeon.lastStamp != driDrawPriv->lastStamp ) {
- if (driDrawPriv->swap_interval == (unsigned)-1) {
- driDrawPriv->vblFlags = (newCtx->radeon.radeonScreen->irq != 0)
- ? driGetDefaultVBlankFlags(&newCtx->radeon.optionCache)
- : VBLANK_FLAG_NO_IRQ;
-
- driDrawableInitVBlank( driDrawPriv );
- }
-
- newCtx->radeon.dri.drawable = driDrawPriv;
-
- radeonSetCliprects(&newCtx->radeon);
- r200UpdateViewportOffset( newCtx->radeon.glCtx );
- }
-
- _mesa_make_current( newCtx->radeon.glCtx,
- (GLframebuffer *) driDrawPriv->driverPrivate,
- (GLframebuffer *) driReadPriv->driverPrivate );
-
- _mesa_update_state( newCtx->radeon.glCtx );
- r200ValidateState( newCtx->radeon.glCtx );
-
- } else {
- if (R200_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
- _mesa_make_current( NULL, NULL, NULL );
- }
- if (R200_DEBUG & DEBUG_DRI)
- fprintf(stderr, "End %s\n", __FUNCTION__);
- return GL_TRUE;
-}
/* Force the context `c' to be unbound from its buffer.
*/
GLuint hw_primitive;
/* hw can handle 12 components max */
- struct radeon_dma_region *aos_components[12];
+ struct radeon_aos aos[12];
+ // struct radeon_dma_region *aos_components[12];
GLuint nr_aos_components;
GLuint *Elts;
*/
GLboolean needproj;
+ struct radeon_bo *bo;
+ void (*flush) (r200ContextPtr);
struct radeon_dma_region indexed_verts;
};
#define R200_MAX_VERTEX_SIZE ((3*6)+11)
-
struct r200_context {
struct radeon_context radeon;
/* Clientdata textures;
*/
- GLuint prefer_gart_client_texturing;
+ GLuint prefer_gart_client_texturing;
GLboolean save_on_next_emit;
#include "swrast/swrast.h"
#include "r200_context.h"
+#include "common_cmdbuf.h"
#include "r200_state.h"
#include "r200_ioctl.h"
#include "r200_tcl.h"
saved_store = rmesa->store;
rmesa->dma.nr_released_bufs = 0;
rmesa->store = rmesa->backup_store;
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
rmesa->dma.nr_released_bufs = nr_released_bufs;
rmesa->store = saved_store;
}
+#if 0
int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
{
int ret, i;
return ret;
}
-
/* Note: does not emit any commands to avoid recursion on
* r200AllocCmdBuf.
*/
LOCK_HARDWARE( &rmesa->radeon );
- ret = r200FlushCmdBufLocked( rmesa, caller );
+ ret = rcommonFlushCmdBufLocked( rmesa, caller );
UNLOCK_HARDWARE( &rmesa->radeon );
exit(ret);
}
}
+#endif
/* =============================================================
* Hardware vertex buffer handling
*/
-
+#if 0
void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
{
struct radeon_dma_buffer *dmabuf;
r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
if (rmesa->dma.nr_released_bufs > 4)
- r200FlushCmdBuf( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
dma.context = rmesa->radeon.dri.hwContext;
dma.send_count = 0;
break;
if (rmesa->dma.nr_released_bufs) {
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
}
if (rmesa->radeon.do_usleeps) {
assert( rmesa->dma.current.ptr <= rmesa->dma.current.end );
}
-
+#endif
/* ================================================================
* Buffer clear
}
/* Send current state to the hardware */
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
for ( i = 0 ; i < dPriv->numClipRects ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
r200EmitState( rmesa );
if (rmesa->store.cmd_used)
- r200FlushCmdBuf( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
}
/* Make sure all commands have been sent to the hardware and have
extern void r200EmitState( r200ContextPtr rmesa );
extern void r200EmitVertexAOS( r200ContextPtr rmesa,
- GLuint vertex_size,
- GLuint offset );
+ GLuint vertex_size,
+ struct radeon_bo *bo,
+ GLuint offset );
extern void r200EmitVbufPrim( r200ContextPtr rmesa,
GLuint primitive,
GLuint primitive,
GLuint min_nr );
-extern void r200EmitAOS( r200ContextPtr rmesa,
- struct radeon_dma_region **regions,
- GLuint n,
- GLuint offset );
+extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
extern void r200EmitBlit( r200ContextPtr rmesa,
GLuint color_fmt,
extern void r200EmitWait( r200ContextPtr rmesa, GLuint flags );
-extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * );
-extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller );
+//extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * );
+//extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller );
extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa );
* and hang on to the lock until the critical section is finished and we flush
* the buffer again and unlock.
*/
+#if 0
static INLINE void r200EnsureCmdBufSpace( r200ContextPtr rmesa, int bytes )
{
if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ)
- r200FlushCmdBuf( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBuf( rmesa, __FUNCTION__ );
assert( bytes <= R200_CMD_BUF_SZ );
}
assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ );
return head;
}
+#endif
+
+static inline uint32_t cmdpacket3_clip(int cmd_type)
+{
+ drm_radeon_cmd_header_t cmd;
+
+ cmd.i = 0;
+ cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP;
+
+ return (uint32_t)cmd.i;
+
+}
+#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \
+ if (!b_l_rmesa->radeonScreen->kernel_mm) { \
+ OUT_BATCH(cmdpacket3_clip(0)); \
+ OUT_BATCH(packet); \
+ } else { \
+ OUT_BATCH(CP_PACKET2); \
+ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
+ } \
+ } while(0)
+
+static inline uint32_t cmdpacket3(int cmd_type)
+{
+ drm_radeon_cmd_header_t cmd;
+
+ cmd.i = 0;
+ cmd.header.cmd_type = RADEON_CMD_PACKET3;
+
+ return (uint32_t)cmd.i;
+
+}
+#define OUT_BATCH_PACKET3(packet, num_extra) do { \
+ if (!b_l_rmesa->radeonScreen->kernel_mm) { \
+ OUT_BATCH(cmdpacket3(0)); \
+ OUT_BATCH(packet); \
+ } else { \
+ OUT_BATCH(CP_PACKET2); \
+ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
+ } \
+ } while(0)
+
#endif /* __R200_IOCTL_H__ */
assert (!rvb->buf);
if (stride == 0) {
- r200AllocDmaRegion( rmesa, rvb, 4, 4 );
+ // r200AllocDmaRegion( rmesa, rvb, 4, 4 );
count = 1;
rvb->aos_start = GET_START(rvb);
rvb->aos_stride = 0;
rvb->aos_size = 1;
}
else {
- r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */
+ // r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */
rvb->aos_start = GET_START(rvb);
rvb->aos_stride = 1;
rvb->aos_size = 1;
assert (!rvb->buf);
if (stride == 0) {
- r200AllocDmaRegion( rmesa, rvb, 4, 4 );
+ // r200AllocDmaRegion( rmesa, rvb, 4, 4 );
count = 1;
rvb->aos_start = GET_START(rvb);
rvb->aos_stride = 0;
rvb->aos_size = 1;
}
else {
- r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */
+ // r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */
rvb->aos_start = GET_START(rvb);
rvb->aos_stride = 1;
rvb->aos_size = 1;
assert (!rvb->buf);
if (stride == 0) {
- r200AllocDmaRegion( rmesa, rvb, size * 4, 4 );
+ // r200AllocDmaRegion( rmesa, rvb, size * 4, 4 );
count = 1;
rvb->aos_start = GET_START(rvb);
rvb->aos_stride = 0;
rvb->aos_size = size;
}
else {
- r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */
+ // r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */
rvb->aos_start = GET_START(rvb);
rvb->aos_stride = size;
rvb->aos_size = size;
{
r200ContextPtr rmesa = R200_CONTEXT( ctx );
struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb;
- struct radeon_dma_region **component = rmesa->tcl.aos_components;
+ // struct radeon_dma_region **component = rmesa->tcl.aos_components;
GLuint nr = 0;
GLuint vfmt0 = 0, vfmt1 = 0;
GLuint count = VB->Count;
assert(attrib == VERT_ATTRIB_FOG);
if (!rmesa->tcl.vertex_data[i].buf) {
if (ctx->VertexProgram._Enabled)
- emit_vector( ctx,
- &(rmesa->tcl.vertex_data[i]),
- (char *)VB->AttribPtr[attrib]->data,
- 1,
- VB->AttribPtr[attrib]->stride,
- count);
+ rcommon_emit_vector( ctx,
+ &(rmesa->tcl.vertex_data[i]),
+ (char *)VB->AttribPtr[attrib]->data,
+ 1,
+ VB->AttribPtr[attrib]->stride,
+ count);
else
emit_vecfog( ctx,
&(rmesa->tcl.vertex_data[i]),
}
after_emit:
assert(nr < 12);
- component[nr++] = &rmesa->tcl.vertex_data[i];
+ // component[nr++] = &rmesa->tcl.vertex_data[i];
}
}
/* only do it for changed inputs ? */
int i;
for (i = 0; i < 15; i++) {
- if (newinputs & (1 << i))
- r200ReleaseDmaRegion( rmesa,
- &rmesa->tcl.vertex_data[i], __FUNCTION__ );
+ // if (newinputs & (1 << i))
+ // r200ReleaseDmaRegion( rmesa,
+ // &rmesa->tcl.vertex_data[i], __FUNCTION__ );
}
}
LOCK_HARDWARE( &rmesa->radeon );
if (rmesa->store.cmd_used)
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height,
&size)) {
bw, bh );
}
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
}
UNLOCK_HARDWARE( &rmesa->radeon );
LOCK_HARDWARE( &rmesa->radeon );
if (rmesa->store.cmd_used)
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
y -= height; /* cope with pixel zoom */
bw, bh );
}
- r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */
UNLOCK_HARDWARE( &rmesa->radeon );
}
#include "swrast/swrast.h"
#include "r200_context.h"
+#include "radeon_buffer.h"
#include "r200_ioctl.h"
#include "r200_state.h"
#include "r200_span.h"
#define SPANTMP_PIXEL_FMT GL_RGB
#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-#define TAG(x) r200##x##_RGB565
-#define TAG2(x,y) r200##x##_RGB565##y
+#define TAG(x) radeon##x##_RGB565
+#define TAG2(x,y) radeon##x##_RGB565##y
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
#include "spantmp2.h"
#define SPANTMP_PIXEL_FMT GL_BGRA
#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define TAG(x) r200##x##_ARGB8888
-#define TAG2(x,y) r200##x##_ARGB8888##y
+#define TAG(x) radeon##x##_ARGB8888
+#define TAG2(x,y) radeon##x##_ARGB8888##y
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
#include "spantmp2.h"
#define READ_DEPTH( d, _x, _y ) \
d = *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo ));
-#define TAG(x) r200##x##_z16
+#define TAG(x) radeon##x##_z16
#include "depthtmp.h"
d = *(GLuint *)(buf + r200_mba_z32( drb, _x + xo, \
_y + yo )) & 0x00ffffff;
-#define TAG(x) r200##x##_z24_s8
+#define TAG(x) radeon##x##_z24_s8
#include "depthtmp.h"
d = tmp >> 24; \
} while (0)
-#define TAG(x) r200##x##_z24_s8
+#define TAG(x) radeon##x##_z24_s8
#include "stenciltmp.h"
/**
* Plug in the Get/Put routines for the given driRenderbuffer.
*/
-void
-radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
+void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
{
- if (drb->Base.InternalFormat == GL_RGBA) {
- if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
- r200InitPointers_RGB565(&drb->Base);
- }
- else {
- r200InitPointers_ARGB8888(&drb->Base);
- }
- }
- else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
- r200InitDepthPointers_z16(&drb->Base);
- }
- else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
- r200InitDepthPointers_z24_s8(&drb->Base);
- }
- else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
- r200InitStencilPointers_z24_s8(&drb->Base);
- }
+ if (rrb->base.InternalFormat == GL_RGB5) {
+ radeonInitPointers_RGB565(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_RGBA8) {
+ radeonInitPointers_ARGB8888(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) {
+ radeonInitDepthPointers_z16(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) {
+ radeonInitDepthPointers_z24_s8(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
+ radeonInitStencilPointers_z24_s8(&rrb->base);
+ }
}
extern void r200InitSpanFuncs( GLcontext *ctx );
-extern void
-radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
+extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
#endif
#include "tnl/t_pipeline.h"
#include "swrast_setup/swrast_setup.h"
+#include "radeon_buffer.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
- GLfloat xoffset = (GLfloat)dPriv->x;
- GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
+ GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
+ GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
const GLfloat *v = ctx->Viewport._WindowMap.m;
float_ui32_type sx = { v[MAT_SX] };
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
- driRenderbuffer *drb;
+ struct radeon_renderbuffer *rrb;
if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
- /* draw to front */
- drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
- }
- else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
- /* draw to back */
- drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- }
- else {
- /* drawing to multiple buffers, or none */
- return;
+ /* draw to front */
+ rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
+ /* draw to back */
+ rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ } else {
+ /* drawing to multiple buffers, or none */
+ return;
}
- assert(drb);
- assert(drb->flippedPitch);
+ assert(rrb);
+ assert(rrb->pitch);
R200_STATECHANGE( rmesa, ctx );
+#if 0
/* Note: we used the (possibly) page-flipped values */
rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
- = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation)
+ = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation)
& R200_COLOROFFSET_MASK);
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
if (rmesa->radeon.sarea->tiling_enabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
}
+#endif
}
#include "xmlpool.h"
+/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
+ * 1.3 cmdbuffers allow all previous state to be updated as well as
+ * the tcl scalar and vector areas.
+ */
+static struct {
+ int start;
+ int len;
+ const char *name;
+} packet[RADEON_MAX_STATE_PACKETS] = {
+ {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
+ {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
+ {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
+ {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
+ {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
+ {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
+ {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
+ {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
+ {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
+ {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
+ {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
+ {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
+ {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
+ {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
+ {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
+ {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
+ {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
+ {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
+ {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
+ {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
+ {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
+ "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
+ {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
+ {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
+ {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
+ {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
+ {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
+ {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
+ {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
+ {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
+ {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
+ {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
+ {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
+ {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
+ {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
+ {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
+ {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
+ {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
+ {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
+ {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
+ {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
+ {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
+ {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
+ {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
+ {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
+ {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
+ {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
+ {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
+ {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
+ {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
+ {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
+ "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
+ {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
+ {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
+ {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
+ {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
+ {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
+ {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
+ {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
+ {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
+ {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
+ {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
+ {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
+ "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
+ {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
+ {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
+ {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
+ {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
+ {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
+ {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
+ {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
+ {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
+ {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
+ {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
+ {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
+ {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
+ {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
+ {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
+ {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
+ {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
+ {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
+ {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
+ {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
+ {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
+ {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
+ {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
+ {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
+ {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
+ {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
+ {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
+ {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
+ {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
+ {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
+ {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
+ {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
+ {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
+ {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
+ {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
+};
+
/* =============================================================
* State initialization
*/
VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
+#if 0
+static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+ r200ContextPtr r200 = R200_CONTEXT(ctx);
+ BATCH_LOCALS(&r200->radeon);
+ struct radeon_renderbuffer *rrb;
+ uint32_t cbpitch;
+ GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
+
+ rrb = r200->radeon.state.color.rrb;
+ if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
+ rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ }
+ if (!rrb || !rrb->bo) {
+ fprintf(stderr, "no rrb\n");
+ return;
+ }
+
+ cbpitch = (rrb->pitch / rrb->cpp);
+ if (rrb->cpp == 4)
+ ;
+ else
+ ;
+
+}
+#endif
+
+static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+
+}
+
+
/* Initialize the context's hardware state.
*/
void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
else
ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
+
+ // rmesa->hw.ctx.emit = ctx_emit;
ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
r200LightingSpaceChange( ctx );
rmesa->hw.all_dirty = GL_TRUE;
+
+ rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size);
}
#include "tnl/t_context.h"
#include "tnl/t_pipeline.h"
+#include "radeon_bo.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
rmesa->dma.flush = NULL;
- if (rmesa->dma.current.buf) {
- struct radeon_dma_region *current = &rmesa->dma.current;
- GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset +
- current->buf->buf->idx * RADEON_BUFFER_SIZE +
- current->start);
+ radeon_bo_unmap(rmesa->swtcl.bo);
+ rcommonEnsureCmdBufSpace(rmesa,
+ rmesa->hw.max_state_size + (12*sizeof(int)),
+ __FUNCTION__);
- assert (!(rmesa->swtcl.hw_primitive & R200_VF_PRIM_WALK_IND));
- assert (current->start +
- rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
- current->ptr);
+ r200EmitState(rmesa);
+ r200EmitVertexAOS( rmesa,
+ rmesa->swtcl.vertex_size,
+ rmesa->swtcl.bo, 0);
- if (rmesa->dma.current.start != rmesa->dma.current.ptr) {
- r200EnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ +
- rmesa->hw.max_state_size + VBUF_BUFSZ );
- r200EmitVertexAOS( rmesa,
- rmesa->swtcl.vertex_size,
- current_offset);
+
+ r200EmitVbufPrim( rmesa,
+ rmesa->swtcl.hw_primitive,
+ rmesa->swtcl.numverts);
- r200EmitVbufPrim( rmesa,
- rmesa->swtcl.hw_primitive,
- rmesa->swtcl.numverts);
- }
-
- rmesa->swtcl.numverts = 0;
- current->start = current->ptr;
- }
+ // COMMIT_BATCH();
+ rmesa->swtcl.numverts = 0;
}
{
GLuint bytes = vsize * nverts;
- if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
- r200RefillCurrentDmaRegion( rmesa );
-
- if (!rmesa->dma.flush) {
- rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
- rmesa->dma.flush = flush_last_swtcl_prim;
- }
-
- ASSERT( vsize == rmesa->swtcl.vertex_size * 4 );
- ASSERT( rmesa->dma.flush == flush_last_swtcl_prim );
- ASSERT( rmesa->dma.current.start +
- rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
- rmesa->dma.current.ptr );
-
-
- {
- GLubyte *head = (GLubyte *) (rmesa->dma.current.address + rmesa->dma.current.ptr);
- rmesa->dma.current.ptr += bytes;
- rmesa->swtcl.numverts += nverts;
- return head;
+ rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+ 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0);
+ radeon_bo_map(rmesa->swtcl.bo, 1);
+ if (rmesa->swtcl.flush == NULL) {
+ rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+ rmesa->swtcl.flush = flush_last_swtcl_prim;
}
+ return rmesa->swtcl.bo->ptr;
+
}
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- if (rmesa->swtcl.indexed_verts.buf)
- r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ );
+ // if (rmesa->swtcl.indexed_verts.buf)
+ // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ );
}
if (rmesa->dma.flush)
rmesa->dma.flush( rmesa->radeon.glCtx );
- r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+ rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + ELTS_BUFSZ(nr) );
r200EmitAOS( rmesa,
- rmesa->tcl.aos_components,
rmesa->tcl.nr_aos_components, 0 );
return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
r200ContextPtr rmesa = R200_CONTEXT( ctx );
r200TclPrimitive( ctx, prim, hwprim );
- r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
- rmesa->hw.max_state_size + VBUF_BUFSZ );
+ rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+ rmesa->hw.max_state_size + VBUF_BUFSZ );
r200EmitAOS( rmesa,
- rmesa->tcl.aos_components,
- rmesa->tcl.nr_aos_components,
- start );
+ rmesa->tcl.nr_aos_components,
+ start );
/* Why couldn't this packet have taken an offset param?
*/
rmesa->dma.flush = NULL;
- if (rmesa->swtcl.indexed_verts.buf)
- r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
- __FUNCTION__ );
+ // if (rmesa->swtcl.indexed_verts.buf)
+ // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
+ // __FUNCTION__ );
R200_STATECHANGE( rmesa, vap );
rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE;
tex = (char *)texImage->Data + done * src_pitch;
memset(®ion, 0, sizeof(region));
- r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 );
+ // r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 );
/* Copy texdata to dma:
*/
r200EmitWait( rmesa, RADEON_WAIT_2D );
- r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ );
+ // r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ );
done += lines;
}
}
* state, so don't destroy it earlier
*/
- /* free the option cache */
- driDestroyOptionCache(&r300->radeon.optionCache);
FREE(r300);
}
#define REG_COLOR0 1
#define REG_TEX0 2
-struct r300_aos {
- struct radeon_bo *bo; /** Buffer object where vertex data is stored */
- int offset; /** Offset into buffer object, in bytes */
- int components; /** Number of components per vertex */
- int stride; /** Stride in dwords (may be 0 for repeating) */
- int count; /** Number of vertices */
-};
-
struct r300_state {
struct r300_texture_state texture;
int sw_tcl_inputs[VERT_ATTRIB_MAX];
struct r300_vertex_shader_state vertex_shader;
- struct r300_aos aos[R300_MAX_AOS_ARRAYS];
+ struct radeon_aos aos[R300_MAX_AOS_ARRAYS];
int aos_count;
struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
#define DEBUG_ALL DEBUG_VERTS
-#if defined(USE_X86_ASM)
-#define COPY_DWORDS( dst, src, nr ) \
-do { \
- int __tmp; \
- __asm__ __volatile__( "rep ; movsl" \
- : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \
- : "0" (nr), \
- "D" ((long)dst), \
- "S" ((long)src) ); \
-} while (0)
-#else
-#define COPY_DWORDS( dst, src, nr ) \
-do { \
- int j; \
- for ( j = 0 ; j < nr ; j++ ) \
- dst[j] = ((int *)src)[j]; \
- dst += nr; \
-} while (0)
-#endif
-
-static void r300EmitVec4(uint32_t *out, GLvoid * data, int stride, int count)
-{
- int i;
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d out %p data %p\n",
- __FUNCTION__, count, stride, (void *)out, (void *)data);
-
- if (stride == 4)
- COPY_DWORDS(out, data, count);
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out++;
- data += stride;
- }
-}
-
-static void r300EmitVec8(uint32_t *out, GLvoid * data, int stride, int count)
-{
- int i;
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d out %p data %p\n",
- __FUNCTION__, count, stride, (void *)out, (void *)data);
-
- if (stride == 8)
- COPY_DWORDS(out, data, count * 2);
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data + 4);
- out += 2;
- data += stride;
- }
-}
-
-static void r300EmitVec12(uint32_t *out, GLvoid * data, int stride, int count)
-{
- int i;
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d out %p data %p\n",
- __FUNCTION__, count, stride, (void *)out, (void *)data);
-
- if (stride == 12) {
- COPY_DWORDS(out, data, count * 3);
- }
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data + 4);
- out[2] = *(int *)(data + 8);
- out += 3;
- data += stride;
- }
-}
-
-static void r300EmitVec16(uint32_t *out, GLvoid * data, int stride, int count)
-{
- int i;
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d out %p data %p\n",
- __FUNCTION__, count, stride, (void *)out, (void *)data);
-
- if (stride == 16)
- COPY_DWORDS(out, data, count * 4);
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data + 4);
- out[2] = *(int *)(data + 8);
- out[3] = *(int *)(data + 12);
- out += 4;
- data += stride;
- }
-}
-
-static void r300EmitVec(GLcontext * ctx, struct r300_aos *aos,
- GLvoid * data, int size, int stride, int count)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- uint32_t *out;
- uint32_t bo_size;
-
- memset(aos, 0, sizeof(struct r300_aos));
- if (stride == 0) {
- bo_size = size * 4;
- count = 1;
- aos->stride = 0;
- } else {
- bo_size = size * count * 4;
- aos->stride = size;
- }
- aos->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
- 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0);
- aos->offset = 0;
- aos->components = size;
- aos->count = count;
-
- radeon_bo_map(aos->bo, 1);
- out = (uint32_t*)((char*)aos->bo->ptr + aos->offset);
- switch (size) {
- case 1: r300EmitVec4(out, data, stride, count); break;
- case 2: r300EmitVec8(out, data, stride, count); break;
- case 3: r300EmitVec12(out, data, stride, count); break;
- case 4: r300EmitVec16(out, data, stride, count); break;
- default:
- assert(0);
- break;
- }
- radeon_bo_unmap(aos->bo);
-}
-
#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \
(attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT)
for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) {
swizzle[i][ci] = ci;
}
- r300EmitVec(ctx, &rmesa->state.aos[i],
- vb->AttribPtr[tab[i]]->data,
- vb->AttribPtr[tab[i]]->size,
- vb->AttribPtr[tab[i]]->stride, count);
+ rcommon_emit_vector(ctx, &rmesa->state.aos[i],
+ vb->AttribPtr[tab[i]]->data,
+ vb->AttribPtr[tab[i]]->size,
+ vb->AttribPtr[tab[i]]->stride, count);
}
/* Setup INPUT_ROUTE. */
#include "r300_cmdbuf.h"
#include "radeon_reg.h"
-/* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up
- * with DRM */
-#define CP_PACKET2 (2 << 30)
-#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
-#define CP_PACKET3( pkt, n ) \
- (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
-
static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn,
int reg, int count)
{
rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
0, n_elts * 4, 4,
RADEON_GEM_DOMAIN_GTT, 0);
- rmesa->state.elt_dma_offset = 0;
- radeon_bo_map(rmesa->state.elt_dma_bo, 1);
+ rmesa->state.elt_dma_offset = 0;
+ radeon_bo_map(rmesa->state.elt_dma_bo, 1);
out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset;
memcpy(out, elts, n_elts * 4);
- radeon_bo_unmap(rmesa->state.elt_dma_bo);
+ radeon_bo_unmap(rmesa->state.elt_dma_bo);
}
static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
GLuint bytes = vsize * nverts;
rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
- 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0);
- radeon_bo_map(rmesa->swtcl.bo, 1);
- if (rmesa->swtcl.flush == NULL) {
- rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
- rmesa->swtcl.flush = flush_last_swtcl_prim;
- }
- return rmesa->swtcl.bo->ptr;
+ 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0);
+ radeon_bo_map(rmesa->swtcl.bo, 1);
+ if (rmesa->swtcl.flush == NULL) {
+ rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+ rmesa->swtcl.flush = flush_last_swtcl_prim;
+ }
+ return rmesa->swtcl.bo->ptr;
}
static GLuint reduced_prim[] = {
#include "xmlpool.h" /* for symbolic values of enum-type options */
#include "drirenderbuffer.h"
-#define DRIVER_DATE "20060815"
-
-
-/* Return various strings for glGetString().
- */
-static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- static char buffer[128];
-
- switch (name) {
- case GL_VENDOR:
- if (IS_R300_CLASS(radeon->radeonScreen))
- return (GLubyte *) "DRI R300 Project";
- else
- return (GLubyte *) "Tungsten Graphics, Inc.";
-
- case GL_RENDERER:
- {
- unsigned offset;
- GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
- radeon->radeonScreen->AGPMode;
- const char* chipname;
-
-
-
- if (IS_R300_CLASS(radeon->radeonScreen))
- chipname = "R300";
- else
- chipname = "R200";
-
- offset = driGetRendererString(buffer, chipname, DRIVER_DATE,
- agp_mode);
-
- if (IS_R300_CLASS(radeon->radeonScreen)) {
- sprintf(&buffer[offset], " %sTCL",
- (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
- ? "" : "NO-");
- } else {
- sprintf(&buffer[offset], " %sTCL",
- !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
- ? "" : "NO-");
- }
-
- if (radeon->radeonScreen->driScreen->dri2.enabled)
- strcat(buffer, " DRI2");
-
- return (GLubyte *) buffer;
- }
-
- default:
- return NULL;
- }
-}
-
-/* Initialize the driver's misc functions.
- */
-static void radeonInitDriverFuncs(struct dd_function_table *functions)
-{
- functions->GetString = radeonGetString;
-}
-
-
-/**
- * Create and initialize all common fields of the context,
- * including the Mesa context itself.
- */
-GLboolean radeonInitContext(radeonContextPtr radeon,
- struct dd_function_table* functions,
- const __GLcontextModes * glVisual,
- __DRIcontextPrivate * driContextPriv,
- void *sharedContextPrivate)
-{
- __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
- radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
- GLcontext* ctx;
- GLcontext* shareCtx;
- int fthrottle_mode;
-
- /* Fill in additional standard functions. */
- radeonInitDriverFuncs(functions);
-
- radeon->radeonScreen = screen;
- /* Allocate and initialize the Mesa context */
- if (sharedContextPrivate)
- shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
- else
- shareCtx = NULL;
- radeon->glCtx = _mesa_create_context(glVisual, shareCtx,
- functions, (void *)radeon);
- if (!radeon->glCtx)
- return GL_FALSE;
-
- ctx = radeon->glCtx;
- driContextPriv->driverPrivate = radeon;
-
- /* DRI fields */
- radeon->dri.context = driContextPriv;
- radeon->dri.screen = sPriv;
- radeon->dri.drawable = NULL;
- radeon->dri.readable = NULL;
- radeon->dri.hwContext = driContextPriv->hHWContext;
- radeon->dri.hwLock = &sPriv->pSAREA->lock;
- radeon->dri.fd = sPriv->fd;
- radeon->dri.drmMinor = sPriv->drm_version.minor;
-
- radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
- screen->sarea_priv_offset);
-
- /* Setup IRQs */
- fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
- radeon->iw.irq_seq = -1;
- radeon->irqsEmitted = 0;
- radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
- radeon->radeonScreen->irq);
-
- radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
-
- if (!radeon->do_irqs)
- fprintf(stderr,
- "IRQ's not enabled, falling back to %s: %d %d\n",
- radeon->do_usleeps ? "usleeps" : "busy waits",
- fthrottle_mode, radeon->radeonScreen->irq);
-
- (*sPriv->systemTime->getUST) (&radeon->swap_ust);
-
- return GL_TRUE;
-}
-
-
-/**
- * Cleanup common context fields.
- * Called by r200DestroyContext/r300DestroyContext
- */
-void radeonCleanupContext(radeonContextPtr radeon)
-{
- FILE *track;
- struct radeon_renderbuffer *rb;
- GLframebuffer *fb;
-
- fb = (void*)radeon->dri.drawable->driverPrivate;
- rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
- if (rb && rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- if (rb && rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
- if (rb && rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- fb = (void*)radeon->dri.readable->driverPrivate;
- rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
- if (rb && rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- if (rb && rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
- if (rb && rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
-
- /* _mesa_destroy_context() might result in calls to functions that
- * depend on the DriverCtx, so don't set it to NULL before.
- *
- * radeon->glCtx->DriverCtx = NULL;
- */
-
- /* free the Mesa context */
- _mesa_destroy_context(radeon->glCtx);
-
- if (radeon->state.scissor.pClipRects) {
- FREE(radeon->state.scissor.pClipRects);
- radeon->state.scissor.pClipRects = 0;
- }
- track = fopen("/tmp/tracklog", "w");
- if (track) {
- radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
- fclose(track);
- }
-}
-
-static void
-radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
- GLframebuffer *draw)
-{
- /* if radeon->fake */
- struct radeon_renderbuffer *rb;
-
- if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
-
- if (!rb->bo) {
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- radeon->radeonScreen->frontOffset,
- 0,
- 0,
- RADEON_GEM_DOMAIN_VRAM,
- 0);
- }
- rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
- }
- if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
- if (!rb->bo) {
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- radeon->radeonScreen->backOffset,
- 0,
- 0,
- RADEON_GEM_DOMAIN_VRAM,
- 0);
- }
- rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
- }
- if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
- if (!rb->bo) {
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- radeon->radeonScreen->depthOffset,
- 0,
- 0,
- RADEON_GEM_DOMAIN_VRAM,
- 0);
- }
- rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
- }
-}
-
-static void
-radeon_make_renderbuffer_current(radeonContextPtr radeon,
- GLframebuffer *draw)
-{
- int size = 4096*4096*4;
- /* if radeon->fake */
- struct radeon_renderbuffer *rb;
-
- if (radeon->radeonScreen->kernel_mm) {
- radeon_make_kernel_renderbuffer_current(radeon, draw);
- return;
- }
-
-
- if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
- if (!rb->bo) {
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- radeon->radeonScreen->frontOffset +
- radeon->radeonScreen->fbLocation,
- size,
- 4096,
- RADEON_GEM_DOMAIN_VRAM,
- 0);
- }
- rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
- }
- if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
- if (!rb->bo) {
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- radeon->radeonScreen->backOffset +
- radeon->radeonScreen->fbLocation,
- size,
- 4096,
- RADEON_GEM_DOMAIN_VRAM,
- 0);
- }
- rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
- }
- if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
- if (!rb->bo) {
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- radeon->radeonScreen->depthOffset +
- radeon->radeonScreen->fbLocation,
- size,
- 4096,
- RADEON_GEM_DOMAIN_VRAM,
- 0);
- }
- rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
- }
-}
-
-
-void
-radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
-{
- unsigned int attachments[10];
- __DRIbuffer *buffers;
- __DRIscreen *screen;
- struct radeon_renderbuffer *rb;
- int i, count;
- GLframebuffer *draw;
- radeonContextPtr radeon;
-
- draw = drawable->driverPrivate;
- screen = context->driScreenPriv;
- radeon = (radeonContextPtr) context->driverPrivate;
- i = 0;
- if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
- attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
- }
- if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
- attachments[i++] = __DRI_BUFFER_BACK_LEFT;
- }
- if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
- attachments[i++] = __DRI_BUFFER_DEPTH;
- }
-
- buffers = (*screen->dri2.loader->getBuffers)(drawable,
- &drawable->w,
- &drawable->h,
- attachments, i,
- &count,
- drawable->loaderPrivate);
- if (buffers == NULL)
- return;
-
- /* set one cliprect to cover the whole drawable */
- drawable->x = 0;
- drawable->y = 0;
- drawable->backX = 0;
- drawable->backY = 0;
- drawable->numClipRects = 1;
- drawable->pClipRects[0].x1 = 0;
- drawable->pClipRects[0].y1 = 0;
- drawable->pClipRects[0].x2 = drawable->w;
- drawable->pClipRects[0].y2 = drawable->h;
- drawable->numBackClipRects = 1;
- drawable->pBackClipRects[0].x1 = 0;
- drawable->pBackClipRects[0].y1 = 0;
- drawable->pBackClipRects[0].x2 = drawable->w;
- drawable->pBackClipRects[0].y2 = drawable->h;
- for (i = 0; i < count; i++) {
- switch (buffers[i].attachment) {
- case __DRI_BUFFER_FRONT_LEFT:
- rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
- if (rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb->cpp = buffers[i].cpp;
- rb->pitch = buffers[i].pitch;
- rb->width = drawable->w;
- rb->height = drawable->h;
- rb->has_surface = 0;
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- buffers[i].name,
- 0,
- 0,
- RADEON_GEM_DOMAIN_VRAM,
- buffers[i].flags);
- if (rb->bo == NULL) {
- fprintf(stderr, "failled to attach front %d\n",
- buffers[i].name);
- }
- break;
- case __DRI_BUFFER_BACK_LEFT:
- rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- if (rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb->cpp = buffers[i].cpp;
- rb->pitch = buffers[i].pitch;
- rb->width = drawable->w;
- rb->height = drawable->h;
- rb->has_surface = 0;
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- buffers[i].name,
- 0,
- 0,
- RADEON_GEM_DOMAIN_VRAM,
- buffers[i].flags);
- break;
- case __DRI_BUFFER_DEPTH:
- rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer;
- if (rb->bo) {
- radeon_bo_unref(rb->bo);
- rb->bo = NULL;
- }
- rb->cpp = buffers[i].cpp;
- rb->pitch = buffers[i].pitch;
- rb->width = drawable->w;
- rb->height = drawable->h;
- rb->has_surface = 0;
- rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
- buffers[i].name,
- 0,
- 0,
- RADEON_GEM_DOMAIN_VRAM,
- buffers[i].flags);
- break;
- case __DRI_BUFFER_STENCIL:
- break;
- case __DRI_BUFFER_ACCUM:
- default:
- fprintf(stderr,
- "unhandled buffer attach event, attacment type %d\n",
- buffers[i].attachment);
- return;
- }
- }
- radeon = (radeonContextPtr) context->driverPrivate;
- driUpdateFramebufferSize(radeon->glCtx, drawable);
-}
-
-
-/* Force the context `c' to be the current context and associate with it
- * buffer `b'.
- */
-GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
- __DRIdrawablePrivate * driDrawPriv,
- __DRIdrawablePrivate * driReadPriv)
-{
- radeonContextPtr radeon;
- GLframebuffer *dfb, *rfb;
-
- if (!driContextPriv) {
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
- _mesa_make_current(NULL, NULL, NULL);
- return GL_TRUE;
- }
- radeon = (radeonContextPtr) driContextPriv->driverPrivate;
- dfb = driDrawPriv->driverPrivate;
- rfb = driReadPriv->driverPrivate;
-
- if (driContextPriv->driScreenPriv->dri2.enabled) {
- radeon_update_renderbuffers(driContextPriv, driDrawPriv);
- if (driDrawPriv != driReadPriv)
- radeon_update_renderbuffers(driContextPriv, driReadPriv);
- radeon->state.color.rrb =
- (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- radeon->state.depth.rrb =
- (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer;
- }
-
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx);
-
- driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
- if (driReadPriv != driDrawPriv)
- driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
-
- if (!driContextPriv->driScreenPriv->dri2.enabled) {
- radeon_make_renderbuffer_current(radeon, dfb);
- }
-
- _mesa_make_current(radeon->glCtx, dfb, rfb);
-
- if (radeon->dri.drawable != driDrawPriv) {
- if (driDrawPriv->swap_interval == (unsigned)-1) {
- driDrawPriv->vblFlags =
- (radeon->radeonScreen->irq != 0)
- ? driGetDefaultVBlankFlags(&radeon->
- optionCache)
- : VBLANK_FLAG_NO_IRQ;
-
- driDrawableInitVBlank(driDrawPriv);
- }
- }
-
- radeon->dri.readable = driReadPriv;
-
- if (radeon->dri.drawable != driDrawPriv ||
- radeon->lastStamp != driDrawPriv->lastStamp) {
- radeon->dri.drawable = driDrawPriv;
-
- radeonSetCliprects(radeon);
- r300UpdateViewportOffset(radeon->glCtx);
- }
-
- _mesa_update_state(radeon->glCtx);
-
- if (!driContextPriv->driScreenPriv->dri2.enabled) {
- radeonUpdatePageFlipping(radeon);
- }
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "End %s\n", __FUNCTION__);
- return GL_TRUE;
-}
-
/* Force the context `c' to be unbound from its buffer.
*/
GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
const char *function,
int line);
+#define CP_PACKET2 (2 << 30)
+#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
+#define CP_PACKET3( pkt, n ) \
+ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
/**
* Every function writing to the command buffer needs to declare this
#define R200_FALLBACK_DISABLE 0x10
#define R200_FALLBACK_BORDER_MODE 0x20
+#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
+#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
+#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
+#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
+#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
+#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
+#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
+#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
+#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
+
/* The blit width for texture uploads
*/
#define BLIT_WIDTH_BYTES 1024
int aos_size;
};
+struct radeon_aos {
+ struct radeon_bo *bo; /** Buffer object where vertex data is stored */
+ int offset; /** Offset into buffer object, in bytes */
+ int components; /** Number of components per vertex */
+ int stride; /** Stride in dwords (may be 0 for repeating) */
+ int count; /** Number of vertices */
+};
struct radeon_dma {
/* Active dma region. Allocations for vertices and retained
#include "drirenderbuffer.h"
#include "vblank.h"
+#include "xmlpool.h" /* for symbolic values of enum-type options */
#include "radeon_bo.h"
#include "radeon_cs.h"
#include "common_lock.h"
#include "common_cmdbuf.h"
+#define DRIVER_DATE "20090101"
+
#ifndef RADEON_DEBUG
int RADEON_DEBUG = (0);
#endif
}
radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line);
}
+
+
+
+/* Return various strings for glGetString().
+ */
+static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
+{
+ radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+ static char buffer[128];
+
+ switch (name) {
+ case GL_VENDOR:
+ if (IS_R300_CLASS(radeon->radeonScreen))
+ return (GLubyte *) "DRI R300 Project";
+ else
+ return (GLubyte *) "Tungsten Graphics, Inc.";
+
+ case GL_RENDERER:
+ {
+ unsigned offset;
+ GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
+ radeon->radeonScreen->AGPMode;
+ const char* chipname;
+
+
+
+ if (IS_R300_CLASS(radeon->radeonScreen))
+ chipname = "R300";
+ else
+ chipname = "R200";
+
+ offset = driGetRendererString(buffer, chipname, DRIVER_DATE,
+ agp_mode);
+
+ if (IS_R300_CLASS(radeon->radeonScreen)) {
+ sprintf(&buffer[offset], " %sTCL",
+ (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
+ ? "" : "NO-");
+ } else {
+ sprintf(&buffer[offset], " %sTCL",
+ !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
+ ? "" : "NO-");
+ }
+
+ if (radeon->radeonScreen->driScreen->dri2.enabled)
+ strcat(buffer, " DRI2");
+
+ return (GLubyte *) buffer;
+ }
+
+ default:
+ return NULL;
+ }
+}
+
+/* Initialize the driver's misc functions.
+ */
+static void radeonInitDriverFuncs(struct dd_function_table *functions)
+{
+ functions->GetString = radeonGetString;
+}
+
+/**
+ * Create and initialize all common fields of the context,
+ * including the Mesa context itself.
+ */
+GLboolean radeonInitContext(radeonContextPtr radeon,
+ struct dd_function_table* functions,
+ const __GLcontextModes * glVisual,
+ __DRIcontextPrivate * driContextPriv,
+ void *sharedContextPrivate)
+{
+ __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
+ radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
+ GLcontext* ctx;
+ GLcontext* shareCtx;
+ int fthrottle_mode;
+
+ /* Fill in additional standard functions. */
+ radeonInitDriverFuncs(functions);
+
+ radeon->radeonScreen = screen;
+ /* Allocate and initialize the Mesa context */
+ if (sharedContextPrivate)
+ shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
+ else
+ shareCtx = NULL;
+ radeon->glCtx = _mesa_create_context(glVisual, shareCtx,
+ functions, (void *)radeon);
+ if (!radeon->glCtx)
+ return GL_FALSE;
+
+ ctx = radeon->glCtx;
+ driContextPriv->driverPrivate = radeon;
+
+ /* DRI fields */
+ radeon->dri.context = driContextPriv;
+ radeon->dri.screen = sPriv;
+ radeon->dri.drawable = NULL;
+ radeon->dri.readable = NULL;
+ radeon->dri.hwContext = driContextPriv->hHWContext;
+ radeon->dri.hwLock = &sPriv->pSAREA->lock;
+ radeon->dri.fd = sPriv->fd;
+ radeon->dri.drmMinor = sPriv->drm_version.minor;
+
+ radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
+ screen->sarea_priv_offset);
+
+ /* Setup IRQs */
+ fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
+ radeon->iw.irq_seq = -1;
+ radeon->irqsEmitted = 0;
+ radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
+ radeon->radeonScreen->irq);
+
+ radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
+
+ if (!radeon->do_irqs)
+ fprintf(stderr,
+ "IRQ's not enabled, falling back to %s: %d %d\n",
+ radeon->do_usleeps ? "usleeps" : "busy waits",
+ fthrottle_mode, radeon->radeonScreen->irq);
+
+ (*sPriv->systemTime->getUST) (&radeon->swap_ust);
+
+ return GL_TRUE;
+}
+
+/**
+ * Cleanup common context fields.
+ * Called by r200DestroyContext/r300DestroyContext
+ */
+void radeonCleanupContext(radeonContextPtr radeon)
+{
+ FILE *track;
+ struct radeon_renderbuffer *rb;
+ GLframebuffer *fb;
+
+ fb = (void*)radeon->dri.drawable->driverPrivate;
+ rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ if (rb && rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ if (rb && rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+ if (rb && rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ fb = (void*)radeon->dri.readable->driverPrivate;
+ rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ if (rb && rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ if (rb && rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+ if (rb && rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+
+ /* _mesa_destroy_context() might result in calls to functions that
+ * depend on the DriverCtx, so don't set it to NULL before.
+ *
+ * radeon->glCtx->DriverCtx = NULL;
+ */
+
+ /* free the Mesa context */
+ _mesa_destroy_context(radeon->glCtx);
+
+ /* free the option cache */
+ driDestroyOptionCache(&radeon->optionCache);
+
+ if (radeon->state.scissor.pClipRects) {
+ FREE(radeon->state.scissor.pClipRects);
+ radeon->state.scissor.pClipRects = 0;
+ }
+ track = fopen("/tmp/tracklog", "w");
+ if (track) {
+ radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
+ fclose(track);
+ }
+}
+
+void
+radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
+ GLframebuffer *draw)
+{
+ /* if radeon->fake */
+ struct radeon_renderbuffer *rb;
+
+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+
+ if (!rb->bo) {
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->frontOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
+ }
+ rb->cpp = radeon->radeonScreen->cpp;
+ rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+ if (!rb->bo) {
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->backOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
+ }
+ rb->cpp = radeon->radeonScreen->cpp;
+ rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+ if (!rb->bo) {
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->depthOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
+ }
+ rb->cpp = radeon->radeonScreen->cpp;
+ rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
+ }
+}
+
+static void
+radeon_make_renderbuffer_current(radeonContextPtr radeon,
+ GLframebuffer *draw)
+{
+ int size = 4096*4096*4;
+ /* if radeon->fake */
+ struct radeon_renderbuffer *rb;
+
+ if (radeon->radeonScreen->kernel_mm) {
+ radeon_make_kernel_renderbuffer_current(radeon, draw);
+ return;
+ }
+
+
+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+ if (!rb->bo) {
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->frontOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
+ }
+ rb->cpp = radeon->radeonScreen->cpp;
+ rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+ if (!rb->bo) {
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->backOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
+ }
+ rb->cpp = radeon->radeonScreen->cpp;
+ rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+ if (!rb->bo) {
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->depthOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
+ }
+ rb->cpp = radeon->radeonScreen->cpp;
+ rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
+ }
+}
+
+
+void
+radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
+{
+ unsigned int attachments[10];
+ __DRIbuffer *buffers;
+ __DRIscreen *screen;
+ struct radeon_renderbuffer *rb;
+ int i, count;
+ GLframebuffer *draw;
+ radeonContextPtr radeon;
+
+ draw = drawable->driverPrivate;
+ screen = context->driScreenPriv;
+ radeon = (radeonContextPtr) context->driverPrivate;
+ i = 0;
+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+ attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+ attachments[i++] = __DRI_BUFFER_BACK_LEFT;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+ attachments[i++] = __DRI_BUFFER_DEPTH;
+ }
+
+ buffers = (*screen->dri2.loader->getBuffers)(drawable,
+ &drawable->w,
+ &drawable->h,
+ attachments, i,
+ &count,
+ drawable->loaderPrivate);
+ if (buffers == NULL)
+ return;
+
+ /* set one cliprect to cover the whole drawable */
+ drawable->x = 0;
+ drawable->y = 0;
+ drawable->backX = 0;
+ drawable->backY = 0;
+ drawable->numClipRects = 1;
+ drawable->pClipRects[0].x1 = 0;
+ drawable->pClipRects[0].y1 = 0;
+ drawable->pClipRects[0].x2 = drawable->w;
+ drawable->pClipRects[0].y2 = drawable->h;
+ drawable->numBackClipRects = 1;
+ drawable->pBackClipRects[0].x1 = 0;
+ drawable->pBackClipRects[0].y1 = 0;
+ drawable->pBackClipRects[0].x2 = drawable->w;
+ drawable->pBackClipRects[0].y2 = drawable->h;
+ for (i = 0; i < count; i++) {
+ switch (buffers[i].attachment) {
+ case __DRI_BUFFER_FRONT_LEFT:
+ rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ if (rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb->cpp = buffers[i].cpp;
+ rb->pitch = buffers[i].pitch;
+ rb->width = drawable->w;
+ rb->height = drawable->h;
+ rb->has_surface = 0;
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags);
+ if (rb->bo == NULL) {
+ fprintf(stderr, "failled to attach front %d\n",
+ buffers[i].name);
+ }
+ break;
+ case __DRI_BUFFER_BACK_LEFT:
+ rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ if (rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb->cpp = buffers[i].cpp;
+ rb->pitch = buffers[i].pitch;
+ rb->width = drawable->w;
+ rb->height = drawable->h;
+ rb->has_surface = 0;
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags);
+ break;
+ case __DRI_BUFFER_DEPTH:
+ rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer;
+ if (rb->bo) {
+ radeon_bo_unref(rb->bo);
+ rb->bo = NULL;
+ }
+ rb->cpp = buffers[i].cpp;
+ rb->pitch = buffers[i].pitch;
+ rb->width = drawable->w;
+ rb->height = drawable->h;
+ rb->has_surface = 0;
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags);
+ break;
+ case __DRI_BUFFER_STENCIL:
+ break;
+ case __DRI_BUFFER_ACCUM:
+ default:
+ fprintf(stderr,
+ "unhandled buffer attach event, attacment type %d\n",
+ buffers[i].attachment);
+ return;
+ }
+ }
+ radeon = (radeonContextPtr) context->driverPrivate;
+ driUpdateFramebufferSize(radeon->glCtx, drawable);
+}
+
+/* Force the context `c' to be the current context and associate with it
+ * buffer `b'.
+ */
+GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
+ __DRIdrawablePrivate * driDrawPriv,
+ __DRIdrawablePrivate * driReadPriv)
+{
+ radeonContextPtr radeon;
+ GLframebuffer *dfb, *rfb;
+
+ if (!driContextPriv) {
+ if (RADEON_DEBUG & DEBUG_DRI)
+ fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
+ _mesa_make_current(NULL, NULL, NULL);
+ return GL_TRUE;
+ }
+ radeon = (radeonContextPtr) driContextPriv->driverPrivate;
+ dfb = driDrawPriv->driverPrivate;
+ rfb = driReadPriv->driverPrivate;
+
+ if (driContextPriv->driScreenPriv->dri2.enabled) {
+ radeon_update_renderbuffers(driContextPriv, driDrawPriv);
+ if (driDrawPriv != driReadPriv)
+ radeon_update_renderbuffers(driContextPriv, driReadPriv);
+ radeon->state.color.rrb =
+ (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ radeon->state.depth.rrb =
+ (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer;
+ }
+
+
+ if (RADEON_DEBUG & DEBUG_DRI)
+ fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx);
+
+ driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
+ if (driReadPriv != driDrawPriv)
+ driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
+
+ if (!driContextPriv->driScreenPriv->dri2.enabled) {
+ radeon_make_renderbuffer_current(radeon, dfb);
+ }
+
+ _mesa_make_current(radeon->glCtx, dfb, rfb);
+
+ if (radeon->dri.drawable != driDrawPriv) {
+ if (driDrawPriv->swap_interval == (unsigned)-1) {
+ driDrawPriv->vblFlags =
+ (radeon->radeonScreen->irq != 0)
+ ? driGetDefaultVBlankFlags(&radeon->
+ optionCache)
+ : VBLANK_FLAG_NO_IRQ;
+
+ driDrawableInitVBlank(driDrawPriv);
+ }
+ }
+
+ radeon->dri.readable = driReadPriv;
+
+ if (radeon->dri.drawable != driDrawPriv ||
+ radeon->lastStamp != driDrawPriv->lastStamp) {
+ radeon->dri.drawable = driDrawPriv;
+
+ radeonSetCliprects(radeon);
+ radeon->vtbl.update_viewport_offset(radeon->glCtx);
+ }
+
+ _mesa_update_state(radeon->glCtx);
+
+ if (!driContextPriv->driScreenPriv->dri2.enabled) {
+ radeonUpdatePageFlipping(radeon);
+ }
+
+ if (RADEON_DEBUG & DEBUG_DRI)
+ fprintf(stderr, "End %s\n", __FUNCTION__);
+ return GL_TRUE;
+}
+
+
+#if defined(USE_X86_ASM)
+#define COPY_DWORDS( dst, src, nr ) \
+do { \
+ int __tmp; \
+ __asm__ __volatile__( "rep ; movsl" \
+ : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \
+ : "0" (nr), \
+ "D" ((long)dst), \
+ "S" ((long)src) ); \
+} while (0)
+#else
+#define COPY_DWORDS( dst, src, nr ) \
+do { \
+ int j; \
+ for ( j = 0 ; j < nr ; j++ ) \
+ dst[j] = ((int *)src)[j]; \
+ dst += nr; \
+} while (0)
+#endif
+
+static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count)
+{
+ int i;
+
+ if (RADEON_DEBUG & DEBUG_VERTS)
+ fprintf(stderr, "%s count %d stride %d out %p data %p\n",
+ __FUNCTION__, count, stride, (void *)out, (void *)data);
+
+ if (stride == 4)
+ COPY_DWORDS(out, data, count);
+ else
+ for (i = 0; i < count; i++) {
+ out[0] = *(int *)data;
+ out++;
+ data += stride;
+ }
+}
+
+static void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count)
+{
+ int i;
+
+ if (RADEON_DEBUG & DEBUG_VERTS)
+ fprintf(stderr, "%s count %d stride %d out %p data %p\n",
+ __FUNCTION__, count, stride, (void *)out, (void *)data);
+
+ if (stride == 8)
+ COPY_DWORDS(out, data, count * 2);
+ else
+ for (i = 0; i < count; i++) {
+ out[0] = *(int *)data;
+ out[1] = *(int *)(data + 4);
+ out += 2;
+ data += stride;
+ }
+}
+
+static void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count)
+{
+ int i;
+
+ if (RADEON_DEBUG & DEBUG_VERTS)
+ fprintf(stderr, "%s count %d stride %d out %p data %p\n",
+ __FUNCTION__, count, stride, (void *)out, (void *)data);
+
+ if (stride == 12) {
+ COPY_DWORDS(out, data, count * 3);
+ }
+ else
+ for (i = 0; i < count; i++) {
+ out[0] = *(int *)data;
+ out[1] = *(int *)(data + 4);
+ out[2] = *(int *)(data + 8);
+ out += 3;
+ data += stride;
+ }
+}
+
+static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count)
+{
+ int i;
+
+ if (RADEON_DEBUG & DEBUG_VERTS)
+ fprintf(stderr, "%s count %d stride %d out %p data %p\n",
+ __FUNCTION__, count, stride, (void *)out, (void *)data);
+
+ if (stride == 16)
+ COPY_DWORDS(out, data, count * 4);
+ else
+ for (i = 0; i < count; i++) {
+ out[0] = *(int *)data;
+ out[1] = *(int *)(data + 4);
+ out[2] = *(int *)(data + 8);
+ out[3] = *(int *)(data + 12);
+ out += 4;
+ data += stride;
+ }
+}
+
+void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos,
+ GLvoid * data, int size, int stride, int count)
+{
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ uint32_t *out;
+ uint32_t bo_size;
+
+ memset(aos, 0, sizeof(struct radeon_aos));
+ if (stride == 0) {
+ bo_size = size * 4;
+ count = 1;
+ aos->stride = 0;
+ } else {
+ bo_size = size * count * 4;
+ aos->stride = size;
+ }
+ aos->bo = radeon_bo_open(rmesa->radeonScreen->bom,
+ 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0);
+ aos->offset = 0;
+ aos->components = size;
+ aos->count = count;
+
+ radeon_bo_map(aos->bo, 1);
+ out = (uint32_t*)((char*)aos->bo->ptr + aos->offset);
+ switch (size) {
+ case 1: radeonEmitVec4(out, data, stride, count); break;
+ case 2: radeonEmitVec8(out, data, stride, count); break;
+ case 3: radeonEmitVec12(out, data, stride, count); break;
+ case 4: radeonEmitVec16(out, data, stride, count); break;
+ default:
+ assert(0);
+ break;
+ }
+ radeon_bo_unmap(aos->bo);
+}
void radeonUpdatePageFlipping(radeonContextPtr rmesa);
+GLboolean radeonInitContext(radeonContextPtr radeon,
+ struct dd_function_table* functions,
+ const __GLcontextModes * glVisual,
+ __DRIcontextPrivate * driContextPriv,
+ void *sharedContextPrivate);
+
+void radeonCleanupContext(radeonContextPtr radeon);
+void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
+GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
+ __DRIdrawablePrivate * driDrawPriv,
+ __DRIdrawablePrivate * driReadPriv);
+
+void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos,
+ GLvoid * data, int size, int stride, int count);
#endif
radeonFlushCmdBuf( rmesa, __FUNCTION__ );
}
+ radeonCleanupContext(&rmesa->radeon);
_mesa_vector4f_free( &rmesa->tcl.ObjClean );
if (rmesa->radeon.state.scissor.pClipRects) {
assert( is_empty_list( & rmesa->radeon.swapped ) );
}
- /* free the Mesa context */
- rmesa->radeon.glCtx->DriverCtx = NULL;
- _mesa_destroy_context( rmesa->radeon.glCtx );
-
- /* free the option cache */
- driDestroyOptionCache (&rmesa->radeon.optionCache);
+ radeonCleanupContext(&rmesa->radeon);
FREE( rmesa );
}
}
-/* Make context `c' the current context and bind it to the given
- * drawing and reading surfaces.
- */
-GLboolean
-radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv )
-{
- if ( driContextPriv ) {
- radeonContextPtr newCtx =
- (radeonContextPtr) driContextPriv->driverPrivate;
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
-
- newCtx->dri.readable = driReadPriv;
-
- if ( (newCtx->dri.drawable != driDrawPriv) ||
- newCtx->lastStamp != driDrawPriv->lastStamp ) {
- if (driDrawPriv->swap_interval == (unsigned)-1) {
- driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0)
- ? driGetDefaultVBlankFlags(&newCtx->optionCache)
- : VBLANK_FLAG_NO_IRQ;
-
- driDrawableInitVBlank( driDrawPriv );
- }
-
- newCtx->dri.drawable = driDrawPriv;
-
- radeonSetCliprects(newCtx);
- radeonUpdateViewportOffset( newCtx->glCtx );
- }
-
- _mesa_make_current( newCtx->glCtx,
- (GLframebuffer *) driDrawPriv->driverPrivate,
- (GLframebuffer *) driReadPriv->driverPrivate );
-
- _mesa_update_state( newCtx->glCtx );
- } else {
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
- _mesa_make_current( NULL, NULL, NULL );
- }
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "End %s\n", __FUNCTION__);
- return GL_TRUE;
-}
/* Force the context `c' to be unbound from its buffer.
*/
#include "radeon_bo_legacy.h"
#include "radeon_bo_gem.h"
+#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
+DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
+ DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
+ DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
+DRI_CONF_OPT_END
+
#if !RADEON_COMMON /* R100 */
PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
DRI_CONF_HYPERZ(false)
+ DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 14;
+static const GLuint __driNConfigOptions = 15;
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
DRI_CONF_HYPERZ(false)
+ DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 16;
+static const GLuint __driNConfigOptions = 17;
extern const struct dri_extension blend_extensions[];
extern const struct dri_extension ARB_vp_extension[];
DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
DRI_CONF_OPT_END
-#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
-DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
- DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
- DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
-DRI_CONF_OPT_END
+
#define DRI_CONF_DISABLE_S3TC(def) \
DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
return GL_TRUE;
}
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
static GLboolean
radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
GLenum intFormat, GLuint w, GLuint h)
return (driDrawPriv->driverPrivate != NULL);
}
-#else
-
-/**
- * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
- *
- * \todo This function (and its interface) will need to be updated to support
- * pbuffers.
- */
-static GLboolean
-radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
- __DRIdrawablePrivate *driDrawPriv,
- const __GLcontextModes *mesaVis,
- GLboolean isPixmap )
-{
- radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
-
- if (isPixmap) {
- return GL_FALSE; /* not implemented */
- }
- else {
- const GLboolean swDepth = GL_FALSE;
- const GLboolean swAlpha = GL_FALSE;
- const GLboolean swAccum = mesaVis->accumRedBits > 0;
- const GLboolean swStencil = mesaVis->stencilBits > 0 &&
- mesaVis->depthBits != 24;
- struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
-
- /* front color renderbuffer */
- {
- driRenderbuffer *frontRb
- = driNewRenderbuffer(GL_RGBA,
- driScrnPriv->pFB + screen->frontOffset,
- screen->cpp,
- screen->frontOffset, screen->frontPitch,
- driDrawPriv);
- radeonSetSpanFunctions(frontRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
- }
-
- /* back color renderbuffer */
- if (mesaVis->doubleBufferMode) {
- driRenderbuffer *backRb
- = driNewRenderbuffer(GL_RGBA,
- driScrnPriv->pFB + screen->backOffset,
- screen->cpp,
- screen->backOffset, screen->backPitch,
- driDrawPriv);
- radeonSetSpanFunctions(backRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
- }
-
- /* depth renderbuffer */
- if (mesaVis->depthBits == 16) {
- driRenderbuffer *depthRb
- = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
- driScrnPriv->pFB + screen->depthOffset,
- screen->cpp,
- screen->depthOffset, screen->depthPitch,
- driDrawPriv);
- radeonSetSpanFunctions(depthRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- // depthRb->has_surface = screen->depthHasSurface;
- }
- else if (mesaVis->depthBits == 24) {
- driRenderbuffer *depthRb
- = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
- driScrnPriv->pFB + screen->depthOffset,
- screen->cpp,
- screen->depthOffset, screen->depthPitch,
- driDrawPriv);
- radeonSetSpanFunctions(depthRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- // depthRb->has_surface = screen->depthHasSurface;
- }
-
- /* stencil renderbuffer */
- if (mesaVis->stencilBits > 0 && !swStencil) {
- driRenderbuffer *stencilRb
- = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
- driScrnPriv->pFB + screen->depthOffset,
- screen->cpp,
- screen->depthOffset, screen->depthPitch,
- driDrawPriv);
- radeonSetSpanFunctions(stencilRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
- //stencilRb->has_surface = screen->depthHasSurface;
- }
-
- _mesa_add_soft_renderbuffers(fb,
- GL_FALSE, /* color */
- swDepth,
- swStencil,
- swAccum,
- swAlpha,
- GL_FALSE /* aux */);
- driDrawPriv->driverPrivate = (void *) fb;
-
- return (driDrawPriv->driverPrivate != NULL);
- }
-}
-#endif
static void
radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
.CreateBuffer = radeonCreateBuffer,
.DestroyBuffer = radeonDestroyBuffer,
.SwapBuffers = radeonSwapBuffers,
- .MakeCurrent = r200MakeCurrent,
+ .MakeCurrent = radeonMakeCurrent,
.UnbindContext = r200UnbindContext,
.GetSwapInfo = getSwapInfo,
.GetDrawableMSC = driDrawableGetMSC32,
/**
* Plug in the Get/Put routines for the given driRenderbuffer.
*/
-void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
+void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
{
- if (drb->Base.InternalFormat == GL_RGBA) {
- if (vis->redBits == 5 && vis->greenBits == 6
- && vis->blueBits == 5) {
- radeonInitPointers_RGB565(&drb->Base);
- } else {
- radeonInitPointers_ARGB8888(&drb->Base);
- }
- } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
- radeonInitDepthPointers_z16(&drb->Base);
- } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
- radeonInitDepthPointers_z24_s8(&drb->Base);
- } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
- radeonInitStencilPointers_z24_s8(&drb->Base);
+ if (rrb->base.InternalFormat == GL_RGB5) {
+ radeonInitPointers_RGB565(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_RGBA8) {
+ radeonInitPointers_ARGB8888(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) {
+ radeonInitDepthPointers_z16(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) {
+ radeonInitDepthPointers_z24_s8(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
+ radeonInitStencilPointers_z24_s8(&rrb->base);
}
}
extern void radeonInitSpanFuncs(GLcontext * ctx);
-#if COMPILE_R300
extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
-#else
-extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis);
-#endif
#endif
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
- GLfloat xoffset = (GLfloat)dPriv->x;
- GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
+ GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
+ GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
const GLfloat *v = ctx->Viewport._WindowMap.m;
float_ui32_type sx = { v[MAT_SX] };
projects / mesa.git / commitdiff