Add assign PCOUT = P to DSP48E1

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 2731cb454eda64a263690ed9fe2818a37b48eab2..02ce0d61b4e223ed1e733b7abb3e89b6c822f973 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -784,4 +784,6 @@ module DSP48E1 (
         end
     endgenerate
 
+    assign PCOUT = P;
+
 endmodule