- Project Management
- <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
- - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
- <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
- EUR 250
- - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
- - EUR 300
- - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
- - EUR 250
- <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
- EUR 1250
- <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
- <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
- - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
- <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
- <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
- <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
- <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
## Completed but not yet submitted:
+
+TO SORT
+
- <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
- EUR 1600
- EUR 800 shared with [[klehman]]
- EUR 800 shared with [[lkcl]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
- - EUR 500 shared between:
- - EUR 100 [[lkcl]]
- - EUR 325 dmitry
- - EUR 75 maciej
- <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
- EUR 800
- <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
- <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
- <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
- - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
- - EUR 800 shared between:
- - EUR 500 [[lkcl]]
- - EUR 300 [[tplaten]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
- - EUR 5500 shared between:
- - EUR 3850 lkcl
- - EUR 1650 Others
- - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
- - EUR 1600
- - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
- - EUR 600
- <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
- EUR 500
- <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
- <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+submitted 2021-dec-09 but not confirmed paid
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
+ - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
+ - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+ - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+ - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
+
+
### Project 2019-02-012 04sep2020 Core
- <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex