Add support for moxie's mul.x and umul.x instructions

diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index d3331c6f13fcf94efdbb24f856f5961345572ee4..561e8c80205460f8f79c5cbc920575208dcffd23 100644 (file)
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,7 @@
+2014-12-24  Anthony Green  <green@moxielogic.com>
+
+       * interp.c (sim_resume): Add mul.x and umul.x instructions.
+
 2014-12-12  Anthony Green  <green@moxielogic.com>
 
        * interp.c (sim_resume): Add zex instructions.

diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index fdb652850e3f32b8b5a0a86ba930f14ce8b80732..fdd94af859e0ba0044da679e43401d01ef8181c6 100644 (file)
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -622,8 +622,30 @@ sim_resume (sd, step, siggnal)
                cpu.asregs.regs[a] = (int) bv & 0xffff;
              }
              break;
-           case 0x14: /* bad */
-           case 0x15: /* bad */
+           case 0x14: /* mul.x */
+             {
+               int a = (inst >> 4) & 0xf;
+               int b = inst & 0xf;
+               unsigned av = cpu.asregs.regs[a];
+               unsigned bv = cpu.asregs.regs[b];
+               TRACE("mul.x");
+               signed long long r = 
+                 (signed long long) av * (signed long long) bv;
+               cpu.asregs.regs[a] = r >> 32;
+             }
+             break;
+           case 0x15: /* umul.x */
+             {
+               int a = (inst >> 4) & 0xf;
+               int b = inst & 0xf;
+               unsigned av = cpu.asregs.regs[a];
+               unsigned bv = cpu.asregs.regs[b];
+               TRACE("umul.x");
+               unsigned long long r = 
+                 (unsigned long long) av * (unsigned long long) bv;
+               cpu.asregs.regs[a] = r >> 32;
+             }
+             break;
            case 0x16: /* bad */
            case 0x17: /* bad */
            case 0x18: /* bad */