radv/gfx10: disable the TC compat zrange workaround

Unnecessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a6d4e0d0e2132a7dee9dda25c95379ea0b2e565d..b4301c0da1524f2d24ac043666f08519db8d8bc1 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1356,7 +1356,8 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
        uint32_t db_z_info = ds->db_z_info;
        uint32_t db_z_info_reg;
 
-       if (!radv_image_is_tc_compat_htile(image))
+       if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
+           !radv_image_is_tc_compat_htile(image))
                return;
 
        if (!radv_layout_has_htile(image, layout,
@@ -1566,6 +1567,10 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
 {
        struct radeon_cmdbuf *cs = cmd_buffer->cs;
        uint64_t va = radv_buffer_get_va(image->bo);
+
+       if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
+               return;
+
        va += image->offset + image->tc_compat_zrange_offset;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 273078239c46fdda97be66ec1efc389aee7bf09d..9e77dc7cb16037493ed89a3a511cfad0f5d224cc 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -363,6 +363,8 @@ radv_physical_device_init(struct radv_physical_device *device,
        device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
                                  device->rad_info.family == CHIP_RAVEN;
 
+       device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
+
        /* Out-of-order primitive rasterization. */
        device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
                                        device->rad_info.max_se >= 2;

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ccbec36849e9f1f81a07b240f6e89db43b30c390..4d3ed71c23cefbb6e93d2631db00b5b3beaf9f66 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1186,14 +1186,15 @@ radv_image_alloc_dcc(struct radv_image *image)
 }
 
 static void
-radv_image_alloc_htile(struct radv_image *image)
+radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
 {
        image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
 
        /* + 8 for storing the clear values */
        image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
        image->size = image->clear_value_offset + 8;
-       if (radv_image_is_tc_compat_htile(image)) {
+       if (radv_image_is_tc_compat_htile(image) &&
+           device->physical_device->has_tc_compat_zrange_bug) {
                /* Metadata for the TC-compatible HTILE hardware bug which
                 * have to be fixed by updating ZRANGE_PRECISION when doing
                 * fast depth clears to 0.0f.
@@ -1402,7 +1403,7 @@ radv_image_create(VkDevice _device,
                        if (radv_image_can_enable_htile(image) &&
                            !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
                                image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
-                               radv_image_alloc_htile(image);
+                               radv_image_alloc_htile(device, image);
                        } else {
                                radv_image_disable_htile(image);
                        }

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b9ac97249d35bc86e87e7e794d7ee250d89d914b..29809ea53bedb9060a3d347dec326b4600b2d1c5 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -317,6 +317,7 @@ struct radv_physical_device {
        bool has_clear_state;
        bool cpdma_prefetch_writes_memory;
        bool has_scissor_bug;
+       bool has_tc_compat_zrange_bug;
 
        bool has_out_of_order_rast;
        bool out_of_order_rast_allowed;