liteusb: fix imports

diff --git a/misoclib/com/liteusb/core/__init__.py b/misoclib/com/liteusb/core/__init__.py
index a382591ceb4bbc9077e12e605022103d7bd53c1a..42b2ee4b2299f984c4d5d25fffd8164ffd852f7a 100644 (file)
--- a/misoclib/com/liteusb/core/__init__.py
+++ b/misoclib/com/liteusb/core/__init__.py
@@ -1,4 +1,4 @@
-from liteusb.ftdi.uart import FtdiUART
-from liteusb.ftdi.dma import FtdiDMA
-from liteusb.ftdi.com import FtdiCom
-from liteusb.ftdi.crc import FtdiCRC32
\ No newline at end of file
+from misoclib.com.liteusb.frontend.uart import FtdiUART
+from misoclib.com.liteusb.frontend.dma import FtdiDMA
+from misoclib.com.liteusb.core.com import FtdiCom
+from misoclib.com.liteusb.core.crc import FtdiCRC32

diff --git a/misoclib/com/liteusb/core/com.py b/misoclib/com/liteusb/core/com.py
index 86e49099aa84655cb2e3f910a761c11fb41563c8..e016638a80c233df9d0efcf18ebef7fa4106b780 100644 (file)
--- a/misoclib/com/liteusb/core/com.py
+++ b/misoclib/com/liteusb/core/com.py
@@ -1,11 +1,11 @@
 from migen.fhdl.std import *
 from migen.flow.actor import *
 
-from liteusb.ftdi.std import *
-from liteusb.ftdi.crossbar import FtdiCrossbar
-from liteusb.ftdi.packetizer import FtdiPacketizer
-from liteusb.ftdi.depacketizer import FtdiDepacketizer
-from liteusb.ftdi.phy import FtdiPHY
+from misoclib.com.liteusb.common import *
+from misoclib.com.liteusb.frontend.crossbar import FtdiCrossbar
+from misoclib.com.liteusb.core.packetizer import FtdiPacketizer
+from misoclib.com.liteusb.core.depacketizer import FtdiDepacketizer
+from misoclib.com.liteusb.phy.ft2232h import FtdiPHY
 
 class FtdiCom(Module):
        def __init__(self, pads, *ports):

diff --git a/misoclib/com/liteusb/core/crc.py b/misoclib/com/liteusb/core/crc.py
index df34837c96a2c963d859684bbddcebaebfc176f3..26fb76074dfeb92ad38d1852d4cc09a4a82afccb 100644 (file)
--- a/misoclib/com/liteusb/core/crc.py
+++ b/misoclib/com/liteusb/core/crc.py
@@ -1,4 +1,3 @@
-
 from collections import OrderedDict
 from migen.fhdl.std import *
 from migen.genlib.fsm import FSM, NextState
@@ -7,7 +6,7 @@ from migen.genlib.misc import chooser, optree
 from migen.flow.actor import Sink, Source
 from migen.actorlib.fifo import SyncFIFO
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class CRCEngine(Module):
        """Cyclic Redundancy Check Engine

diff --git a/misoclib/com/liteusb/core/depacketizer.py b/misoclib/com/liteusb/core/depacketizer.py
index d1b75a9152e9df47d2b7240567686bca6bae1825..97400df3e44f3ed652f923fae87dc5cf780f0057 100644 (file)
--- a/misoclib/com/liteusb/core/depacketizer.py
+++ b/misoclib/com/liteusb/core/depacketizer.py
@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.actorlib.structuring import *
 from migen.genlib.fsm import FSM, NextState
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiDepacketizer(Module):
        def __init__(self, timeout=10):

diff --git a/misoclib/com/liteusb/core/packetizer.py b/misoclib/com/liteusb/core/packetizer.py
index bba3ab88c053e20cfc4d8eb7615de342f62ffe4d..de9c69ed452ff88029a1ef6dd478322d3358472b 100644 (file)
--- a/misoclib/com/liteusb/core/packetizer.py
+++ b/misoclib/com/liteusb/core/packetizer.py
@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.actorlib.structuring import *
 from migen.genlib.fsm import FSM, NextState
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiPacketizer(Module):
        def __init__(self):

diff --git a/misoclib/com/liteusb/frontend/crossbar.py b/misoclib/com/liteusb/frontend/crossbar.py
index d1771c0491e3a561c8a4a78f6291a37b6df376ff..cc548a43a1f628f698ab9dc8105f03956b448f5c 100644 (file)
--- a/misoclib/com/liteusb/frontend/crossbar.py
+++ b/misoclib/com/liteusb/frontend/crossbar.py
@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.roundrobin import *
 from migen.genlib.record import Record
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiCrossbar(Module):
        def __init__(self, masters, slave=None):

diff --git a/misoclib/com/liteusb/frontend/dma.py b/misoclib/com/liteusb/frontend/dma.py
index 6aff0f0c9ebd1a1f46c4bfa5e8e45949c089d541..bcbbe4fbc63a2447d09b987961906b6c015065e9 100644 (file)
--- a/misoclib/com/liteusb/frontend/dma.py
+++ b/misoclib/com/liteusb/frontend/dma.py
@@ -8,7 +8,7 @@ from migen.genlib.record import Record
 
 from misoclib.mem.sdram.frontend import dma_lasmi
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiDMAWriter(Module, AutoCSR):
        def __init__(self, lasmim):

diff --git a/misoclib/com/liteusb/frontend/uart.py b/misoclib/com/liteusb/frontend/uart.py
index 64833f4cef1e6c818cc70fb8ac190e320b49a095..2712d7b93ba33adae07ce3756403cb399cd955cd 100644 (file)
--- a/misoclib/com/liteusb/frontend/uart.py
+++ b/misoclib/com/liteusb/frontend/uart.py
@@ -3,7 +3,7 @@ from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.genlib.fifo import SyncFIFOBuffered
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiUART(Module, AutoCSR):
        def __init__(self, tag, fifo_depth=64):