freedreno: Add CP_REG_WRITE documentation

Document the first DWORD, which at least for the Vulkan blob on a640
isn't always 2.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>

diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index 86c4ff0c5f3b5e9165e991cfd6cf653ea64dd350..2a00db8ed5b5c3f30573a196a5c185d3501dbbc0 100644 (file)
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -1564,5 +1564,37 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
        </reg32>
 </domain>
 
+<domain name="CP_REG_WRITE" width="32">
+       <enum name="reg_tracker">
+               <doc>
+                       Keep shadow copies of these registers and only set them
+                       when drawing, avoiding redundant writes:
+                       - VPC_CNTL_0
+                       - HLSQ_CONTROL_1_REG
+                       - HLSQ_UNKNOWN_B980
+               </doc>
+               <value name="TRACK_CNTL_REG" value="0x1"/>
+               <doc>
+                       Track RB_RENDER_CNTL, and insert a WFI in the following
+                       situation:
+                       - There is a write that disables binning
+                       - There was a draw with binning left enabled, but in
+                         BYPASS mode
+                       Presumably this is a hang workaround?
+               </doc>
+               <value name="TRACK_RENDER_CNTL" value="0x2"/>
+               <doc>
+                       Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
+                       the data to write is 0. Used by the Vulkan blob with
+                       PC_UNKNOWN_9B07, but this isn't predicated on particular
+                       register(s) like the others.
+               </doc>
+               <value name="UNK_EVENT_WRITE" value="0x4"/>
+       </enum>
+       <reg32 offset="0" name="0">
+               <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
+       </reg32>
+</domain>
+
 </database>
 

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index ff5f723aaf62beb88a0b160612851d6146b82d69..1a4c3d7fd7d10d901fdbb6118a1921f85a4aabca 100644 (file)
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -548,7 +548,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 
    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
-   tu_cs_emit(cs, 0x2);
+   tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
    tu_cs_emit(cs, cntl);
 }

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index a477d5429117d3abe4a5600d1d9835d246c15178..11dc37922163aa5c130f81cecb8e220563388db1 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -317,7 +317,7 @@ update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, b
                cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 
        OUT_PKT7(ring, CP_REG_WRITE, 3);
-       OUT_RING(ring, 0x2);
+       OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
        OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
        OUT_RING(ring, cntl |
                COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |