(no commit message)

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index cf39d4dea0d5d37bc9546918c7b5ea05c0995ab3..64bff0b5b3f864aab3fc8d84fed64bf5a0a4afc8 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -889,7 +889,7 @@ are RESERVED)
 | 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) |
 | 0b0101 | DCT COS table index generation |
 | 0b0110 | DCT half-swap   |
-| 0b0111 | Parallel Reduction |
+| 0b0111 | Parallel Reduction and Prefix Sum |
 | 0b1000 | reserved for svshape2 |
 | 0b1001 | reserved for svshape2 |
 | 0b1010 | reserved |
@@ -914,6 +914,18 @@ to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions
 larger than 32, and in-place Transpose.  Potentially a future v3.1 Prefixed
 instruction, `psvshape`, may extend the capability here.
 
+Programmer's Note: Parallel Reduction Mode is selected by setting `SVRM=7,SVyd=1`.
+Prefix Sum Mode is selected by setting `SVRM=7,SVyd=3`:
+
+```
+    # Vector length of 8.
+    svshape 8, 3, 1, 0x7, 0
+    # activate SVSHAPE0 (prefix-sum lhs) for RA
+    # activate SVSHAPE1 (prefix-sum rhs) for RT and RB
+    svremap 7, 0, 1, 0, 1, 0, 0
+    sv.add *10, *10, *10
+```
+
 *Architectural Resource Allocation note: the SVRM field is carefully
 crafted to allocate two Modes, corresponding to bits 21-23 within the
 instruction being set to the value `0b100`, to `svshape2` (not