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diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index ce77a33084fcc3e85f9198bc0d03e33b5abec485..71112e3bc1195697fd40cc3b5051d327022236f7 100644 (file)
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -218,6 +218,10 @@ struct XilinxSrlPass : public Pass {
                                do {
                                        auto pm = xilinx_srl_pm(module, module->selected_cells());
                                        pm.ud_variable.minlen = minlen;
+                                       // Since `nusers` does not count module ports as a user,
+                                       //   and since `sigmap` does not always make such ports
+                                       //   the canonical signal.. need to maintain a pool these
+                                       //   ourselves
                                        for (auto p : module->ports) {
                                                auto w = module->wire(p);
                                                if (w->port_output)