The width of the instruction didn't match the size of its operands.
2020-06-23 Victor Collod <vcollod@nvidia.com>
* amd64-tdep.c (amd64_analyze_prologue): Fix incorrect comment.
Change-Id: I104ebfe0b3c24bd6a8d0f0c5a791b9676a930a54
+2020-08-06 Victor Collod <vcollod@nvidia.com>
+
+ * amd64-tdep.c (amd64_analyze_prologue): Fix incorrect comment.
+
2020-08-05 Kevin Buettner <kevinb@redhat.com>
* corelow.c (core_target::build_file_mappings): Don't output
return pc + 4;
}
- /* For X32, also check for `movq %esp, %ebp'. */
+ /* For X32, also check for `movl %esp, %ebp'. */
if (gdbarch_ptr_bit (gdbarch) == 32)
{
if (memcmp (buf, mov_esp_ebp_1, 2) == 0