arm: Add a missing "break" in an ARM miscreg decode function.

This change accidentally left out a "break" which gcc found and
complained about.

arch-arm: Implementation of Hardware Breakpoint exception

This change adds in the break based on the assumption that the function
should not fall through that case to the next.

Change-Id: Id728a0c9a504d1b6d231d3fe1e7c5ece05d3ac4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30654
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 86b3aaa947960de5272b03f071ff32f29e838854..2bdbaa48d867628dc48106b491ed615f0694068d 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -201,8 +201,6 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                       return MISCREG_DBGBXVR15;
                 }
                 break;
-            }
-            switch (opc2) {
               case 4:
                 switch (crm) {
                   case 0:
@@ -216,6 +214,7 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                 }
                 break;
             }
+            break;
           case 6:
             switch (crm) {
               case 0: