[libre-riscv-dev] [Bug 268] New: nmigen does not seem to support write-through SRAM
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Fri, 27 Mar 2020 09:50:48 +0000 (09:50 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 27 Mar 2020 09:50:50 +0000 (09:50 +0000)
86/18037aa2b375d36faf1b3ecdf0365674f0a542 [new file with mode: 0644]

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+Date: Fri, 27 Mar 2020 09:50:48 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: new
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
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+Message-ID: <bug-268-13@http.bugs.libre-riscv.org/>
+X-Bugzilla-URL: http://bugs.libre-riscv.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 268] New: nmigen does not seem to support
+ write-through SRAM
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