soc_core/soc_core_args: specify default cpu (vexriscv)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 346175f0cfd86a126f3009fbc81149e39e58d975..1a811ff7ad231a2bcdc87e860707a34660ae5595 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -540,7 +540,7 @@ class SoCCore(Module):
 def soc_core_args(parser):
     # CPU parameters
     parser.add_argument("--cpu-type", default=None,
-                        help="select CPU: {}".format(", ".join(iter(cpu.CPUS.keys()))))
+                        help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
     parser.add_argument("--cpu-variant", default=None,
                         help="select CPU variant, (default=standard)")
     parser.add_argument("--cpu-reset-address", default=None, type=int,