Renamed extend() to extend_xx(), changed most users to extend_u0()

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 390822ed3f9fb382d970acb8b1f496f0ac0fc4e1..2c614178ba5077ca65ca644a4442a77d659aa4bf 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -84,7 +84,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
                                RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
                                if (cell->hasPort(wire->name)) {
                                        sig = sigmap(cell->getPort(wire->name));
-                                       sig.extend(wire->width, false);
+                                       sig.extend_u0(wire->width, false);
                                }
                                port_sigs.push_back(sig);
                        }

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 4a102370b7bc314d7b2a0e350882d60df14f384a..238da2634a9d4b793b3324757cad6e214fe80aa9 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -73,7 +73,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
 {
        if (width <= sig.size()) {
-               sig.extend(width, is_signed);
+               sig.extend_u0(width, is_signed);
                return;
        }
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5c010dabfca9403c4a5e14e46f1621aa3ee2cd18..0e8078df6db12298bc9fc31b98415429f03e41d0 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2590,9 +2590,9 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
        check();
 }
 
-void RTLIL::SigSpec::extend(int width, bool is_signed)
+void RTLIL::SigSpec::extend_xx(int width, bool is_signed)
 {
-       cover("kernel.rtlil.sigspec.extend");
+       cover("kernel.rtlil.sigspec.extend_xx");
 
        pack();
 
@@ -2600,10 +2600,9 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
                remove(width, width_ - width);
        
        if (width_ < width) {
-               RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
-               if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
-                               padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
-                       padding = RTLIL::SigSpec(RTLIL::State::S0);
+               RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
+               if (!is_signed && (padding == RTLIL::State::S1 || padding.wire))
+                       padding = RTLIL::State::S0;
                while (width_ < width)
                        append(padding);
        }
@@ -2619,9 +2618,9 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
                remove(width, width_ - width);
        
        if (width_ < width) {
-               RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
+               RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
                if (!is_signed)
-                       padding = RTLIL::SigSpec(RTLIL::State::S0);
+                       padding = RTLIL::State::S0;
                while (width_ < width)
                        append(padding);
        }

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index efb8e833a24a9340eeff1183ab040e6cbace6542..99831244e49e9762bdf99badfd68b8d47dce3511 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1057,7 +1057,7 @@ public:
        void append(const RTLIL::SigSpec &signal);
        void append_bit(const RTLIL::SigBit &bit);
 
-       void extend(int width, bool is_signed = false);
+       void extend_xx(int width, bool is_signed = false);
        void extend_u0(int width, bool is_signed = false);
 
        RTLIL::SigSpec repeat(int num) const;

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index e01c549694df3827a6393e0c50eb9b3b3f8d5872..68667ef024519d16fc5f3d43fe25f40cb779e995 100644 (file)
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -40,7 +40,7 @@ static std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> exclusive_ctrls;
 
 static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
 {
-       sig.extend(dff_out.size(), false);
+       sig.extend_u0(dff_out.size(), false);
 
        if (sig == dff_out)
                return true;

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 54630682256ed3e93f72051642ab06349f33a243..ccc19620200a2c26b01166f313e7fe12835e474c 100644 (file)
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -85,12 +85,12 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
                        RTLIL::SigSpec data = cell->getPort("\\DATA");
                        RTLIL::SigSpec en = cell->getPort("\\EN");
 
-                       clk.extend(1, false);
-                       clk_enable.extend(1, false);
-                       clk_polarity.extend(1, false);
-                       addr.extend(addr_bits, false);
-                       data.extend(memory->width, false);
-                       en.extend(memory->width, false);
+                       clk.extend_u0(1, false);
+                       clk_enable.extend_u0(1, false);
+                       clk_polarity.extend_u0(1, false);
+                       addr.extend_u0(addr_bits, false);
+                       data.extend_u0(memory->width, false);
+                       en.extend_u0(memory->width, false);
 
                        sig_wr_clk.append(clk);
                        sig_wr_clk_enable.append(clk_enable);
@@ -112,12 +112,12 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
                        RTLIL::SigSpec addr = cell->getPort("\\ADDR");
                        RTLIL::SigSpec data = cell->getPort("\\DATA");
 
-                       clk.extend(1, false);
-                       clk_enable.extend(1, false);
-                       clk_polarity.extend(1, false);
-                       transparent.extend(1, false);
-                       addr.extend(addr_bits, false);
-                       data.extend(memory->width, false);
+                       clk.extend_u0(1, false);
+                       clk_enable.extend_u0(1, false);
+                       clk_polarity.extend_u0(1, false);
+                       transparent.extend_u0(1, false);
+                       addr.extend_u0(addr_bits, false);
+                       data.extend_u0(memory->width, false);
 
                        sig_rd_clk.append(clk);
                        sig_rd_clk_enable.append(clk_enable);

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 1e59f18c10c331c247e2b51fc73a6e339ad586e5..5bac76cf62ea8ec4df0f7a572297038a67937ba3 100644 (file)
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -491,7 +491,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                                if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
                                        cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
                                        RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
-                                       new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+                                       new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
                                        replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y);
                                        goto next_cell;
                                }
@@ -504,7 +504,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        if (new_a.size() == 0) {
                                cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
                                RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S1 : RTLIL::State::S0);
-                               new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+                               new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
                                replace_cell(assign_map, module, cell, "empty", "\\Y", new_y);
                                goto next_cell;
                        }
@@ -560,7 +560,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int());
 
                        if (GetSize(sig_a) < GetSize(sig_y))
-                               sig_a.extend(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
+                               sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
 
                        for (int i = 0; i < GetSize(sig_y); i++) {
                                int idx = i + shift_bits;

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index cd84cfd5bad57e75934f97efd4088de197a96966..0874d0981ae6e0b383afd918052c772be08e007c 100644 (file)
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -262,7 +262,7 @@ struct ProcArstPass : public Pass {
                                                                for (auto &chunk : act.first.chunks())
                                                                        if (chunk.wire && chunk.wire->attributes.count("\\init")) {
                                                                                RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
-                                                                               value.extend(chunk.wire->width, false);
+                                                                               value.extend_xx(chunk.wire->width, false);
                                                                                arst_sig.append(chunk);
                                                                                arst_val.append(value.extract(chunk.offset, chunk.width));
                                                                        }

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 46ebdb8460087e07d45d70f3396aea0a99d505a4..b012bc6a4a0cba279105a52f1d72b86139a86d7b 100644 (file)
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -607,7 +607,7 @@ struct ExposePass : public Pass {
                                                        RTLIL::SigSpec sig;
                                                        if (cell->hasPort(p->name))
                                                                sig = cell->getPort(p->name);
-                                                       sig.extend(w->width);
+                                                       sig.extend_u0(w->width);
                                                        if (w->port_input)
                                                                module->connect(RTLIL::SigSig(sig, w));
                                                        else

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 2e297a2c68980f71bc8a13d903b5bc04283a7d17..dcffed94d32b14c36f9e7c0d27042eee973c7f0d 100644 (file)
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -501,7 +501,7 @@ struct AlumaccWorker
                                if (GetSize(sig) > 1)
                                        sig = module->ReduceOr(NEW_ID, sig);
 
-                               sig.extend(GetSize(cmp_y));
+                               sig.extend_u0(GetSize(cmp_y));
                                module->connect(cmp_y, sig);
                        }
 

diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index c487cc36a1087d5eac8a9de2803111bd061ce79e..ffbd6289d05bd9cf9db69a7b3be29bec422a6c05 100644 (file)
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -49,7 +49,7 @@ struct MaccmapWorker
 
        void add(RTLIL::SigSpec a, bool is_signed, bool do_subtract)
        {
-               a.extend(width, is_signed);
+               a.extend_u0(width, is_signed);
 
                if (do_subtract) {
                        a = module->Not(NEW_ID, a);
@@ -65,10 +65,10 @@ struct MaccmapWorker
                if (GetSize(a) < GetSize(b))
                        std::swap(a, b);
 
-               a.extend(width, is_signed);
+               a.extend_u0(width, is_signed);
 
                if (GetSize(b) > width)
-                       b.extend(width, is_signed);
+                       b.extend_u0(width, is_signed);
 
                for (int i = 0; i < GetSize(b); i++)
                        if (is_signed && i+1 == GetSize(b))

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 2dcb5f3eb87ae28708e0127a0700db3177575914..c1c0f76a8c7794283be087f6457b47110712f490 100644 (file)
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -32,7 +32,7 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
        RTLIL::SigSpec sig_a = cell->getPort("\\A");
        RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-       sig_a.extend(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+       sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
        for (int i = 0; i < GetSize(sig_y); i++) {
                RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");