add instruction flen detection

diff --git a/id_regs.py b/id_regs.py
index d8b587ae81b3052ad8c2d8ecc3000b659752f8b0..7e9dda08f62fea409a395b99ce2c42b40bddf791 100644 (file)
--- a/id_regs.py
+++ b/id_regs.py
@@ -55,7 +55,8 @@ floatmask = (1<<len(allfloats)-1)
 allints = intpatterns + cintpatterns[2:] # skip the WRITE_RVC_xx ones
 
 skip = '#define USING_NOREGS\n' \
-       '#define REGS_PATTERN 0x0\n'
+       '#define REGS_PATTERN 0x0\n' \
+       '#define INSN_FLEN 0\n'
 
 # this matches the order of the 5 predication arguments to
 drlookup = { 'rd': 0, 'frd': 0, 'rs1': 1, 'rs2': 2, 'rs3': 3,
@@ -79,6 +80,13 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
     with open(fname) as f:
         f = f.read()
         dest_reg = None
+        flen = 0
+        if "f128(" in f:
+            flen = 128
+        elif "f64(" in f:
+            flen = 64
+        elif "f32(" in f:
+            flen = 32
         for pattern in patterns:
             x = f.find(pattern)
             if x == -1:
@@ -127,6 +135,7 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
     if not res:
         return skip
     res.append('#define REGS_PATTERN 0x%x' % isintfloat)
+    res.append('#define INSN_FLEN %d' % flen)
 
     predargs = ['dest_pred'] * 5
     if immed_offset: # C.LWSP

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 738d3b42a52f94539180845293e126f17d88363f..6309c412d0eefc86494506667d1a48ec0a777451 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -63,7 +63,8 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t target_pred = ~0x0;
   bool zeroingtarg = false;
 #endif
-  sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen, PRED_ARGS, OFFS_ARGS,
+  sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen, INSN_FLEN,
+                 PRED_ARGS, OFFS_ARGS,
 #ifdef INSN_TYPE_SIGNED
                  true
 #else

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 5cfc4c08c0a9b39b257f424a0703d9650e337760..18a4e7c52f028140b56f2a4cd5c9c628dd2fb01d 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -21,13 +21,13 @@ uint8_t maxelwidth(uint8_t wid1, uint8_t wid2)
 }
 
 sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
-            insn_bits_t bits, unsigned int f, int _xlen,
+            insn_bits_t bits, unsigned int f, int _xlen, int _flen,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
             int *o_imm,
             bool _sign) :
-            insn_t(bits), p(pr), src_bitwidth(0), xlen(_xlen),
+            insn_t(bits), p(pr), src_bitwidth(0), xlen(_xlen), flen(_flen),
             sv_enabled(_sv_enabled), signextended(_sign),
             vloop_continue(false),
             at_least_one_reg_vectorised(false), fimap(f),

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 7102dd9cebc0aff7d7a6e861957c6b95876375dc..d449bc7c42317a4e1263bc94aa02a818cfb2abdc 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -38,7 +38,7 @@ class sv_insn_t: public insn_t
 {
 public:
   sv_insn_t(processor_t *pr, bool _sv_enabled, insn_bits_t bits, unsigned int f,
-            int xlen,
+            int xlen, int flen,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
@@ -102,6 +102,7 @@ public:
   processor_t *p;
   uint8_t src_bitwidth;
   int xlen;
+  int flen;
   bool sv_enabled;
   bool signextended;