bit of a mess being sorted out

1) update to this page was inconsistent: now fixed
   https://libre-soc.org/openpower/sv/bitmanip/
2) power_decoder.py bitsel for minor_22.csv had been set to (1,5) which
   is *only four bits* (LSB0 numbering, python-style) 1 2 3 4
   where what was actually needed was (1,6) to be bits (MSB0) 26..30
3) when converting to "ignore" format (previous: 0b00000 new 000000-)
   and adding the extra bit, (2) messed things up.
   bitsel has now been set to (0,6) which is bits 0 1 2 3 4 5
   aka (MSB0) 26..31 and the four instructions setvl/svremap/svshap/svstep
   set to 10011- and 011001 etc. as appropriate
4) the minor_22.csv entries for both svshape and svremap were set to
   Rc=1 mode which is NOT correct

astoundingly the unit tests all functioned correctly despite the above
errors.  now all corrected, unit test test_caller_setvl.py still functions

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 9fc38e024d34b62e4a715dc4299ea9436fdbc4fa..dc71b6bff79a6a795c49ac51f78afe60bc6b878f 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -1,5 +1,5 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
-0b00000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b00001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b00010,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b00011,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+11011-,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+111001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+10011-,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 39ba5f22a46c35ed3824faacb9bad8c96d43f396..72fc85c9f1276f7cecde43e50f4ce5f5d5c2a38d 100644 (file)
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -735,7 +735,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
         Subdecoder(pattern=62, opcodes=get_csv("minor_62.csv"),
                    opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]),
         Subdecoder(pattern=22, opcodes=get_csv("minor_22.csv"),
-                   opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]),
+                   opint=False, bitsel=(0, 6), suffix=None, subdecoders=[]),
         Subdecoder(pattern=5, opcodes=get_csv("minor_5.csv"),
                    opint=True, bitsel=(0, 11), suffix=None, subdecoders=[]),
     ]

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index cebf32e41f39c706b0b7cb32fa53f72480a66884..e456d031a2be29e7ab8e633a07ffc003b06bd4c6 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -205,7 +205,7 @@ class SVP64Asm:
             insn |= fields[3] << (31-25)  # vf       , bit  25
             insn |= fields[4] << (31-24)  # vs       , bit  24
             insn |= fields[5] << (31-23)  # ms       , bit  23
-            insn |= 0b00000 << (31-30)  # XO       , bits 26..30
+            insn |= 0b11011 << (31-30)    # XO       , bits 26..30
             if opcode == 'setvl.':
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
             log("setvl", bin(insn))
@@ -228,7 +228,7 @@ class SVP64Asm:
             insn |= fields[0] << (31-10)  # RT       , bits 6-10
             insn |= (fields[1]-1) << (31-22)  # SVi      , bits 16-22
             insn |= fields[2] << (31-25)  # vf       , bit  25
-            insn |= 0b00011 << (31-30)  # XO       , bits 26..30
+            insn |= 0b10011 << (31-30)    # XO       , bits 26..30
             if opcode == 'svstep.':
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
             log("svstep", bin(insn))
@@ -252,7 +252,7 @@ class SVP64Asm:
             insn |= (fields[2]-1) << (31-20)  # SVzd       , bits 16-20
             insn |= (fields[3]) << (31-24)  # SVRM       , bits 21-24
             insn |= (fields[4]) << (31-25)  # vf         , bits 25
-            insn |= 0b00001 << (31-30)  # XO       , bits 26..30
+            insn |= 0b011001 << (31-31)  # XO       , bits 26..31
             #insn &= ((1<<32)-1)
             log("svshape", bin(insn))
             yield ".long 0x%x" % insn
@@ -277,8 +277,7 @@ class SVP64Asm:
             insn |= fields[4] << (31-18)  # m00        , bits 17-18
             insn |= fields[5] << (31-20)  # m01        , bits 19-20
             insn |= fields[6] << (31-21)  # pst        , bit 21
-            insn |= 0b00010 << (31-30)  # XO       , bits 26..30
-            #insn &= ((1<<32)-1)
+            insn |= 0b111001 << (31-31)   # XO       , bits 26..31
             log("svremap", bin(insn))
             yield ".long 0x%x" % insn
             return
@@ -1112,7 +1111,7 @@ class SVP64Asm:
             insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
             insn |= int(v30b_newfields[1]) << (31-22)  # SVi      , bits 16-22
             insn |= int(v30b_newfields[2]) << (31-25)  # vf       , bit  25
-            insn |= 0b00011 << (31-30)  # XO       , bits 26..30
+            insn |= 0b10011 << (31-30)  # XO       , bits 26..30
             if opcode == 'svstep.':
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
             log("svstep", bin(insn))