Move shregmap until after first techmap

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 280c6b729975a855b9373824703c0fe5cb0a83dc..ce597ea4a7a433ce0bd691899185c328af0f2d24 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -103,9 +103,9 @@ struct SynthXilinxPass : public Pass
                log("        memory_map\n");
                log("        dffsr2dff\n");
                log("        dff2dffe\n");
-               log("        shregmap -init\n");
                log("        opt -full\n");
                log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
+               log("        shregmap -init -params -enpol any_or_none\n");
                log("        opt -fast\n");
                log("\n");
                log("    map_luts:\n");
@@ -223,9 +223,9 @@ struct SynthXilinxPass : public Pass
                        Pass::call(design, "memory_map");
                        Pass::call(design, "dffsr2dff");
                        Pass::call(design, "dff2dffe");
-                       Pass::call(design, "shregmap -init -params -enpol any_or_none");
                        Pass::call(design, "opt -full");
                        Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
+                       Pass::call(design, "shregmap -init -params -enpol any_or_none");
                        Pass::call(design, "opt -fast");
                }