adapt to migen changes

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index a4ad24d53fff3a6678525c7eb41e047789721d77..51163aa7dd7573f73d1882808acdd04836dc33b2 100644 (file)
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -33,6 +33,7 @@
 #      I M P O R T 
 #==============================================================================
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.fhdl import verilog, autofragment
 from migen.bus import csr
 from migen.bus.transactions import *

diff --git a/examples/de1/top.py b/examples/de1/top.py
index 45b45fc691433140ca0e14ed4dfd0b1f6fd82130..b0daa496590228774730f6c7b2273b2672044b22 100644 (file)
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -33,6 +33,7 @@
 #      I M P O R T 
 #==============================================================================
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.fhdl import verilog, autofragment
 from migen.bus import csr
 from migen.bus.transactions import *

diff --git a/miscope/recorder.py b/miscope/recorder.py
index 16d5fa13139013453475c333996a1ac53b79d70e..04283f2d85d03be613ae726ecbbbe6a949200aaa 100644 (file)
--- a/miscope/recorder.py
+++ b/miscope/recorder.py
@@ -1,9 +1,10 @@
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.bus import csr
 from migen.bank import description, csrgen
 from migen.bank.description import *
-from migen.corelogic.misc import optree
-from migen.corelogic.fsm import *
+from migen.genlib.misc import optree
+from migen.genlib.fsm import *
 
 class Storage:
        # 
@@ -88,7 +89,7 @@ class Storage:
                ]
                comb +=[self.done.eq((self._push_ptr == self._push_ptr_stop) & active_ongoing)]
                
-               return Fragment(comb, sync, memories=[self._mem])
+               return Fragment(comb, sync, specials={self._mem})
 
 class Sequencer:
        # 

diff --git a/miscope/tools/vcd.py b/miscope/tools/vcd.py
index c66811b313a39769fad476f365543053ebf0cf2e..3a44116ad01872d63dfe3b6664444198a3615833 100644 (file)
--- a/miscope/tools/vcd.py
+++ b/miscope/tools/vcd.py
@@ -1,8 +1,7 @@
 import sys
 import datetime
 
-sys.path.append("../../")
-from migScope.tools.conv import *
+from miscope.tools.conv import *
 
 def get_bits(values, width, low, high =None):
        r = []

diff --git a/miscope/trigger.py b/miscope/trigger.py
index 9c0cda3b887dc12da8f3b178531054009a82c71f..55ace7c1a4198731ab3a3b5aa0e195f0ce044a0d 100644 (file)
--- a/miscope/trigger.py
+++ b/miscope/trigger.py
@@ -1,8 +1,9 @@
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.bus import csr
 from migen.bank import description, csrgen
 from migen.bank.description import *
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 
 
 class RegParams:
@@ -233,7 +234,7 @@ class Sum:
                                self.o.eq(self._o)
                ]
                comb += self.get_registers()
-               return Fragment(comb, memories=[self._mem])
+               return Fragment(comb, specials={self._mem})
        
        #
        #Driver