Fix iopadmap for cases where IO pins already have buffers on them

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 4acbf7c0ddb73e96b1bc1983ba61589da9936263..c20081c649aa1b8c74b51b858f45a39fd6c34653 100644 (file)
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -146,10 +146,34 @@ struct IopadmapPass : public Pass {
                for (auto module : design->selected_modules())
                {
                        dict<IdString, pool<int>> skip_wires;
+                       pool<SigBit> skip_wire_bits;
+                       SigMap sigmap(module);
+
+                       for (auto cell : module->cells())
+                       {
+                               if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
+                                       for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
+                                               skip_wire_bits.insert(bit);
+
+                               if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
+                                       for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
+                                               skip_wire_bits.insert(bit);
+
+                               if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
+                                       for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
+                                               skip_wire_bits.insert(bit);
+
+                               if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
+                                       for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
+                                               skip_wire_bits.insert(bit);
+
+                               if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
+                                       for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
+                                               skip_wire_bits.insert(bit);
+                       }
 
                        if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
                        {
-                               SigMap sigmap(module);
                                dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
 
                                for (auto cell : module->cells())
@@ -177,6 +201,9 @@ struct IopadmapPass : public Pass {
                                                if (tbuf_bits.count(mapped_wire_bit) == 0)
                                                        continue;
 
+                                               if (skip_wire_bits.count(mapped_wire_bit))
+                                                       continue;
+
                                                auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
                                                Cell *tbuf_cell = module->cell(tbuf_cache.first);
 
@@ -272,6 +299,13 @@ struct IopadmapPass : public Pass {
                                        skip_bit_indices = skip_wires.at(wire->name);
                                }
 
+                               for (int i = 0; i < GetSize(wire); i++)
+                                       if (skip_wire_bits.count(sigmap(SigBit(wire, i))))
+                                               skip_bit_indices.insert(i);
+
+                               if (GetSize(wire) == GetSize(skip_bit_indices))
+                                       continue;
+
                                if (wire->port_input && !wire->port_output) {
                                        if (inpad_celltype.empty()) {
                                                log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));