########################################################################
#
-# Trace Flags
+# Debug Flags
#
-trace_flags = {}
-def TraceFlag(name, desc=None):
- if name in trace_flags:
+debug_flags = {}
+def DebugFlag(name, desc=None):
+ if name in debug_flags:
raise AttributeError, "Flag %s already specified" % name
- trace_flags[name] = (name, (), desc)
+ debug_flags[name] = (name, (), desc)
+TraceFlag = DebugFlag
def CompoundFlag(name, flags, desc=None):
- if name in trace_flags:
+ if name in debug_flags:
raise AttributeError, "Flag %s already specified" % name
compound = tuple(flags)
- trace_flags[name] = (name, compound, desc)
+ debug_flags[name] = (name, compound, desc)
+Export('DebugFlag')
Export('TraceFlag')
Export('CompoundFlag')
MakeAction(makeEmbeddedSwigInit, Transform("EMBED SW")))
Source(init_file)
-def getFlags(source_flags):
- flagsMap = {}
- flagsList = []
- for s in source_flags:
- val = eval(s.get_contents())
- name, compound, desc = val
- flagsList.append(val)
- flagsMap[name] = bool(compound)
-
- for name, compound, desc in flagsList:
- for flag in compound:
- if flag not in flagsMap:
- raise AttributeError, "Trace flag %s not found" % flag
- if flagsMap[flag]:
- raise AttributeError, \
- "Compound flag can't point to another compound flag"
-
- flagsList.sort()
- return flagsList
-
-
-# Generate traceflags.py
-def traceFlagsPy(target, source, env):
- assert(len(target) == 1)
- code = code_formatter()
-
- allFlags = getFlags(source)
-
- code('basic = [')
- code.indent()
- for flag, compound, desc in allFlags:
- if not compound:
- code("'$flag',")
- code(']')
- code.dedent()
- code()
-
- code('compound = [')
- code.indent()
- code("'All',")
- for flag, compound, desc in allFlags:
- if compound:
- code("'$flag',")
- code("]")
- code.dedent()
- code()
-
- code("all = frozenset(basic + compound)")
- code()
-
- code('compoundMap = {')
- code.indent()
- all = tuple([flag for flag,compound,desc in allFlags if not compound])
- code("'All' : $all,")
- for flag, compound, desc in allFlags:
- if compound:
- code("'$flag' : $compound,")
- code('}')
- code.dedent()
- code()
-
- code('descriptions = {')
- code.indent()
- code("'All' : 'All flags',")
- for flag, compound, desc in allFlags:
- code("'$flag' : '$desc',")
- code("}")
- code.dedent()
-
- code.write(str(target[0]))
+#
+# Handle debug flags
+#
+def makeDebugFlagCC(target, source, env):
+ assert(len(target) == 1 and len(source) == 1)
-def traceFlagsCC(target, source, env):
- assert(len(target) == 1)
+ val = eval(source[0].get_contents())
+ name, compound, desc = val
+ compound = list(sorted(compound))
- allFlags = getFlags(source)
code = code_formatter()
# file header
* DO NOT EDIT THIS FILE! Automatically generated
*/
-#include "base/traceflags.hh"
-
-using namespace Trace;
-
-const char *Trace::flagStrings[] =
-{''')
-
- code.indent()
- # The string array is used by SimpleEnumParam to map the strings
- # provided by the user to enum values.
- for flag, compound, desc in allFlags:
- if not compound:
- code('"$flag",')
-
- code('"All",')
- for flag, compound, desc in allFlags:
- if compound:
- code('"$flag",')
- code.dedent()
-
- code('''\
-};
-
-const int Trace::numFlagStrings = ${{len(allFlags) + 1}};
-
+#include "base/debug.hh"
''')
- # Now define the individual compound flag arrays. There is an array
- # for each compound flag listing the component base flags.
- all = tuple([flag for flag,compound,desc in allFlags if not compound])
- code('static const Flags AllMap[] = {')
- code.indent()
- for flag, compound, desc in allFlags:
- if not compound:
- code('$flag,')
- code.dedent()
- code('};')
+ for flag in compound:
+ code('#include "debug/$flag.hh"')
+ code()
+ code('namespace Debug {')
code()
- for flag, compound, desc in allFlags:
- if not compound:
- continue
- code('static const Flags ${flag}Map[] = {')
+ if not compound:
+ code('SimpleFlag $name("$name", "$desc");')
+ else:
+ code('CompoundFlag $name("$name", "$desc",')
code.indent()
- for flag in compound:
- code('$flag,')
- code('(Flags)-1')
+ last = len(compound) - 1
+ for i,flag in enumerate(compound):
+ if i != last:
+ code('$flag,')
+ else:
+ code('$flag);')
code.dedent()
- code('};')
- code()
- # Finally the compoundFlags[] array maps the compound flags
- # to their individual arrays/
- code('const Flags *Trace::compoundFlags[] = {')
- code.indent()
- code('AllMap,')
- for flag, compound, desc in allFlags:
- if compound:
- code('${flag}Map,')
- # file trailer
- code.dedent()
- code('};')
+ code()
+ code('} // namespace Debug')
code.write(str(target[0]))
-def traceFlagsHH(target, source, env):
- assert(len(target) == 1)
+def makeDebugFlagHH(target, source, env):
+ assert(len(target) == 1 and len(source) == 1)
+
+ val = eval(source[0].get_contents())
+ name, compound, desc = val
- allFlags = getFlags(source)
code = code_formatter()
# file header boilerplate
/*
* DO NOT EDIT THIS FILE!
*
- * Automatically generated from traceflags.py
+ * Automatically generated by SCons
*/
-#ifndef __BASE_TRACE_FLAGS_HH__
-#define __BASE_TRACE_FLAGS_HH__
+#ifndef __DEBUG_${name}_HH__
+#define __DEBUG_${name}_HH__
-namespace Trace {
-
-enum Flags {''')
+namespace Debug {
+''')
- # Generate the enum. Base flags come first, then compound flags.
- idx = 0
- code.indent()
- for flag, compound, desc in allFlags:
- if not compound:
- code('$flag = $idx,')
- idx += 1
+ if compound:
+ code('class CompoundFlag;')
+ code('class SimpleFlag;')
- numBaseFlags = idx
- code('NumFlags = $idx,')
- code.dedent()
- code()
+ if compound:
+ code('extern CompoundFlag $name;')
+ for flag in compound:
+ code('extern SimpleFlag $flag;')
+ else:
+ code('extern SimpleFlag $name;')
- # put a comment in here to separate base from compound flags
code('''
-// The remaining enum values are *not* valid indices for Trace::flags.
-// They are "compound" flags, which correspond to sets of base
-// flags, and are used by changeFlag.''')
-
- code.indent()
- code('All = $idx,')
- idx += 1
- for flag, compound, desc in allFlags:
- if compound:
- code('$flag = $idx,')
- idx += 1
-
- numCompoundFlags = idx - numBaseFlags
- code('NumCompoundFlags = $numCompoundFlags')
- code.dedent()
-
- # trailer boilerplate
- code('''\
-}; // enum Flags
-
-// Array of strings for SimpleEnumParam
-extern const char *flagStrings[];
-extern const int numFlagStrings;
-
-// Array of arraay pointers: for each compound flag, gives the list of
-// base flags to set. Inidividual flag arrays are terminated by -1.
-extern const Flags *compoundFlags[];
-
-} // namespace Trace
+}
-#endif // __BASE_TRACE_FLAGS_HH__
+#endif // __DEBUG_${name}_HH__
''')
code.write(str(target[0]))
-flags = map(Value, trace_flags.values())
-env.Command('base/traceflags.py', flags,
- MakeAction(traceFlagsPy, Transform("TRACING", 0)))
-PySource('m5', 'base/traceflags.py')
+for name,flag in sorted(debug_flags.iteritems()):
+ n, compound, desc = flag
+ assert n == name
-env.Command('base/traceflags.hh', flags,
- MakeAction(traceFlagsHH, Transform("TRACING", 0)))
-env.Command('base/traceflags.cc', flags,
- MakeAction(traceFlagsCC, Transform("TRACING", 0)))
-Source('base/traceflags.cc')
+ env.Command('debug/%s.hh' % name, Value(flag),
+ MakeAction(makeDebugFlagHH, Transform("TRACING", 0)))
+ env.Command('debug/%s.cc' % name, Value(flag),
+ MakeAction(makeDebugFlagCC, Transform("TRACING", 0)))
+ Source('debug/%s.cc' % name)
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Flow.hh"
+#include "debug/Interrupt.hh"
#include "params/AlphaInterrupts.hh"
#include "sim/sim_object.hh"
#include "arch/alpha/osfpal.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Context.hh"
#include "kern/tru64/tru64_syscalls.hh"
#include "sim/system.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Thread.hh"
#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/GDBAcc.hh"
+#include "debug/GDBMisc.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/system.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
+#include "debug/Loader.hh"
#include "mem/physical.hh"
#include "mem/vport.hh"
#include "params/AlphaSystem.hh"
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/TLB.hh"
using namespace std;
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/VtoPhys.hh"
#include "mem/vport.hh"
using namespace std;
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Faults.hh"
namespace ArmISA
{
*/
#include "arch/arm/isa.hh"
+#include "debug/Arm.hh"
+#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "arch/arm/registers.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
+#include "debug/Checkpoint.hh"
class ThreadContext;
class Checkpoint;
#endif
#include "base/cp_annotate.hh"
+#include "debug/Arm.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/nativetrace.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecRegDelta.hh"
#include "params/ArmNativeTrace.hh"
#include "sim/byteswap.hh"
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Predecoder.hh"
namespace ArmISA
{
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/byteswap.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "debug/GDBAcc.hh"
+#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
namespace ArmISA
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/TLB.hh"
+#include "debug/TLBVerbose.hh"
#include "mem/page_table.hh"
#include "params/ArmTLB.hh"
#include "sim/process.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
+#include "debug/Predecoder.hh"
namespace ArmISA
{
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
namespace MipsISA
{
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
+#include "debug/MipsPRA.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "kern/linux/linux.hh"
#include "sim/eventq.hh"
#include "sim/process.hh"
#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/LLSC.hh"
#include "mem/request.hh"
namespace MipsISA
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
+#include "debug/TLB.hh"
#include "mem/page_table.hh"
#include "params/MipsTLB.hh"
#include "sim/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/process_impl.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
class StackTrace;
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Power.hh"
+#include "debug/TLB.hh"
#include "mem/page_table.hh"
#include "params/PowerTLB.hh"
#include "sim/process.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
#include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
#include "params/SparcInterrupts.hh"
#include "sim/sim_object.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/MiscRegs.hh"
+#include "debug/Timer.hh"
namespace SparcISA
{
#include "base/bigint.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
+#include "debug/Sparc.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/process_impl.hh"
#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/GDBRead.hh"
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
namespace SparcISA
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/IPR.hh"
+#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/system.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Quiesce.hh"
+#include "debug/Timer.hh"
#include "sim/system.hh"
using namespace SparcISA;
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/VtoPhys.hh"
#include "mem/vport.hh"
using namespace std;
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
+
#if !FULL_SYSTEM
#include "arch/x86/isa_traits.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#else
#include "arch/x86/tlb.hh"
+#include "debug/Faults.hh"
#endif
namespace X86ISA
#include "arch/x86/insts/microregop.hh"
#include "arch/x86/regs/misc.hh"
#include "base/condcodes.hh"
+#include "debug/X86.hh"
namespace X86ISA
{
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/X86.hh"
namespace X86ISA
{
#include "arch/x86/interrupts.hh"
#include "arch/x86/intmessage.hh"
#include "cpu/base.hh"
+#include "debug/LocalApic.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/pc.hh"
#include "dev/x86/south_bridge.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
+#include "debug/X86.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/nativetrace.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecRegDelta.hh"
#include "params/X86NativeTrace.hh"
#include "sim/byteswap.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/PageTableWalker.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/system.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
+#include "debug/Predecoder.hh"
namespace X86ISA
{
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "debug/Predecoder.hh"
class ThreadContext;
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/process_impl.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
namespace X86ISA
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
+#include "debug/VtoPhys.hh"
#include "sim/fault_fwd.hh"
using namespace std;
#include <sys/types.h>
#include <unistd.h>
+#include <algorithm>
#include <csignal>
+#include <map>
+#include <vector>
#include "base/cprintf.hh"
+#include "base/debug.hh"
+#include "base/misc.hh"
+
+using namespace std;
namespace Debug {
+//
+// This function will cause the process to signal itself with a
+// SIGTRAP which is ignored if not in gdb, but will cause the debugger
+// to break if in gdb.
+//
void
breakpoint()
{
#endif
}
+//
+// Flags for debugging purposes. Primarily for trace.hh
+//
+typedef std::map<string, Flag *> FlagsMap;
+int allFlagsVersion = 0;
+FlagsMap &
+allFlags()
+{
+ static FlagsMap flags;
+ return flags;
+}
+
+Flag *
+findFlag(const std::string &name)
+{
+ FlagsMap::iterator i = allFlags().find(name);
+ if (i == allFlags().end())
+ return NULL;
+ return i->second;
+}
+
+Flag::Flag(const char *name, const char *desc)
+ : _name(name), _desc(desc)
+{
+ pair<FlagsMap::iterator, bool> result =
+ allFlags().insert(make_pair(name, this));
+
+ if (!result.second)
+ panic("Flag %s already defined!", name);
+
+ ++allFlagsVersion;
+}
+
+Flag::~Flag()
+{
+ // should find and remove flag.
+}
+
+void
+CompoundFlag::enable()
+{
+ SimpleFlag::enable();
+ for_each(flags.begin(), flags.end(), mem_fun(&Flag::enable));
+}
+
+void
+CompoundFlag::disable()
+{
+ SimpleFlag::disable();
+ for_each(flags.begin(), flags.end(), mem_fun(&Flag::disable));
+}
+
+struct AllFlags : public Flag
+{
+ AllFlags()
+ : Flag("All", "All Flags")
+ {}
+
+ void
+ enable()
+ {
+ FlagsMap::iterator i = allFlags().begin();
+ FlagsMap::iterator end = allFlags().end();
+ for (; i != end; ++i)
+ if (i->second != this)
+ i->second->enable();
+ }
+
+ void
+ disable()
+ {
+ FlagsMap::iterator i = allFlags().begin();
+ FlagsMap::iterator end = allFlags().end();
+ for (; i != end; ++i)
+ if (i->second != this)
+ i->second->enable();
+ }
+};
+
+AllFlags theAllFlags;
+Flag *const All = &theAllFlags;
+
+bool
+changeFlag(const char *s, bool value)
+{
+ Flag *f = findFlag(s);
+ if (!f)
+ return false;
+
+ if (value)
+ f->enable();
+ else
+ f->disable();
+
+ return true;
+}
+
} // namespace Debug
+
+// add a set of functions that can easily be invoked from gdb
+void
+setDebugFlag(const char *string)
+{
+ Debug::changeFlag(string, true);
+}
+
+void
+clearDebugFlag(const char *string)
+{
+ Debug::changeFlag(string, false);
+}
+
+void
+dumpDebugFlags()
+{
+ using namespace Debug;
+ FlagsMap::iterator i = allFlags().begin();
+ FlagsMap::iterator end = allFlags().end();
+ for (; i != end; ++i) {
+ SimpleFlag *f = dynamic_cast<SimpleFlag *>(i->second);
+ if (f && f->status())
+ cprintf("%s\n", f->name());
+ }
+}
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2010 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#ifndef __BASE_DEBUG_HH__
#define __BASE_DEBUG_HH__
+#include <string>
+#include <vector>
+
namespace Debug {
void breakpoint();
+class Flag
+{
+ protected:
+ const char *_name;
+ const char *_desc;
+
+ public:
+ Flag(const char *name, const char *desc);
+ virtual ~Flag();
+
+ std::string name() const { return _name; }
+ std::string desc() const { return _desc; }
+
+ virtual void enable() = 0;
+ virtual void disable() = 0;
+};
+
+class SimpleFlag : public Flag
+{
+ protected:
+ bool _status;
+
+ public:
+ SimpleFlag(const char *name, const char *desc)
+ : Flag(name, desc)
+ { }
+
+ bool status() const { return _status; }
+ operator bool() const { return _status; }
+ bool operator!() const { return !_status; }
+
+ void enable() { _status = true; }
+ void disable() { _status = false; }
+};
+
+class CompoundFlag : public SimpleFlag
+{
+ protected:
+ std::vector<Flag *> flags;
+
+ public:
+ CompoundFlag(const char *name, const char *desc,
+ Flag &f00 = *(Flag *)0, Flag &f01 = *(Flag *)0,
+ Flag &f02 = *(Flag *)0, Flag &f03 = *(Flag *)0,
+ Flag &f04 = *(Flag *)0, Flag &f05 = *(Flag *)0,
+ Flag &f06 = *(Flag *)0, Flag &f07 = *(Flag *)0,
+ Flag &f08 = *(Flag *)0, Flag &f09 = *(Flag *)0,
+ Flag &f10 = *(Flag *)0, Flag &f11 = *(Flag *)0,
+ Flag &f12 = *(Flag *)0, Flag &f13 = *(Flag *)0,
+ Flag &f14 = *(Flag *)0, Flag &f15 = *(Flag *)0,
+ Flag &f16 = *(Flag *)0, Flag &f17 = *(Flag *)0,
+ Flag &f18 = *(Flag *)0, Flag &f19 = *(Flag *)0)
+ : SimpleFlag(name, desc)
+ {
+ addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03); addFlag(f04);
+ addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08); addFlag(f09);
+ addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13); addFlag(f14);
+ addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18); addFlag(f19);
+ }
+
+ void
+ addFlag(Flag &f)
+ {
+ if (&f != NULL)
+ flags.push_back(&f);
+ }
+
+ void enable();
+ void disable();
+};
+
} // namespace Debug
#endif // __BASE_DEBUG_HH__
#include "base/loader/exec_aout.h"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
+#include "debug/Loader.hh"
using namespace std;
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "debug/Loader.hh"
// Only alpha will be able to load ecoff files for now.
// base/types.hh and ecoff_machdep.h must be before the other .h files
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/Loader.hh"
#include "sim/byteswap.hh"
#include "gelf.h"
#include "base/loader/raw_object.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
+#include "debug/Loader.hh"
ObjectFile *
RawObject::tryFile(const std::string &fname, int fd, size_t len, uint8_t *data)
#include "base/mysql.hh"
#include "base/trace.hh"
+#include "debug/SQL.hh"
using namespace std;
#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/GDBAll.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "sim/system.hh"
using namespace std;
+using namespace Debug;
using namespace TheISA;
#ifndef NDEBUG
#include <cctype>
#include <fstream>
#include <iostream>
-#include <list>
#include <string>
-#include <vector>
#include "base/misc.hh"
#include "base/output.hh"
using namespace std;
namespace Trace {
+
const string DefaultName("global");
-FlagVec flags(NumFlags, false);
bool enabled = false;
//
}
}
-bool
-changeFlag(const char *s, bool value)
-{
- using namespace Trace;
- std::string str(s);
-
- for (int i = 0; i < numFlagStrings; ++i) {
- if (str != flagStrings[i])
- continue;
-
- if (i < NumFlags) {
- flags[i] = value;
- } else {
- i -= NumFlags;
-
- const Flags *flagVec = compoundFlags[i];
- for (int j = 0; flagVec[j] != -1; ++j) {
- if (flagVec[j] < NumFlags)
- flags[flagVec[j]] = value;
- }
- }
-
- return true;
- }
-
- // the flag was not found.
- return false;
-}
-
-void
-dumpStatus()
-{
- using namespace Trace;
- for (int i = 0; i < numFlagStrings; ++i) {
- if (flags[i])
- cprintf("%s\n", flagStrings[i]);
- }
-}
-
} // namespace Trace
-
-
-// add a set of functions that can easily be invoked from gdb
-void
-setTraceFlag(const char *string)
-{
- Trace::changeFlag(string, true);
-}
-
-void
-clearTraceFlag(const char *string)
-{
- Trace::changeFlag(string, false);
-}
-
-void
-dumpTraceStatus()
-{
- Trace::dumpStatus();
-}
#define __BASE_TRACE_HH__
#include <string>
-#include <vector>
#include "base/cprintf.hh"
+#include "base/debug.hh"
#include "base/match.hh"
-#include "base/traceflags.hh"
#include "base/types.hh"
#include "sim/core.hh"
namespace Trace {
+using Debug::SimpleFlag;
+using Debug::CompoundFlag;
+
std::ostream &output();
void setOutput(const std::string &filename);
extern bool enabled;
-typedef std::vector<bool> FlagVec;
-extern FlagVec flags;
-inline bool IsOn(int t) { return flags[t]; }
bool changeFlag(const char *str, bool value);
void dumpStatus();
#if TRACING_ON
-#define DTRACE(x) (Trace::IsOn(Trace::x) && Trace::enabled)
+#define DTRACE(x) ((Debug::x) && Trace::enabled)
#define DDUMP(x, data, count) do { \
+ using namespace Debug; \
if (DTRACE(x)) \
Trace::dump(curTick(), name(), data, count); \
} while (0)
#define DPRINTF(x, ...) do { \
+ using namespace Debug; \
if (DTRACE(x)) \
Trace::dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
-#define DPRINTFS(x,s, ...) do { \
+#define DPRINTFS(x, s, ...) do { \
+ using namespace Debug; \
if (DTRACE(x)) \
- Trace::dprintf(curTick(), s->name(), __VA_ARGS__); \
+ Trace::dprintf(curTick(), s->name(), __VA_ARGS__); \
} while (0)
-
#define DPRINTFR(x, ...) do { \
+ using namespace Debug; \
if (DTRACE(x)) \
Trace::dprintf((Tick)-1, std::string(), __VA_ARGS__); \
} while (0)
#include "base/misc.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "debug/VNC.hh"
#include "sim/byteswap.hh"
using namespace std;
TraceFlag('PCEvent')
TraceFlag('Quiesce')
+CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
+ 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
+ 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
+ 'ExecTicks', 'ExecMicro', 'ExecMacro' ])
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
#include "cpu/activity.hh"
#include "cpu/timebuf.hh"
+#include "debug/Activity.hh"
using namespace std;
#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "params/BaseCPU.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
+#include "debug/DynInst.hh"
+#include "debug/IQ.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecAll.hh"
#include "enums/OpClass.hh"
using namespace std;
{
ostream &outs = Trace::output();
- if (IsOn(ExecTicks))
+ if (Debug::ExecTicks)
dumpTicks(outs);
outs << thread->getCpuPtr()->name() << " ";
- if (IsOn(ExecSpeculative))
+ if (Debug::ExecSpeculative)
outs << (misspeculating ? "-" : "+") << " ";
- if (IsOn(ExecThread))
+ if (Debug::ExecThread)
outs << "T" << thread->threadId() << " : ";
std::string sym_str;
Addr sym_addr;
Addr cur_pc = pc.instAddr();
- if (debugSymbolTable
- && IsOn(ExecSymbol)
+ if (debugSymbolTable && Debug::ExecSymbol
#if FULL_SYSTEM
&& !inUserMode(thread)
#endif
if (ran) {
outs << " : ";
- if (IsOn(ExecOpClass)) {
+ if (Debug::ExecOpClass) {
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
- if (IsOn(ExecResult) && predicate == false) {
+ if (Debug::ExecResult && predicate == false) {
outs << "Predicated False";
}
- if (IsOn(ExecResult) && data_status != DataInvalid) {
+ if (Debug::ExecResult && data_status != DataInvalid) {
ccprintf(outs, " D=%#018x", data.as_int);
}
- if (IsOn(ExecEffAddr) && addr_valid)
+ if (Debug::ExecEffAddr && addr_valid)
outs << " A=0x" << hex << addr;
- if (IsOn(ExecFetchSeq) && fetch_seq_valid)
+ if (Debug::ExecFetchSeq && fetch_seq_valid)
outs << " FetchSeq=" << dec << fetch_seq;
- if (IsOn(ExecCPSeq) && cp_seq_valid)
+ if (Debug::ExecCPSeq && cp_seq_valid)
outs << " CPSeq=" << dec << cp_seq;
}
* finishes. Macroops then behave like regular instructions and don't
* complete/print when they fault.
*/
- if (IsOn(ExecMacro) && staticInst->isMicroop() &&
- ((IsOn(ExecMicro) &&
- macroStaticInst && staticInst->isFirstMicroop()) ||
- (!IsOn(ExecMicro) &&
+ if (Debug::ExecMacro && staticInst->isMicroop() &&
+ ((Debug::ExecMicro &&
+ macroStaticInst && staticInst->isFirstMicroop()) ||
+ (!Debug::ExecMicro &&
macroStaticInst && staticInst->isLastMicroop()))) {
traceInst(macroStaticInst, false);
}
- if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
+ if (Debug::ExecMicro || !staticInst->isMicroop()) {
traceInst(staticInst, true);
}
}
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecEnable.hh"
+#include "debug/ExecSpeculative.hh"
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
- if (!IsOn(ExecEnable))
+ if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
return NULL;
- if (!IsOn(ExecSpeculative) && tc->misspeculating())
+ if (!Debug::ExecSpeculative && tc->misspeculating())
return NULL;
return new ExeTracerRecord(when, tc,
#include "cpu/exetrace.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderCPU.hh"
+#include "debug/RefCount.hh"
+#include "debug/SkedCache.hh"
#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
#include "sim/process.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/first_stage.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderStage.hh"
#include "params/InOrderTrace.hh"
using namespace std;
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/exetrace.hh"
+#include "debug/InOrderDynInst.hh"
#include "mem/request.hh"
using namespace std;
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/InOrderDynInst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecEnable.hh"
#include "params/InOrderTrace.hh"
using namespace std;
InOrderTrace::getInstRecord(unsigned num_stages, bool stage_tracing,
ThreadContext *tc)
{
- if (!IsOn(ExecEnable))
+ if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_stage.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderStage.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/Resource.hh"
+#include "debug/ThreadModel.hh"
using namespace std;
using namespace ThePipeline;
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/reg_dep_map.hh"
+#include "debug/RegDepMap.hh"
using namespace std;
using namespace TheISA;
#include "base/str.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource.hh"
+#include "debug/RefCount.hh"
+#include "debug/ResReqCount.hh"
+#include "debug/Resource.hh"
+
using namespace std;
Resource::Resource(string res_name, int res_id, int res_width,
#include "cpu/inorder/resources/resource_list.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_sked.hh"
+#include "debug/SkedCache.hh"
using namespace std;
using namespace ThePipeline;
*/
#include "cpu/inorder/resources/agen_unit.hh"
+#include "debug/InOrderAGEN.hh"
AGENUnit::AGENUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu,
#include "arch/utility.hh"
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/bpred_unit.hh"
+#include "debug/InOrderBPred.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;
#include "config/the_isa.hh"
#include "cpu/inorder/resources/branch_predictor.hh"
+#include "debug/InOrderBPred.hh"
+#include "debug/InOrderStage.hh"
using namespace std;
using namespace TheISA;
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/AddrDep.hh"
+#include "debug/InOrderCachePort.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/InOrderTLB.hh"
+#include "debug/LLSC.hh"
+#include "debug/RefCount.hh"
+#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;
#include "config/the_isa.hh"
#include "cpu/inorder/resources/decode_unit.hh"
+#include "debug/InOrderDecode.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/Resource.hh"
using namespace TheISA;
using namespace ThePipeline;
#include "cpu/inorder/resources/execution_unit.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderExecute.hh"
+#include "debug/InOrderStall.hh"
using namespace std;
using namespace ThePipeline;
#include "config/the_isa.hh"
#include "cpu/inorder/resources/fetch_seq_unit.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderFetchSeq.hh"
+#include "debug/InOrderStall.hh"
using namespace std;
using namespace TheISA;
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderCachePort.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/RefCount.hh"
+#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;
*/
#include "cpu/inorder/resources/graduation_unit.hh"
+#include "debug/InOrderGraduation.hh"
using namespace ThePipeline;
#include "cpu/inorder/resources/inst_buffer.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
+#include "debug/InOrderInstBuffer.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace TheISA;
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
#include "cpu/op_class.hh"
+#include "debug/InOrderMDU.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;
#include "cpu/inorder/resources/use_def.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/InOrderUseDef.hh"
using namespace std;
using namespace TheISA;
#include "config/the_isa.hh"
#include "cpu/inorder/thread_context.hh"
#include "cpu/exetrace.hh"
+#include "debug/InOrderCPU.hh"
using namespace TheISA;
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "debug/ExecEnable.hh"
+#include "debug/ExecSpeculative.hh"
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
- if (!IsOn(ExecEnable))
+ if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
return NULL;
- if (!IsOn(ExecSpeculative) && tc->misspeculating())
+ if (!Debug::ExecSpeculative && tc->misspeculating())
return NULL;
return new IntelTraceRecord(when, tc,
#include "cpu/base.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
+#include "debug/IntrControl.hh"
#include "sim/sim_object.hh"
using namespace std;
#include "base/socket.hh"
#include "cpu/nativetrace.hh"
#include "cpu/static_inst.hh"
+#include "debug/GDBMisc.hh"
#include "params/NativeTrace.hh"
using namespace std;
#include "arch/types.hh"
#include "arch/utility.hh"
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/o3/bpred_unit.hh"
+#include "debug/Fetch.hh"
#include "params/DerivO3CPU.hh"
template<class Impl>
#include "cpu/o3/thread_state.hh"
#include "cpu/exetrace.hh"
#include "cpu/timebuf.hh"
+#include "debug/Activity.hh"
+#include "debug/Commit.hh"
+#include "debug/CommitRate.hh"
+#include "debug/ExecFaulting.hh"
#include "params/DerivO3CPU.hh"
#include "sim/faults.hh"
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
+#include "debug/Activity.hh"
+#include "debug/O3CPU.hh"
+#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
#include "sim/core.hh"
#include "sim/stat_control.hh"
#if THE_ISA == ALPHA_ISA
#include "arch/alpha/osfpal.hh"
+#include "debug/Activity.hh"
#endif
class BaseCPUParams;
#include "config/the_isa.hh"
#include "cpu/o3/decode.hh"
#include "cpu/inst_seq.hh"
+#include "debug/Activity.hh"
+#include "debug/Decode.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
#include "cpu/checker/cpu.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/exetrace.hh"
+#include "debug/Activity.hh"
+#include "debug/Fetch.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/DerivO3CPU.hh"
#include "base/trace.hh"
#include "cpu/o3/free_list.hh"
+#include "debug/FreeList.hh"
SimpleFreeList::SimpleFreeList(ThreadID activeThreads,
unsigned _numLogicalIntRegs,
#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
+#include "debug/FreeList.hh"
/**
* FreeList class that simply holds the list of free integer and floating
#include "cpu/o3/lsq.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/timebuf.hh"
+#include "debug/IEW.hh"
class DerivO3CPUParams;
class FUPool;
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
#include "cpu/timebuf.hh"
+#include "debug/Activity.hh"
+#include "debug/Decode.hh"
+#include "debug/IEW.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
+#include "debug/IQ.hh"
#include "enums/OpClass.hh"
#include "params/DerivO3CPU.hh"
#include "sim/core.hh"
#include <string>
#include "cpu/o3/lsq.hh"
+#include "debug/Fetch.hh"
+#include "debug/LSQ.hh"
+#include "debug/Writeback.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
+#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "config/use_checker.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/o3/lsq_unit.hh"
+#include "debug/Activity.hh"
+#include "debug/IEW.hh"
+#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "base/refcnt.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
+#include "debug/MemDepUnit.hh"
struct SNHash {
size_t operator() (const InstSeqNum &seq_num) const {
#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/mem_dep_unit.hh"
+#include "debug/MemDepUnit.hh"
#include "params/DerivO3CPU.hh"
template <class MemDepPred, class Impl>
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
+#include "debug/IEW.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/o3/rename.hh"
+#include "debug/Activity.hh"
+#include "debug/Rename.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
#include <vector>
#include "cpu/o3/rename_map.hh"
+#include "debug/Rename.hh"
using namespace std;
#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
+#include "debug/Fetch.hh"
+#include "debug/ROB.hh"
using namespace std;
#include "config/the_isa.hh"
#include "cpu/o3/scoreboard.hh"
+#include "debug/Scoreboard.hh"
Scoreboard::Scoreboard(unsigned activeThreads,
unsigned _numLogicalIntRegs,
#include <vector>
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "cpu/o3/comm.hh"
/**
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/o3/store_set.hh"
+#include "debug/StoreSet.hh"
StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
: SSITSize(_SSIT_size), LFSTSize(_LFST_size)
#include "config/the_isa.hh"
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
+#include "debug/O3CPU.hh"
#if FULL_SYSTEM
template <class Impl>
#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "cpu/thread_context.hh"
+#include "debug/PCEvent.hh"
#include "sim/core.hh"
#include "sim/system.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/pred/2bit_local.hh"
+#include "debug/Fetch.hh"
LocalBP::LocalBP(unsigned _localPredictorSize,
unsigned _localCtrBits,
#include "base/intmath.hh"
#include "base/trace.hh"
#include "cpu/pred/btb.hh"
+#include "debug/Fetch.hh"
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
#include "cpu/base.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/thread_context.hh"
+#include "debug/Quiesce.hh"
EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc)
: tc(_tc)
#include "config/the_isa.hh"
#include "cpu/simple/atomic.hh"
#include "cpu/exetrace.hh"
+#include "debug/ExecFaulting.hh"
+#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/AtomicSimpleCPU.hh"
#include "cpu/smt.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/Decode.hh"
+#include "debug/Fetch.hh"
+#include "debug/Quiesce.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
#include "config/the_isa.hh"
#include "cpu/simple/timing.hh"
#include "cpu/exetrace.hh"
+#include "debug/Config.hh"
+#include "debug/ExecFaulting.hh"
+#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "debug/FloatRegs.hh"
+#include "debug/IntRegs.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/InvalidateGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
+#include "debug/DirectedTest.hh"
InvalidateGenerator::InvalidateGenerator(const Params *p)
: DirectedGenerator(p)
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
+#include "debug/DirectedTest.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "sim/sim_exit.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
+#include "debug/DirectedTest.hh"
SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
: DirectedGenerator(p)
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/testers/memtest/memtest.hh"
+#include "debug/MemTest.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/testers/networktest/networktest.hh"
+#include "debug/NetworkTest.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
*/
#include "cpu/testers/rubytest/Check.hh"
+#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"
#include "base/intmath.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "cpu/testers/rubytest/CheckTable.hh"
+#include "debug/RubyTest.hh"
CheckTable::CheckTable(int _num_cpu_sequencers, RubyTester* _tester)
: m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester)
#include "base/misc.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
+#include "debug/RubyTest.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "debug/Context.hh"
void
ThreadContext::compare(ThreadContext *one, ThreadContext *two)
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/AlphaBackdoor.hh"
#include "dev/alpha/backdoor.hh"
#include "dev/platform.hh"
#include "dev/simple_disk.hh"
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
+#include "debug/IPI.hh"
+#include "debug/Tsunami.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/alpha/tsunami_cchip.hh"
#include "dev/alpha/tsunamireg.h"
#include "base/time.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/Tsunami.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/alpha/tsunami_cchip.hh"
#include "dev/alpha/tsunami_io.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/Tsunami.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/alpha/tsunami_pchip.hh"
#include "dev/alpha/tsunamireg.h"
#include "base/cp_annotate.hh"
#include "base/trace.hh"
+#include "debug/DMACopyEngine.hh"
#include "dev/copy_engine.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "base/callback.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/DiskImageRead.hh"
+#include "debug/DiskImageWrite.hh"
#include "dev/disk_image.hh"
#include "sim/byteswap.hh"
#include "sim/sim_exit.hh"
#include <vector>
#include "base/trace.hh"
+#include "debug/Ethernet.hh"
+#include "debug/EthernetData.hh"
#include "dev/etherbus.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "base/random.hh"
#include "base/trace.hh"
+#include "debug/Ethernet.hh"
+#include "debug/EthernetData.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherlink.hh"
#include "base/pollevent.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "debug/Ethernet.hh"
+#include "debug/EthernetData.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "base/inet.hh"
#include "base/trace.hh"
+#include "debug/EthernetAll.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "base/cp_annotate.hh"
#include "base/inet.hh"
+#include "debug/EthernetDesc.hh"
+#include "debug/EthernetIntr.hh"
#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "base/trace.hh"
#include "cpu/intr_control.hh"
+#include "debug/IdeCtrl.hh"
#include "dev/ide_ctrl.hh"
#include "dev/ide_disk.hh"
#include "mem/packet.hh"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/IdeDisk.hh"
#include "dev/disk_image.hh"
#include "dev/ide_ctrl.hh"
#include "dev/ide_disk.hh"
*/
#include "base/misc.hh"
+#include "debug/Intel8254Timer.hh"
#include "dev/intel_8254_timer.hh"
using namespace std;
#include "base/bitunion.hh"
#include "base/types.hh"
+#include "debug/Intel8254Timer.hh"
#include "sim/eventq.hh"
#include "sim/serialize.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
+#include "debug/BusAddrRanges.hh"
+#include "debug/DMA.hh"
#include "dev/io_device.hh"
#include "sim/system.hh"
*/
#include "base/trace.hh"
+#include "debug/IsaFake.hh"
#include "dev/isa_fake.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "base/bitfield.hh"
#include "base/time.hh"
#include "base/trace.hh"
+#include "debug/MC146818.hh"
#include "dev/mc146818.hh"
#include "dev/rtcreg.h"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "debug/EthernetAll.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
#include "dev/pciconfigall.hh"
*/
#include "base/trace.hh"
+#include "debug/PciConfigAll.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcireg.h"
#include "dev/platform.hh"
#include "base/misc.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "debug/PCIDEV.hh"
#include "dev/alpha/tsunamireg.h"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/SimpleDisk.hh"
+#include "debug/SimpleDiskData.hh"
#include "dev/disk_image.hh"
#include "dev/simple_disk.hh"
#include "mem/port.hh"
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
+#include "debug/EthernetAll.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
#include "mem/packet.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/intr_control.hh"
+#include "debug/Iob.hh"
#include "dev/sparc/iob.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include <cstring>
#include "base/trace.hh"
+#include "debug/IdeDisk.hh"
#include "dev/sparc/mm_disk.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include "base/output.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "debug/Terminal.hh"
+#include "debug/TerminalVerbose.hh"
#include "dev/platform.hh"
#include "dev/terminal.hh"
#include "dev/uart.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/Uart.hh"
#include "dev/platform.hh"
#include "dev/terminal.hh"
#include "dev/uart8250.hh"
* Authors: Gabe Black
*/
+#include "debug/CMOS.hh"
#include "dev/x86/cmos.hh"
#include "dev/x86/intdev.hh"
#include "mem/packet_access.hh"
*/
#include "base/bitunion.hh"
+#include "debug/I8042.hh"
#include "dev/x86/i8042.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "arch/x86/interrupts.hh"
#include "arch/x86/intmessage.hh"
+#include "debug/I82094AA.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/i8259.hh"
#include "mem/packet.hh"
* Authors: Gabe Black
*/
+#include "debug/I8254.hh"
#include "dev/x86/i8254.hh"
#include "dev/x86/intdev.hh"
#include "mem/packet.hh"
*/
#include "base/bitfield.hh"
+#include "debug/I8259.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/i8259.hh"
#include "mem/packet.hh"
#include "base/bitunion.hh"
#include "base/trace.hh"
+#include "debug/PcSpeaker.hh"
#include "dev/x86/i8254.hh"
#include "dev/x86/speaker.hh"
#include "mem/packet.hh"
#include "arch/utility.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/DebugPrintf.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "kern/system_events.hh"
#include <string>
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
#include "sim/system.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "debug/PCEvent.hh"
#include "kern/system_events.hh"
using namespace TheISA;
#include "arch/alpha/registers.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
+#include "debug/SyscallVerbose.hh"
#include "sim/core.hh"
#include "sim/syscall_emul.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/BADADDR.hh"
+#include "debug/DebugPrintf.hh"
+#include "debug/Printf.hh"
#include "kern/tru64/dump_mbuf.hh"
#include "kern/tru64/printf.hh"
#include "kern/tru64/tru64_events.hh"
#include "base/range_ops.hh"
#include "base/trace.hh"
+#include "debug/BusBridge.hh"
#include "mem/bridge.hh"
#include "params/Bridge.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/Bus.hh"
+#include "debug/BusAddrRanges.hh"
+#include "debug/MMU.hh"
#include "mem/bus.hh"
Bus::Bus(const BusParams *p)
#include "cpu/base.hh"
#include "cpu/smt.hh"
+#include "debug/Cache.hh"
#include "mem/cache/base.hh"
#include "mem/cache/mshr.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/full_system.hh"
+#include "debug/Cache.hh"
+#include "debug/CachePort.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "base/misc.hh"
#include "base/range.hh"
#include "base/types.hh"
+#include "debug/Cache.hh"
+#include "debug/CachePort.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/cache.hh"
#include "base/misc.hh"
#include "base/types.hh"
+#include "debug/Cache.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/mshr.hh"
#include "sim/core.hh"
#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/base.hh"
#include "mem/request.hh"
*/
#include "base/trace.hh"
+#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/ghb.hh"
void
*/
#include "base/trace.hh"
+#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/stride.hh"
void
#include "base/intmath.hh"
#include "base/trace.hh"
+#include "debug/Cache.hh"
+#include "debug/IIC.hh"
+#include "debug/IICMore.hh"
#include "mem/cache/tags/iic.hh"
#include "mem/cache/base.hh"
#include "sim/core.hh"
#include <string>
#include "base/intmath.hh"
+#include "debug/CacheRepl.hh"
#include "mem/cache/tags/cacheset.hh"
#include "mem/cache/tags/lru.hh"
#include "mem/cache/base.hh"
#include "base/intmath.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/MMU.hh"
#include "mem/page_table.hh"
#include "sim/faults.hh"
#include "sim/process.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
+#include "debug/LLSC.hh"
+#include "debug/MemoryAccess.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
#include "sim/eventq.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
+#include "debug/Config.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "base/stl_helpers.hh"
+#include "debug/RubyQueue.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/system/System.hh"
#include <iostream>
#include <vector>
+#include "debug/RubyMemory.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/Set.hh"
#include <cmath>
#include "base/stl_helpers.hh"
+#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh"
*/
#include "base/stl_helpers.hh"
+#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh"
#include <cmath>
#include "base/stl_helpers.hh"
+#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh"
*/
#include "base/stl_helpers.hh"
+#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/InVcState.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/Router.hh"
#include <algorithm>
+#include "debug/RubyNetwork.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include <cassert>
#include "base/cprintf.hh"
+#include "debug/RubyNetwork.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/Throttle.hh"
#include <cassert>
+#include "debug/RubyNetwork.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/protocol/TopologyType.hh"
*/
#include "base/intmath.hh"
+#include "debug/RubyCache.hh"
#include "mem/ruby/system/CacheMemory.hh"
using namespace std;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "debug/RubyDma.hh"
#include "mem/protocol/SequencerMsg.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
*/
#include "base/intmath.hh"
+#include "debug/RubyCache.hh"
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#include "mem/ruby/system/DirectoryMemory.hh"
#include "mem/ruby/system/System.hh"
#include "arch/x86/insts/microldstop.hh"
#endif // X86_ISA
#include "cpu/testers/rubytest/RubyTester.hh"
+#include "debug/MemoryAccess.hh"
+#include "debug/Ruby.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "mem/physical.hh"
#include "base/misc.hh"
#include "base/str.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
+#include "debug/MemoryAccess.hh"
+#include "debug/ProtocolTrace.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/Global.hh"
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "debug/RubyCache.hh"
#include "mem/ruby/system/SparseMemory.hh"
#include "mem/ruby/system/System.hh"
#include <string>
#include "base/cprintf.hh"
+#include "debug/RubyGenerated.hh"
+#include "debug/RubySlicc.hh"
#include "mem/protocol/${ident}_Controller.hh"
#include "mem/protocol/${ident}_Event.hh"
#include "mem/protocol/${ident}_State.hh"
#include <cassert>
#include "base/misc.hh"
+#include "debug/RubySlicc.hh"
#include "mem/protocol/${ident}_Controller.hh"
#include "mem/protocol/${ident}_Event.hh"
#include "mem/protocol/${ident}_State.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/ProtocolTrace.hh"
+#include "debug/RubyGenerated.hh"
#include "mem/protocol/${ident}_Controller.hh"
#include "mem/protocol/${ident}_Event.hh"
#include "mem/protocol/${ident}_State.hh"
* Authors: Ali Saidi
*/
+#include "debug/Bus.hh"
#include "mem/tport.hh"
using namespace std;
import internal
from internal.debug import schedBreakCycle, setRemoteGDBPort
+
+def help():
+ print "Base Flags:"
+ for flag in flags.basic:
+ print " %s: %s" % (flag, flags.descriptions[flag])
+ print
+ print "Compound Flags:"
+ for flag in flags.compound:
+ if flag == 'All':
+ continue
+ print " %s: %s" % (flag, flags.descriptions[flag])
+ util.printList(flags.compoundMap[flag], indent=8)
+ print
+
+class AllFlags(object):
+ def __init__(self):
+ self._version = -1
+ self._dict = {}
+
+ def _update(self):
+ current_version = internal.debug.getAllFlagsVersion()
+ if self._version == current_version:
+ return
+
+ self._dict.clear()
+ for flag in internal.debug.getAllFlags():
+ self._dict[flag.name()] = flag
+ self._version = current_version
+
+ def __contains__(self, item):
+ self._update()
+ return item in self._dict
+
+ def __getitem__(self, item):
+ self._update()
+ return self._dict[item]
+
+ def keys(self):
+ self._update()
+ return self._dict.keys()
+
+ def values(self):
+ self._update()
+ return self._dict.values()
+
+ def items(self):
+ self._update()
+ return self._dict.items()
+
+ def iterkeys(self):
+ self._update()
+ return self._dict.iterkeys()
+
+ def itervalues(self):
+ self._update()
+ return self._dict.itervalues()
+
+ def iteritems(self):
+ self._update()
+ return self._dict.iteritems()
+
+flags = AllFlags()
set_group("Debugging Options")
add_option("--debug-break", metavar="TIME[,TIME]", action='append', split=',',
help="Cycle to create a breakpoint")
+add_option("--debug-help", action='store_true',
+ help="Print help on debug flags")
+add_option("--debug-flags", metavar="FLAG[,FLAG]", action='append', split=',',
+ help="Sets the flags for debugging (-FLAG disables a flag)")
add_option("--remote-gdb-port", type='int', default=7000,
help="Remote gdb base port (set to 0 to disable listening)")
# Tracing options
set_group("Trace Options")
-add_option("--trace-help", action='store_true',
- help="Print help on trace flags")
-add_option("--trace-flags", metavar="FLAG[,FLAG]", action='append', split=',',
- help="Sets the flags for tracing (-FLAG disables a flag)")
add_option("--trace-start", metavar="TIME", type='int',
help="Start tracing at TIME (must be in ticks)")
add_option("--trace-file", metavar="FILE", default="cout",
print info.README
print
- if options.trace_help:
+ if options.debug_help:
done = True
check_tracing()
- trace.help()
+ debug.help()
if options.list_sim_objects:
import SimObject
for when in options.debug_break:
debug.schedBreakCycle(int(when))
- if options.trace_flags:
+ if options.debug_flags:
check_tracing()
on_flags = []
off_flags = []
- for flag in options.trace_flags:
+ for flag in options.debug_flags:
off = False
if flag.startswith('-'):
flag = flag[1:]
off = True
- if flag not in trace.flags.all and flag != "All":
- print >>sys.stderr, "invalid trace flag '%s'" % flag
+
+ if flag not in debug.flags:
+ print >>sys.stderr, "invalid debug flag '%s'" % flag
sys.exit(1)
if off:
- off_flags.append(flag)
+ debug.flags[flag].disable()
else:
- on_flags.append(flag)
-
- for flag in on_flags:
- trace.set(flag)
-
- for flag in off_flags:
- trace.clear(flag)
+ debug.flags[flag].enable()
if options.trace_start:
check_tracing()
# Authors: Nathan Binkert
import internal
-import traceflags as flags
import util
-from internal.trace import clear, output, set, ignore
+from internal.trace import output, ignore
def disable():
internal.trace.cvar.enabled = False
def enable():
internal.trace.cvar.enabled = True
-
-def help():
- print "Base Flags:"
- for flag in flags.basic:
- print " %s: %s" % (flag, flags.descriptions[flag])
- print
- print "Compound Flags:"
- for flag in flags.compound:
- if flag == 'All':
- continue
- print " %s: %s" % (flag, flags.descriptions[flag])
- util.printList(flags.compoundMap[flag], indent=8)
- print
/*
* Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2010 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
%module(package="m5.internal") debug
%{
+#include <cassert>
+#include <map>
+#include <string>
+#include <vector>
+
+#include "base/debug.hh"
#include "base/types.hh"
#include "sim/debug.hh"
+
+using namespace std;
+
+typedef map<string, Debug::Flag *> FlagsMap;
+typedef vector<Debug::Flag *> FlagsVec;
+
+namespace Debug {
+extern int allFlagsVersion;
+FlagsMap &allFlags();
+}
+
+inline int
+getAllFlagsVersion()
+{
+ return Debug::allFlagsVersion;
+}
+
+inline FlagsVec
+getAllFlags()
+{
+ FlagsMap &flagsMap = Debug::allFlags();
+
+ FlagsVec flags(flagsMap.size());
+
+ int index = 0;
+ FlagsMap::iterator i = flagsMap.begin();
+ FlagsMap::iterator end = flagsMap.end();
+ for (; i != end; ++i) {
+ assert(index < flags.size());
+ flags[index++] = i->second;
+ }
+
+ return flags;
+}
+
%}
+%ignore Debug::SimpleFlag::operator!;
+
+%include <std_string.i>
+%include <std_vector.i>
%include <stdint.i>
+%include "base/debug.hh"
%include "base/types.hh"
%include "sim/debug.hh"
+
+%template(AllFlags) std::vector<Debug::Flag *>;
+
+int getAllFlagsVersion();
+std::vector<Debug::Flag *> getAllFlags();
Trace::setOutput(filename);
}
-inline void
-set(const char *flag)
-{
- Trace::changeFlag(flag, true);
-}
-
-inline void
-clear(const char *flag)
-{
- Trace::changeFlag(flag, false);
-}
-
inline void
ignore(const char *expr)
{
using Trace::enabled;
%}
-%inline %{
extern void output(const char *string);
-extern void set(const char *string);
-extern void clear(const char *string);
extern void ignore(const char *expr);
extern bool enabled;
-%}
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/smt.hh"
+#include "debug/Config.hh"
#include "sim/core.hh"
#include "sim/eventq.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "debug/Event.hh"
#include "sim/serialize.hh"
class EventQueue; // forward declaration
#include "base/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Fault.hh"
#include "mem/page_table.hh"
#include "sim/faults.hh"
#include "sim/process.hh"
#include "cpu/base.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
+#include "debug/Quiesce.hh"
+#include "debug/WorkItems.hh"
#include "params/BaseCPU.hh"
#include "sim/pseudo_inst.hh"
#include "sim/serialize.hh"
*/
#include "base/misc.hh"
+#include "debug/TimeSync.hh"
#include "sim/root.hh"
Root *Root::_root = NULL;
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "debug/Config.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/sim_exit.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/byteswap.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
#include "mem/mem_object.hh"
#include "mem/physical.hh"
#include "sim/byteswap.hh"
projects / gem5.git / commitdiff