Add powerpc cell support.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0346ef50906b46c230726de447aa48712b10ebc3..986188809a234f6ae8c08010cb7eb71ad68e8ed7 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+       * doc/c-ppc.texi (-mcell): Document.
+       * config/tc-ppc.c (parse_cpu): Parse -mcell.
+       (md_show_usage): Document -mcell.
+
 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 
        * doc/c-i386.texi : Document amdfam10,.sse4a and .abm in cpu_type.

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 1d655ca123c1ab555b43adefadd52f8e61414b68..bcd32e094125e7a6c464637896550df81d556f59 100644 (file)
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -920,6 +920,12 @@ parse_cpu (const char *arg)
                 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6);
     }
+  else if (strcmp (arg, "cell") == 0)
+    {
+      ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+                | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+                | PPC_OPCODE_CELL);
+    }
   /* -mcom means assemble for the common intersection between Power
      and PowerPC.  At present, we just allow the union, rather
      than the intersection.  */
@@ -1116,6 +1122,7 @@ PowerPC options:\n\
 -mpower4               generate code for Power4 architecture\n\
 -mpower5               generate code for Power5 architecture\n\
 -mpower6               generate code for Power6 architecture\n\
+-mcell                 generate code for Cell Broadband Engine architecture\n\
 -mcom                  generate code Power/PowerPC common instructions\n\
 -many                  generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\

diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index b5e26fd0a8d884d85152344779c0136f554c32f7..ad6bd1a689344e4d2f94f1abe0d95aa34337ba9b 100644 (file)
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -82,6 +82,9 @@ Generate code for Power5 architecture.
 @item -mpower6
 Generate code for Power6 architecture.
 
+@item -mcell
+Generate code for Cell Broadband Engine architecture.
+
 @item -mcom
 Generate code Power/PowerPC common instructions.
 

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b6b8003d0177fdf660e75e00ae8b76ce5fa42b82..69c2ea89791ccfb8ac17ae4f30bcfeb35eef005c 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+       * gas/ppc/cell.s: New file.
+       * gas/ppc/cell.d: New file.
+       * gas/ppc/ppc.exp: Test cell.s.
+
 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 
        * gas/i386/amdfam10.d : Modify to support for the change in POPCNT

diff --git a/gas/testsuite/gas/ppc/cell.d b/gas/testsuite/gas/ppc/cell.d
new file mode 100644 (file)
index 0000000..799a8e0
--- /dev/null
+++ b/gas/testsuite/gas/ppc/cell.d
@@ -0,0 +1,31 @@
+#as: -mcell
+#objdump: -dr -Mcell
+#name: Cell tests
+
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.text>:
+   0:  7c 01 14 0e     lvlx    v0,r1,r2
+   4:  7c 00 14 0e     lvlx    v0,0,r2
+   8:  7c 01 16 0e     lvlxl   v0,r1,r2
+   c:  7c 00 16 0e     lvlxl   v0,0,r2
+  10:  7c 01 14 4e     lvrx    v0,r1,r2
+  14:  7c 00 14 4e     lvrx    v0,0,r2
+  18:  7c 01 16 4e     lvrxl   v0,r1,r2
+  1c:  7c 00 16 4e     lvrxl   v0,0,r2
+  20:  7c 01 15 0e     stvlx   v0,r1,r2
+  24:  7c 00 15 0e     stvlx   v0,0,r2
+  28:  7c 01 17 0e     stvlxl  v0,r1,r2
+  2c:  7c 00 17 0e     stvlxl  v0,0,r2
+  30:  7c 01 15 4e     stvrx   v0,r1,r2
+  34:  7c 00 15 4e     stvrx   v0,0,r2
+  38:  7c 01 17 4e     stvrxl  v0,r1,r2
+  3c:  7c 00 17 4e     stvrxl  v0,0,r2
+  40:  7c 00 0c 28     ldbrx   r0,0,r1
+  44:  7c 01 14 28     ldbrx   r0,r1,r2
+  48:  7c 00 0d 28     stdbrx  r0,0,r1
+  4c:  7c 01 15 28     stdbrx  r0,r1,r2

diff --git a/gas/testsuite/gas/ppc/cell.s b/gas/testsuite/gas/ppc/cell.s
new file mode 100644 (file)
index 0000000..2985386
--- /dev/null
+++ b/gas/testsuite/gas/ppc/cell.s
@@ -0,0 +1,24 @@
+       .section        ".text"
+       lvlx %r0, %r1, %r2
+       lvlx %r0, 0, %r2
+       lvlxl %r0, %r1, %r2
+       lvlxl %r0, 0, %r2
+       lvrx %r0, %r1, %r2
+       lvrx %r0, 0, %r2
+       lvrxl %r0, %r1, %r2
+       lvrxl %r0, 0, %r2
+
+       stvlx %r0, %r1, %r2
+       stvlx %r0, 0, %r2
+       stvlxl %r0, %r1, %r2
+       stvlxl %r0, 0, %r2
+       stvrx %r0, %r1, %r2
+       stvrx %r0, 0, %r2
+       stvrxl %r0, %r1, %r2
+       stvrxl %r0, 0, %r2
+
+       ldbrx %r0, 0, %r1
+       ldbrx %r0, %r1, %r2
+
+       stdbrx %r0, 0, %r1
+       stdbrx %r0, %r1, %r2

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 0dd4648f021dcdf7e7fcb6cca799118de528b334..dc5ef2c5b6fa5ae70484ff395234590d38009286 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -11,6 +11,7 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
     run_dump_test "astest2_64"
     run_dump_test "test1elf64"
     run_dump_test "power4"
+    run_dump_test "cell"
 } elseif { [istarget powerpc*-*aix*] } then {
     run_dump_test "test1xcoff32"
 } elseif { [istarget powerpc*-*-*bsd*] \

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 3f70f5db9e28c84283ab7891fee54c41d968cf1c..33a22688ab420cb2e0eb024ed61194f230f6a6bd 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+       * ppc.h (PPC_OPCODE_CELL): Define.
+ 
 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 
        * i386.h :  Modify opcode to support for the change in POPCNT opcode 

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index fc4d41f9f41d839db2c0c74065aa293b28c5a3d1..2205bd6a65c57c4a383344e61b9c749ad7854579 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -143,6 +143,8 @@ extern const int powerpc_num_opcodes;
 /* Opcode is only supported by Power6 architecture.  */
 #define PPC_OPCODE_POWER6       0x4000000
 
+/* Opcode is only supported by PowerPC Cell family.  */
+#define PPC_OPCODE_CELL                 0x8000000
 
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3173ec31180e8dd4f185aae7af5f4dc257b9361d..7f17d757d43e62e77b36902bd9ac14bfd49ddf64 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+       * ppc-opc.c (CELL): New define.
+       (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
+       cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
+       VMX instructions.
+       * ppc-dis.c (powerpc_dialect): Handle cell.
+
 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 
        * i386-dis.c (dis386): Add support for the change in POPCNT opcode in 

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 8b3996a1476ea89a14b9f6d2fb0d88a21378a7b9..d144892fe2dad8bd8889e8121922b2b97cad5d3e 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -73,6 +73,10 @@ powerpc_dialect (struct disassemble_info *info)
       && strstr (info->disassembler_options, "power5") != NULL)
     dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
 
+  if (info->disassembler_options
+      && strstr (info->disassembler_options, "cell") != NULL)
+    dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
+
   if (info->disassembler_options
       && strstr (info->disassembler_options, "power6") != NULL)
     dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 84e6d6a04e9de87322ea5d34f7c72209aa80c472..acfeb8ccfd958cfc4190ee686edc1af542f34f50 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1823,6 +1823,7 @@ extract_tbr (unsigned long insn,
 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
 #define POWER4 PPC_OPCODE_POWER4
 #define POWER5 PPC_OPCODE_POWER5
+#define CELL   PPC_OPCODE_CELL
 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
 #define PPC403 PPC_OPCODE_403
@@ -3014,7 +3015,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "crand",   XL(19,257), XL_MASK,      COM,            { BT, BA, BB } },
 
-{ "hrfid",   XL(19,274), 0xffffffff,   POWER5,         { 0 } },
+{ "hrfid",   XL(19,274), 0xffffffff,   POWER5 | CELL,  { 0 } },
 
 { "crset",   XL(19,289), XL_MASK,      PPCCOM,         { BT, BAT, BBA } },
 { "creqv",   XL(19,289), XL_MASK,      COM,            { BT, BA, BB } },
@@ -3622,7 +3623,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "lscbx",   XRC(31,277,0), X_MASK,    M601,           { RT, RA, RB } },
 { "lscbx.",  XRC(31,277,1), X_MASK,    M601,           { RT, RA, RB } },
 
-{ "dcbt",    X(31,278),        X_MASK, PPC,                    { CT, RA, RB } },
+{ "dcbt",    X(31,278),        X_MASK,         PPC,            { CT, RA, RB } },
 
 { "lhzx",    X(31,279),        X_MASK,         COM,            { RT, RA0, RB } },
 
@@ -4206,6 +4207,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "clcs",    X(31,531), XRB_MASK,      M601,           { RT, RA } },
 
+{ "ldbrx",   X(31,532),        X_MASK,         CELL,           { RT, RA0, RB } },
+
 { "lswx",    X(31,533),        X_MASK,         PPCCOM,         { RT, RA0, RB } },
 { "lsx",     X(31,533),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 
@@ -4265,6 +4268,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsrin",  X(31,659), XRA_MASK,      PPC32,          { RT, RB } },
 
+{ "stdbrx",  X(31,660), X_MASK,                CELL,           { RS, RA0, RB } },
+
 { "stswx",   X(31,661), X_MASK,                PPCCOM,         { RS, RA0, RB } },
 { "stsx",    X(31,661), X_MASK,                PWRCOM,         { RS, RA0, RB } },
 
@@ -4423,6 +4428,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stvx",    X(31, 231), X_MASK,       PPCVEC,         { VS, RA, RB } },
 { "stvxl",   X(31, 487), X_MASK,       PPCVEC,         { VS, RA, RB } },
 
+/* New load/store left/right index vector instructions that are in the Cell only.  */
+{ "lvlx",    X(31, 519), X_MASK,       CELL,           { VD, RA0, RB } },
+{ "lvlxl",   X(31, 775), X_MASK,       CELL,           { VD, RA0, RB } },
+{ "lvrx",    X(31, 551), X_MASK,       CELL,           { VD, RA0, RB } },
+{ "lvrxl",   X(31, 807), X_MASK,       CELL,           { VD, RA0, RB } },
+{ "stvlx",   X(31, 647), X_MASK,       CELL,           { VS, RA0, RB } },
+{ "stvlxl",  X(31, 903), X_MASK,       CELL,           { VS, RA0, RB } },
+{ "stvrx",   X(31, 679), X_MASK,       CELL,           { VS, RA0, RB } },
+{ "stvrxl",  X(31, 935), X_MASK,       CELL,           { VS, RA0, RB } },
+
 { "lwz",     OP(32),   OP_MASK,        PPCCOM,         { RT, D, RA0 } },
 { "l",      OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },