uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
+ uint64_t max_alignment; /* from addrlib */
/* Tile modes. */
uint32_t si_tile_mode_array[32];
uint32_t cik_macrotile_mode_array[16];
}
ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
- const struct amdgpu_gpu_info *amdinfo)
+ const struct amdgpu_gpu_info *amdinfo,
+ uint64_t *max_alignment)
{
ADDR_CREATE_INPUT addrCreateInput = {0};
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
+ ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
if (addrRet != ADDR_OK)
return NULL;
+ if (max_alignment) {
+ addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
+ if (addrRet == ADDR_OK){
+ *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
+ }
+ }
return addrCreateOutput.hLib;
}
};
ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
- const struct amdgpu_gpu_info *amdinfo);
+ const struct amdgpu_gpu_info *amdinfo,
+ uint64_t *max_alignment);
int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config * config,
if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
flags |= RADEON_FLAG_GTT_WC;
- mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
+ mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
domain, flags);
if (!mem->bo) {
return false;
}
- ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo);
+ ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
return false;
goto fail;
}
- ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo);
+ ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, NULL);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
goto fail;