#define V_028A90_FLUSH_HS_OUTPUT 0x11
#define V_028A90_FLUSH_LS_OUTPUT 0x12
#define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
-#define V_028A90_ZPASS_DONE 0x15 /* not on CIK */
+#define V_028A90_ZPASS_DONE 0x15
#define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16
#define V_028A90_PERFCOUNTER_START 0x17
#define V_028A90_PERFCOUNTER_STOP 0x18
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
+ radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, old_value); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
+ radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, new_value); /* immediate data */
radeon_emit(cs, 0); /* unused */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
+ radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
break;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
+ radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);