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Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
author
Claire Wolf
<clifford@clifford.at>
Thu, 14 May 2020 16:06:18 +0000
(18:06 +0200)
committer
GitHub
<noreply@github.com>
Thu, 14 May 2020 16:06:18 +0000
(18:06 +0200)
ast: swap range regardless of range_left >= 0
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frontends/ast/simplify.cc
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diff --cc
frontends/ast/simplify.cc
Simple merge