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mshrs=10
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mshrs=10
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prefetch_degree=1
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latency=1000
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mshrs=10
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prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:50:56
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:02:05
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
env=
errout=cerr
euid=100
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+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:08
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:36:02
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated
latency=1000
max_miss_count=0
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latency=10000
max_miss_count=0
mshrs=10
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:05:42
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:27:06
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
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latency=1000
max_miss_count=0
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prefetch_latency=10000
latency=1000
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mshrs=10
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 12:13:14
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:32
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618365 # Number of instructions simulated
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency
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system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency
env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:04:58
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:19:07
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2585505 # Simulator instruction rate (inst/s)
-host_mem_usage 197792 # Number of bytes of host memory used
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-host_tick_rate 1292756549 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
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mshrs=10
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prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:25:44
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:27:10
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:41:09
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1432576 # Simulator instruction rate (inst/s)
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-host_seconds 1130.39 # Real time elapsed on the host
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sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619366736 # Number of instructions simulated
sim_seconds 0.962929 # Number of seconds simulated
latency=1000
max_miss_count=0
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prefetch_data_accesses_only=false
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latency=1000
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prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
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+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:32:22
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:47:37
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1181561 # Simulator instruction rate (inst/s)
-host_mem_usage 194380 # Number of bytes of host memory used
-host_seconds 1370.53 # Real time elapsed on the host
-host_tick_rate 1324103876 # Simulator tick rate (ticks/s)
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+host_tick_rate 1112100106 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619366736 # Number of instructions simulated
sim_seconds 1.814727 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.901154 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42325.964954 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 660.164909 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.052737 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.452189 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1728.087970 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14817.313734 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 442788 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=2
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:50:49
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1907705384500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 195241 # Simulator instruction rate (inst/s)
-host_mem_usage 278896 # Number of bytes of host memory used
-host_seconds 287.80 # Real time elapsed on the host
-host_tick_rate 6628539651 # Simulator tick rate (ticks/s)
+host_inst_rate 126888 # Simulator instruction rate (inst/s)
+host_mem_usage 280000 # Number of bytes of host memory used
+host_seconds 442.84 # Real time elapsed on the host
+host_tick_rate 4307932213 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56190549 # Number of instructions simulated
sim_seconds 1.907705 # Number of seconds simulated
system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated
system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses 147686 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688 # average LoadLockedReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15414.654688 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits 135219 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.084416 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 12467 # number of LoadLockedReq misses
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system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062680 # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses 6414671 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 28975.322669 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.577320 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.ReadReq_miss_latency 27426794500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_mshr_hits 250848 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency 19979077000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses 156551 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 54668.039693 # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51668.039693 # average StoreCondReq mshr miss latency
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system.cpu0.dcache.StoreCondReq_miss_latency 875946000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827877000 # number of StoreCondReq MSHR miss cycles
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system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 4258061 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609099 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.542507 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits 2612712 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 80387818274 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency 15269947736 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050789497 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9307.081114 # average number of cycles each access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 1082813738 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 32500 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 10672732 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 41596.652338 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 8080826 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 107814612774 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.242853 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2591906 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 1613056 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 35249024736 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.091715 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 10672732 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 41596.652338 # average overall miss latency
+system.cpu0.dcache.occ_%::0 0.863629 # Average percentage of cache occupancy
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system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 8080826 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 107814612774 # number of overall miss cycles
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system.cpu0.dcache.overall_mshr_hits 1613056 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 35249024736 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 1690651997 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 70526783 # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses 6456937 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 15194.125887 # average ReadReq miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 5806694 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_latency 9879873999 # number of ReadReq miss cycles
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system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated
system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads
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system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.809571 # average WriteReq mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency
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system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu1.fetch.rateDist::total 38118943 # Number of instructions fetched each cycle (Total)
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-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.810666 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 2.233553 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1423763998 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 455578 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 455578 # number of Writeback hits
+system.l2c.Writeback_accesses::0 455578 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 455578 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 455578 # number of Writeback hits
+system.l2c.Writeback_hits::total 455578 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 4.834791 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2522281 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52179.674113 # average overall miss latency
+system.l2c.demand_accesses::0 1543318 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 978963 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2522281 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 62510.658683 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 315728.455181 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
+system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency
-system.l2c.demand_hits 1893900 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1018788 # number of demand (read+write) hits
+system.l2c.demand_hits::1 875112 # number of demand (read+write) hits
+system.l2c.demand_hits::2 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1893900 # number of demand (read+write) hits
system.l2c.demand_miss_latency 32788715799 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.249132 # miss rate for demand accesses
-system.l2c.demand_misses 628381 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.339872 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.106083 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.demand_misses::0 524530 # number of demand (read+write) misses
+system.l2c.demand_misses::1 103851 # number of demand (read+write) misses
+system.l2c.demand_misses::2 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 628381 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 25198480438 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.249125 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 0.407151 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0.641867 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 628364 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2522281 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52179.674113 # average overall miss latency
+system.l2c.occ_%::0 0.065210 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.029545 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.380758 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 4273.595958 # Average occupied blocks per context
+system.l2c.occ_blocks::1 1936.249784 # Average occupied blocks per context
+system.l2c.occ_blocks::2 24953.333071 # Average occupied blocks per context
+system.l2c.overall_accesses::0 1543318 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 978963 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2522281 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 62510.658683 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 315728.455181 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
+system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1893900 # number of overall hits
+system.l2c.overall_hits::0 1018788 # number of overall hits
+system.l2c.overall_hits::1 875112 # number of overall hits
+system.l2c.overall_hits::2 0 # number of overall hits
+system.l2c.overall_hits::total 1893900 # number of overall hits
system.l2c.overall_miss_latency 32788715799 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.249132 # miss rate for overall accesses
-system.l2c.overall_misses 628381 # number of overall misses
+system.l2c.overall_miss_rate::0 0.339872 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.106083 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.overall_misses::0 524530 # number of overall misses
+system.l2c.overall_misses::1 103851 # number of overall misses
+system.l2c.overall_misses::2 0 # number of overall misses
+system.l2c.overall_misses::total 628381 # number of overall misses
system.l2c.overall_mshr_hits 17 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 25198480438 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.249125 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 0.407151 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0.641867 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 628364 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 2264235998 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:50:49
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:35:15
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1867362977500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 193554 # Simulator instruction rate (inst/s)
-host_mem_usage 276972 # Number of bytes of host memory used
-host_seconds 274.29 # Real time elapsed on the host
-host_tick_rate 6807960214 # Simulator tick rate (ticks/s)
+host_inst_rate 86499 # Simulator instruction rate (inst/s)
+host_mem_usage 277924 # Number of bytes of host memory used
+host_seconds 613.76 # Real time elapsed on the host
+host_tick_rate 3042478511 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 53090223 # Number of instructions simulated
sim_seconds 1.867363 # Number of seconds simulated
system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated
system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 214422 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 15515.537615 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits 192250 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.103404 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 22172 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081717 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 9342386 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 23884.018523 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits 7810012 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.164024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1532374 # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.116118 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses 219797 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.488950 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits 189796 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate 0.136494 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 30001 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136494 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6157245 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 49037.572489 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits 3926713 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.362261 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2230532 # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.064467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15499631 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 38794.252006 # average overall miss latency
+system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 11736725 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.242774 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3762906 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses
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+system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1786590 # number of ReadReq hits
+system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.148328 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 311153 # number of ReadReq misses
+system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.148327 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 130274 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 52273.201045 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 130274 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430447 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430447 # number of Writeback hits
+system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 430447 # number of Writeback hits
+system.l2c.Writeback_hits::total 430447 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 4.597861 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2398325 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52201.631966 # average overall miss latency
+system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
+system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency
-system.l2c.demand_hits 1786590 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits
+system.l2c.demand_hits::1 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.255068 # miss rate for demand accesses
-system.l2c.demand_misses 611735 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.demand_misses::0 611735 # number of demand (read+write) misses
+system.l2c.demand_misses::1 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 611735 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.255067 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2398325 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52201.631966 # average overall miss latency
+system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context
+system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
+system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1786590 # number of overall hits
+system.l2c.overall_hits::0 1786590 # number of overall hits
+system.l2c.overall_hits::1 0 # number of overall hits
+system.l2c.overall_hits::total 1786590 # number of overall hits
system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.255068 # miss rate for overall accesses
-system.l2c.overall_misses 611735 # number of overall misses
+system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.overall_misses::0 611735 # number of overall misses
+system.l2c.overall_misses::1 0 # number of overall misses
+system.l2c.overall_misses::total 611735 # number of overall misses
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.255067 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:06:05
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:27:41
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2430508 # Simulator instruction rate (inst/s)
-host_mem_usage 329972 # Number of bytes of host memory used
-host_seconds 100.32 # Real time elapsed on the host
-host_tick_rate 1218223693 # Simulator tick rate (ticks/s)
+host_inst_rate 1458389 # Simulator instruction rate (inst/s)
+host_mem_usage 317928 # Number of bytes of host memory used
+host_seconds 167.20 # Real time elapsed on the host
+host_tick_rate 730976871 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:30:43
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:30:29
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1809872 # Simulator instruction rate (inst/s)
-host_mem_usage 339332 # Number of bytes of host memory used
-host_seconds 134.73 # Real time elapsed on the host
-host_tick_rate 2719868473 # Simulator tick rate (ticks/s)
+host_inst_rate 794629 # Simulator instruction rate (inst/s)
+host_mem_usage 325576 # Number of bytes of host memory used
+host_seconds 306.85 # Real time elapsed on the host
+host_tick_rate 1194166006 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366435 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.871490 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3569.622607 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.354611 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 726.242454 # Average occupied blocks per context
system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.010976 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.262444 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 359.659901 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8599.756547 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
All Rights Reserved
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:30:53
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:50:08
+M5 executing on SC2B0619
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 635652 # Simulator instruction rate (inst/s)
-host_mem_usage 347576 # Number of bytes of host memory used
-host_seconds 424.28 # Real time elapsed on the host
-host_tick_rate 388188748 # Simulator tick rate (ticks/s)
+host_inst_rate 1130966 # Simulator instruction rate (inst/s)
+host_mem_usage 323116 # Number of bytes of host memory used
+host_seconds 238.47 # Real time elapsed on the host
+host_tick_rate 690673696 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269695959 # Number of instructions simulated
sim_seconds 0.164702 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:34:05
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:52:35
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 839358 # Simulator instruction rate (inst/s)
-host_mem_usage 328912 # Number of bytes of host memory used
-host_seconds 321.31 # Real time elapsed on the host
-host_tick_rate 1189158712 # Simulator tick rate (ticks/s)
+host_inst_rate 855655 # Simulator instruction rate (inst/s)
+host_mem_usage 331116 # Number of bytes of host memory used
+host_seconds 315.19 # Real time elapsed on the host
+host_tick_rate 1212247082 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269695959 # Number of instructions simulated
sim_seconds 0.382091 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.995395 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4077.137530 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 20188.783508 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.325918 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 667.480800 # Average occupied blocks per context
system.cpu.icache.overall_accesses 217696172 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.198854 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.350512 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 6516.062046 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 11485.589337 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2067619 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.158560 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:45
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:53:46
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1252342 # Simulator instruction rate (inst/s)
-host_mem_usage 201956 # Number of bytes of host memory used
-host_seconds 1194.32 # Real time elapsed on the host
-host_tick_rate 727261872 # Simulator tick rate (ticks/s)
+host_inst_rate 1408369 # Simulator instruction rate (inst/s)
+host_mem_usage 192628 # Number of bytes of host memory used
+host_seconds 1062.01 # Real time elapsed on the host
+host_tick_rate 817869724 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495700470 # Number of instructions simulated
sim_seconds 0.868585 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:39:28
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:54:07
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1459378 # Simulator instruction rate (inst/s)
-host_mem_usage 198104 # Number of bytes of host memory used
-host_seconds 1024.89 # Real time elapsed on the host
-host_tick_rate 1680505604 # Simulator tick rate (ticks/s)
+host_inst_rate 925832 # Simulator instruction rate (inst/s)
+host_mem_usage 200280 # Number of bytes of host memory used
+host_seconds 1615.52 # Real time elapsed on the host
+host_tick_rate 1066115675 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495700470 # Number of instructions simulated
sim_seconds 1.722332 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.997757 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4086.814341 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 38769.912986 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 887.538461 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.111890 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.413414 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3666.426168 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13546.751396 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2521227 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:50:56
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:18:35
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
-host_inst_rate 241043 # Simulator instruction rate (inst/s)
-host_mem_usage 197116 # Number of bytes of host memory used
-host_seconds 1558.12 # Real time elapsed on the host
-host_tick_rate 86640473 # Simulator tick rate (ticks/s)
+host_inst_rate 119207 # Simulator instruction rate (inst/s)
+host_mem_usage 198920 # Number of bytes of host memory used
+host_seconds 3150.62 # Real time elapsed on the host
+host_tick_rate 42847667 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.134997 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.804192 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3293.970402 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.890401 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1823.540410 # Average occupied blocks per context
system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.106709 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011557 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3496.652993 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 378.690415 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:12
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:33:35
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 3427488 # Simulator instruction rate (inst/s)
-host_mem_usage 203296 # Number of bytes of host memory used
-host_seconds 116.31 # Real time elapsed on the host
-host_tick_rate 1713741057 # Simulator tick rate (ticks/s)
+host_inst_rate 1825585 # Simulator instruction rate (inst/s)
+host_mem_usage 190564 # Number of bytes of host memory used
+host_seconds 218.38 # Real time elapsed on the host
+host_tick_rate 912792158 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:06:21
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:32
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2382679 # Simulator instruction rate (inst/s)
-host_mem_usage 212620 # Number of bytes of host memory used
-host_seconds 167.32 # Real time elapsed on the host
-host_tick_rate 3390857898 # Simulator tick rate (ticks/s)
+host_inst_rate 860135 # Simulator instruction rate (inst/s)
+host_mem_usage 198216 # Number of bytes of host memory used
+host_seconds 463.49 # Real time elapsed on the host
+host_tick_rate 1224083493 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.802954 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3288.899192 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.876526 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1795.124700 # Average occupied blocks per context
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.101996 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011352 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3342.203160 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 371.972955 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:52:13
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:45:31
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 233856 # Simulator instruction rate (inst/s)
-host_mem_usage 197400 # Number of bytes of host memory used
-host_seconds 7795.57 # Real time elapsed on the host
-host_tick_rate 90456464 # Simulator tick rate (ticks/s)
+host_inst_rate 178423 # Simulator instruction rate (inst/s)
+host_mem_usage 199584 # Number of bytes of host memory used
+host_seconds 10217.56 # Real time elapsed on the host
+host_tick_rate 69014447 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.705159 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.104513 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.788136 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1614.102824 # Average occupied blocks per context
system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.927694 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.046416 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 30398.691034 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1520.954518 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:41:45
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:10:59
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 3366150 # Simulator instruction rate (inst/s)
-host_mem_usage 202468 # Number of bytes of host memory used
-host_seconds 596.82 # Real time elapsed on the host
-host_tick_rate 1683437750 # Simulator tick rate (ticks/s)
+host_inst_rate 2073139 # Simulator instruction rate (inst/s)
+host_mem_usage 190360 # Number of bytes of host memory used
+host_seconds 969.06 # Real time elapsed on the host
+host_tick_rate 1036792835 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:09:09
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 01:51:28
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
-host_inst_rate 2471520 # Simulator instruction rate (inst/s)
-host_mem_usage 211800 # Number of bytes of host memory used
-host_seconds 812.86 # Real time elapsed on the host
-host_tick_rate 3463041314 # Simulator tick rate (ticks/s)
+host_inst_rate 1237577 # Simulator instruction rate (inst/s)
+host_mem_usage 198020 # Number of bytes of host memory used
+host_seconds 1623.32 # Real time elapsed on the host
+host_tick_rate 1734066560 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999804 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.198740 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.721885 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1478.420115 # Average occupied blocks per context
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.926943 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.046880 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 30374.076068 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1536.161417 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:55:23
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:28:19
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 254468 # Simulator instruction rate (inst/s)
-host_mem_usage 199708 # Number of bytes of host memory used
-host_seconds 312.78 # Real time elapsed on the host
-host_tick_rate 86754409 # Simulator tick rate (ticks/s)
+host_inst_rate 172212 # Simulator instruction rate (inst/s)
+host_mem_usage 201796 # Number of bytes of host memory used
+host_seconds 462.17 # Real time elapsed on the host
+host_tick_rate 58711424 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027135 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.995440 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4077.324152 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.936032 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1916.994169 # Average occupied blocks per context
system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.089962 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.474123 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2947.876007 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15536.049051 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:57:23
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:31
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 5366735 # Simulator instruction rate (inst/s)
-host_mem_usage 205860 # Number of bytes of host memory used
-host_seconds 16.46 # Real time elapsed on the host
-host_tick_rate 2686413423 # Simulator tick rate (ticks/s)
+host_inst_rate 3163275 # Simulator instruction rate (inst/s)
+host_mem_usage 192676 # Number of bytes of host memory used
+host_seconds 27.93 # Real time elapsed on the host
+host_tick_rate 1583437342 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:10:15
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:21:01
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2287584 # Simulator instruction rate (inst/s)
-host_mem_usage 215192 # Number of bytes of host memory used
-host_seconds 38.62 # Real time elapsed on the host
-host_tick_rate 3500174868 # Simulator tick rate (ticks/s)
+host_inst_rate 1182325 # Simulator instruction rate (inst/s)
+host_mem_usage 200332 # Number of bytes of host memory used
+host_seconds 74.72 # Real time elapsed on the host
+host_tick_rate 1809050434 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.995818 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4078.872537 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.913950 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1871.768668 # Average occupied blocks per context
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.081795 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.475328 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2680.267907 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15575.557767 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall time(4026527848, 4026528248, ...)
+warn: ignoring syscall time(4026528248, 4026527848, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527400, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527312, 1, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 413, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 414, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527288, 4026527688, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526960, 409, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527040, 409, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527000, 409, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526312, 19045, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526832, 409, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526936, 409, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527008, 4026527408, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526560, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 18732, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526632, 409, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526736, 0, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527744, 225, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527096, 4026527496, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526648, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526824, 0, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 1879089152, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 1595768, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 20500, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 4026526436, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526056, 7004192, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527512, 4, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525760, 0, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:05:08
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:33:19
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2400032 # Simulator instruction rate (inst/s)
-host_mem_usage 206680 # Number of bytes of host memory used
-host_seconds 56.72 # Real time elapsed on the host
-host_tick_rate 1201405231 # Simulator tick rate (ticks/s)
+host_inst_rate 1397341 # Simulator instruction rate (inst/s)
+host_mem_usage 194632 # Number of bytes of host memory used
+host_seconds 97.43 # Real time elapsed on the host
+host_tick_rate 699480350 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.068149 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall time(4026527848, 4026528248, ...)
+warn: ignoring syscall time(4026528248, 4026527848, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527400, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527312, 1, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 413, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 414, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527288, 4026527688, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526960, 409, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527040, 409, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527000, 409, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526312, 19045, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526832, 409, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526936, 409, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527008, 4026527408, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526560, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 18732, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526632, 409, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526736, 0, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527744, 225, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527096, 4026527496, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526648, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526824, 0, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 1879089152, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 1595768, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 20500, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 4026526436, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526056, 7004192, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527512, 4, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525760, 0, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:31:17
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:34:57
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1881110 # Simulator instruction rate (inst/s)
-host_mem_usage 216040 # Number of bytes of host memory used
-host_seconds 72.37 # Real time elapsed on the host
-host_tick_rate 2810156861 # Simulator tick rate (ticks/s)
+host_inst_rate 755710 # Simulator instruction rate (inst/s)
+host_mem_usage 202292 # Number of bytes of host memory used
+host_seconds 180.15 # Real time elapsed on the host
+host_tick_rate 1128944281 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.203377 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.997952 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4087.609698 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.978865 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 2004.715107 # Average occupied blocks per context
system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.120206 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.469380 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3938.922202 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15380.640176 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
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prefetch_data_accesses_only=false
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mshrs=10
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latency=1000
max_miss_count=0
mshrs=10
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Oct 22 2009 13:11:07
-M5 revision e406bb83c56f 6682 default qtip tip syscall-ioctl.patch
-M5 started Oct 22 2009 13:42:59
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:37:14
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:59:02
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:01:37
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_seconds 0.913189 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
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mshrs=10
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:13:47
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:02
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:57:51
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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latency=1000
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env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:30:56
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:58:19
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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env=
errout=cerr
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 12:07:21
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:44:07
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency
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system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
env=
errout=cerr
euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:51:42
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:01:12
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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latency=1000
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env=
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euid=100
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gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:16:45
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:41:35
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2678753 # Simulator instruction rate (inst/s)
-host_mem_usage 209892 # Number of bytes of host memory used
-host_seconds 34.31 # Real time elapsed on the host
-host_tick_rate 3461170696 # Simulator tick rate (ticks/s)
+host_inst_rate 611509 # Simulator instruction rate (inst/s)
+host_mem_usage 195576 # Number of bytes of host memory used
+host_seconds 150.29 # Real time elapsed on the host
+host_tick_rate 790125098 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118747 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.352056 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1442.022508 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.692396 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1418.025998 # Average occupied blocks per context
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.061290 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2008.334369 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13.724981 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:14:36
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:35:37
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2403614 # Simulator instruction rate (inst/s)
-host_mem_usage 202316 # Number of bytes of host memory used
-host_seconds 80.48 # Real time elapsed on the host
-host_tick_rate 1201810632 # Simulator tick rate (ticks/s)
+host_inst_rate 1979245 # Simulator instruction rate (inst/s)
+host_mem_usage 190260 # Number of bytes of host memory used
+host_seconds 97.74 # Real time elapsed on the host
+host_tick_rate 989625806 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.096723 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:30
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:37:15
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1857648 # Simulator instruction rate (inst/s)
-host_mem_usage 211672 # Number of bytes of host memory used
-host_seconds 104.13 # Real time elapsed on the host
-host_tick_rate 2598354088 # Simulator tick rate (ticks/s)
+host_inst_rate 890462 # Simulator instruction rate (inst/s)
+host_mem_usage 197912 # Number of bytes of host memory used
+host_seconds 217.24 # Real time elapsed on the host
+host_tick_rate 1245520491 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.270578 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.302049 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1237.193190 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.777132 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.081095 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:37:58
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:02:03
+M5 executing on SC2B0619
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 608858 # Simulator instruction rate (inst/s)
-host_mem_usage 220444 # Number of bytes of host memory used
-host_seconds 360.40 # Real time elapsed on the host
-host_tick_rate 361897269 # Simulator tick rate (ticks/s)
+host_inst_rate 1408387 # Simulator instruction rate (inst/s)
+host_mem_usage 196212 # Number of bytes of host memory used
+host_seconds 155.80 # Real time elapsed on the host
+host_tick_rate 837126295 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 219430973 # Number of instructions simulated
sim_seconds 0.130427 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:37:25
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:04:39
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 894535 # Simulator instruction rate (inst/s)
-host_mem_usage 201656 # Number of bytes of host memory used
-host_seconds 245.30 # Real time elapsed on the host
-host_tick_rate 1023073835 # Simulator tick rate (ticks/s)
+host_inst_rate 527252 # Simulator instruction rate (inst/s)
+host_mem_usage 203888 # Number of bytes of host memory used
+host_seconds 416.18 # Real time elapsed on the host
+host_tick_rate 603014388 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 219430973 # Number of instructions simulated
sim_seconds 0.250962 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.332384 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1361.446792 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 77197730 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55870.331950 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52870.072614 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.710588 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1455.283940 # Average occupied blocks per context
system.cpu.icache.overall_accesses 173494375 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.062047 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy
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+system.cpu.l2cache.occ_blocks::1 0.022985 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 6596 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52003.272804 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
boot_cpu_frequency=1
boot_osflags=a
hypervisor_addr=1099243257856
-hypervisor_bin=/dist/m5/system/binaries/q_new.bin
+hypervisor_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc
hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-hv.bin
init_param=0
kernel=
mem_mode=atomic
nvram=system.nvram
nvram_addr=133429198848
-nvram_bin=/dist/m5/system/binaries/nvram1
+nvram_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/nvram1
openboot_addr=1099243716608
-openboot_bin=/dist/m5/system/binaries/openboot_new.bin
+openboot_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/openboot_new.bin
partition_desc=system.partition_desc
partition_desc_addr=133445976064
-partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
+partition_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-md.bin
physmem=system.physmem
readfile=tests/halt.sh
reset_addr=1099243192320
-reset_bin=/dist/m5/system/binaries/reset_new.bin
+reset_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/reset_new.bin
rom=system.rom
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/disk.s10hw2
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/disk.s10hw2
read_only=true
[system.hypervisor_desc]
All Rights Reserved
-M5 compiled Apr 21 2009 18:38:50
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:39:20
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:38:31
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:45
+M5 executing on SC2B0619
command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second
info: No kernel set for full system simulation. Assuming you know what you're doing...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2338829 # Simulator instruction rate (inst/s)
-host_mem_usage 501616 # Number of bytes of host memory used
-host_seconds 953.11 # Real time elapsed on the host
-host_tick_rate 2343672 # Simulator tick rate (ticks/s)
+host_inst_rate 2688852 # Simulator instruction rate (inst/s)
+host_mem_usage 490548 # Number of bytes of host memory used
+host_seconds 829.04 # Real time elapsed on the host
+host_tick_rate 2694420 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 2229160714 # Number of instructions simulated
sim_seconds 1.116889 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jan 29 2010 09:13:03
-M5 revision 23ae96d82d21+ 6704+ default qtip tip inorder_hello_alpha
-M5 started Jan 29 2010 09:13:04
-M5 executing on zooks
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:21:00
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 23048 # Simulator instruction rate (inst/s)
-host_mem_usage 153228 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-host_tick_rate 112412599 # Simulator tick rate (ticks/s)
+host_inst_rate 37021 # Simulator instruction rate (inst/s)
+host_mem_usage 190468 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
+host_tick_rate 180549624 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000031 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.025315 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 103.689640 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56217.032967 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.063659 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 7277 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55521.594684 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005540 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52069.690265 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:06
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 01:04:08
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
-host_inst_rate 76035 # Simulator instruction rate (inst/s)
-host_mem_usage 189864 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 148017846 # Simulator tick rate (ticks/s)
+host_inst_rate 104903 # Simulator instruction rate (inst/s)
+host_mem_usage 190976 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 203948336 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6386 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:57:23
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:01:37
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 272186 # Simulator instruction rate (inst/s)
-host_mem_usage 192556 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 135226078 # Simulator tick rate (ticks/s)
+host_inst_rate 1228467 # Simulator instruction rate (inst/s)
+host_mem_usage 182556 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 587751371 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:17:21
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:02
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 244055 # Simulator instruction rate (inst/s)
-host_mem_usage 201804 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 1274748085 # Simulator tick rate (ticks/s)
+host_inst_rate 605866 # Simulator instruction rate (inst/s)
+host_mem_usage 190120 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 3109075847 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context
system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:07
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:44:06
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 18690 # Simulator instruction rate (inst/s)
-host_mem_usage 188768 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 56136046 # Simulator tick rate (ticks/s)
+host_inst_rate 86395 # Simulator instruction rate (inst/s)
+host_mem_usage 189960 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 257307637 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000007 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.011202 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 45.884316 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.043324 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 88.727286 # Average occupied blocks per context
system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.003380 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 110.762790 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:03
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:37:14
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 312515 # Simulator instruction rate (inst/s)
-host_mem_usage 191632 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 151541696 # Simulator tick rate (ticks/s)
+host_inst_rate 794145 # Simulator instruction rate (inst/s)
+host_mem_usage 181656 # Number of bytes of host memory used
+host_seconds 0.00 # Real time elapsed on the host
+host_tick_rate 371138444 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:17:22
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:06
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 89461 # Simulator instruction rate (inst/s)
-host_mem_usage 200972 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 597928210 # Simulator tick rate (ticks/s)
+host_inst_rate 400715 # Simulator instruction rate (inst/s)
+host_mem_usage 189300 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 2582342449 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context
system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 27 2009 00:45:04
-M5 revision 44a3d32f3217 6414 default qtip tip runnableagainstatupdate.patch
-M5 started Jul 27 2009 00:45:05
-M5 executing on fajita
+M5 compiled Feb 25 2010 04:11:39
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:11:44
+M5 executing on SC2B0619
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 9392 # Simulator instruction rate (inst/s)
-host_mem_usage 189932 # Number of bytes of host memory used
-host_seconds 0.59 # Real time elapsed on the host
-host_tick_rate 4693453 # Simulator tick rate (ticks/s)
+host_inst_rate 1074248 # Simulator instruction rate (inst/s)
+host_mem_usage 180696 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 511253720 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5498 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jan 31 2010 17:08:14
-M5 revision 01508015f86b 6964 default qtip tip inorder_hello_mips
-M5 started Jan 31 2010 17:08:15
-M5 executing on zooks
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:23
+M5 executing on SC2B0619
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 19644 # Simulator instruction rate (inst/s)
-host_mem_usage 155856 # Number of bytes of host memory used
-host_seconds 0.30 # Real time elapsed on the host
-host_tick_rate 98307932 # Simulator tick rate (ticks/s)
+host_inst_rate 38577 # Simulator instruction rate (inst/s)
+host_mem_usage 191640 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+host_tick_rate 192989817 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.021604 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 88.491296 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context
system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jan 2 2010 07:01:31
-M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
-M5 started Jan 2 2010 07:03:10
-M5 executing on fajita
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:23
+M5 executing on SC2B0619
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
-host_inst_rate 48407 # Simulator instruction rate (inst/s)
-host_mem_usage 206048 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-host_tick_rate 131379529 # Simulator tick rate (ticks/s)
+host_inst_rate 82851 # Simulator instruction rate (inst/s)
+host_mem_usage 191760 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 224354167 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5169 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context
system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jan 2 2010 07:01:31
-M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
-M5 started Jan 2 2010 07:03:10
-M5 executing on fajita
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:22
+M5 executing on SC2B0619
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
-host_inst_rate 449580 # Simulator instruction rate (inst/s)
-host_mem_usage 197348 # Number of bytes of host memory used
+host_inst_rate 1101929 # Simulator instruction rate (inst/s)
+host_mem_usage 183300 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 220987561 # Simulator tick rate (ticks/s)
+host_tick_rate 525428314 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jan 2 2010 07:01:31
-M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
-M5 started Jan 2 2010 07:03:09
-M5 executing on fajita
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:22
+M5 executing on SC2B0619
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
---------- Begin Simulation Statistics ----------
-host_inst_rate 21056 # Simulator instruction rate (inst/s)
-host_mem_usage 204976 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-host_tick_rate 118397165 # Simulator tick rate (ticks/s)
+host_inst_rate 534293 # Simulator instruction rate (inst/s)
+host_mem_usage 190944 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 2928316372 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000033 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.021457 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 87.887695 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.065174 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 133.475693 # Average occupied blocks per context
system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005638 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 184.758016 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/power/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 13202840. This will break if not /dev/zero.
For more information see: http://www.m5sim.org/warn/3a2134f6
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Oct 15 2009 15:43:13
-M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip
-M5 started Oct 15 2009 15:49:09
-M5 executing on frontend01
+M5 compiled Feb 24 2010 23:13:07
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 103409 # Simulator instruction rate (inst/s)
-host_mem_usage 271924 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 212174700 # Simulator tick rate (ticks/s)
+host_inst_rate 51828 # Simulator instruction rate (inst/s)
+host_mem_usage 189300 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
+host_tick_rate 106468871 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5800 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.016127 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 66.056188 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.077734 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 159.198376 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005513 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 180.652204 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/power/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero.
For more information see: http://www.m5sim.org/warn/3a2134f6
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Oct 15 2009 15:43:13
-M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip
-M5 started Oct 15 2009 15:49:56
-M5 executing on frontend01
+M5 compiled Feb 24 2010 23:13:07
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 259216 # Simulator instruction rate (inst/s)
-host_mem_usage 263696 # Number of bytes of host memory used
+host_inst_rate 277162 # Simulator instruction rate (inst/s)
+host_mem_usage 181156 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 128114508 # Simulator tick rate (ticks/s)
+host_tick_rate 136566988 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5801 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:05:07
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:37:59
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 314858 # Simulator instruction rate (inst/s)
-host_mem_usage 193720 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 157107957 # Simulator tick rate (ticks/s)
+host_inst_rate 897027 # Simulator instruction rate (inst/s)
+host_mem_usage 182692 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 434663663 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:52
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:37:59
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 165633 # Simulator instruction rate (inst/s)
-host_mem_usage 203084 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 893371492 # Simulator tick rate (ticks/s)
+host_inst_rate 462498 # Simulator instruction rate (inst/s)
+host_mem_usage 190336 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 2452978454 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.020107 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 82.357482 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.057478 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 117.715481 # Average occupied blocks per context
system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.004176 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 136.844792 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:11:29
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 23019 # Simulator instruction rate (inst/s)
-host_mem_usage 193704 # Number of bytes of host memory used
-host_seconds 0.41 # Real time elapsed on the host
-host_tick_rate 13302912 # Simulator tick rate (ticks/s)
+host_inst_rate 940985 # Simulator instruction rate (inst/s)
+host_mem_usage 185436 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 530148334 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9519 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Aug 8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug 8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:11:30
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 21415 # Simulator instruction rate (inst/s)
-host_mem_usage 201336 # Number of bytes of host memory used
-host_seconds 0.44 # Real time elapsed on the host
-host_tick_rate 66853602 # Simulator tick rate (ticks/s)
+host_inst_rate 605496 # Simulator instruction rate (inst/s)
+host_mem_usage 193040 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1857026858 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9519 # Number of instructions simulated
sim_seconds 0.000030 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.019744 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.052069 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 6887 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.003910 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
numPhysIntRegs=256
numROBEntries=192
numRobs=1
-numThreads=1
+numThreads=2
phase=0
predType=tournament
progress_interval=0
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:05
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:32
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 36918 # Simulator instruction rate (inst/s)
-host_mem_usage 190384 # Number of bytes of host memory used
-host_seconds 0.35 # Real time elapsed on the host
-host_tick_rate 41160042 # Simulator tick rate (ticks/s)
+host_inst_rate 95914 # Simulator instruction rate (inst/s)
+host_mem_usage 191488 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 106648956 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 12773 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction
system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses::0 3925 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3925 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35473.913043 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::0 3580 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3580 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.087898 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 345 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 345 # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate 0.087898 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33703.947368 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::0 970 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 970 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles
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-system.cpu.dcache.WriteReq_misses::0 760 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 760 # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 5655 # number of demand (read+write) accesses
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-system.cpu.dcache.demand_accesses::total 5655 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
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system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles
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-system.cpu.dcache.demand_misses::0 1105 # number of demand (read+write) misses
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-system.cpu.dcache.demand_misses::total 1105 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate 0.195402 # miss rate for demand accesses
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system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses
system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 4550 # number of overall hits
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system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles
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system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses::0 4113 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_misses::total 841 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 4113 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 4113 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 3272 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 3272 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.204474 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 841 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 841 # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate 0.204474 # miss rate for demand accesses
+system.cpu.icache.demand_misses 841 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses
system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::0 4113 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 4113 # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0 0.156877 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 321.284131 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35793.697979 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 3272 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 3272 # number of overall hits
+system.cpu.icache.overall_hits 3272 # number of overall hits
system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.204474 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 841 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 841 # number of overall misses
+system.cpu.icache.overall_miss_rate 0.204474 # miss rate for overall accesses
+system.cpu.icache.overall_misses 841 # number of overall misses
system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.150498 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::0 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::0 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::0 825 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 825 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34555.285541 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::0 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::0 0.997576 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::0 823 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 823 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_miss_rate 0.997576 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997576 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses::0 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34482.142857 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses::0 28 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses::0 971 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34568.627451 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::0 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::0 0.997940 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::0 969 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 969 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_rate 0.997940 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997940 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::0 971 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0 0.013297 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 435.713880 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34568.627451 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits::0 2 # number of overall hits
-system.cpu.l2cache.overall_hits::1 0 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2 # number of overall hits
+system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::0 0.997940 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::0 969 # number of overall misses
-system.cpu.l2cache.overall_misses::1 0 # number of overall misses
-system.cpu.l2cache.overall_misses::total 969 # number of overall misses
+system.cpu.l2cache.overall_miss_rate 0.997940 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 969 # number of overall misses
system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997940 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:24
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:00
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1945 # Simulator instruction rate (inst/s)
-host_mem_usage 190344 # Number of bytes of host memory used
-host_seconds 7.43 # Real time elapsed on the host
-host_tick_rate 3735278 # Simulator tick rate (ticks/s)
+host_inst_rate 72869 # Simulator instruction rate (inst/s)
+host_mem_usage 190800 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+host_tick_rate 139786869 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
sim_seconds 0.000028 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.026530 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 108.665251 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.110760 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 226.836007 # Average occupied blocks per context
system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.007680 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 251.642612 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:05:08
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:01
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 587404 # Simulator instruction rate (inst/s)
-host_mem_usage 193520 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 292299724 # Simulator tick rate (ticks/s)
+host_inst_rate 1098364 # Simulator instruction rate (inst/s)
+host_mem_usage 182400 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 540894569 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
sim_seconds 0.000008 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:53
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:01
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 286976 # Simulator instruction rate (inst/s)
-host_mem_usage 202788 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 804151064 # Simulator tick rate (ticks/s)
+host_inst_rate 227392 # Simulator instruction rate (inst/s)
+host_mem_usage 190044 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 637540839 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
sim_seconds 0.000043 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.023864 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.074743 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.005323 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 174.433606 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=atomic
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=2
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:10:46
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:12
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1870335522500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 4214021 # Simulator instruction rate (inst/s)
-host_mem_usage 277380 # Number of bytes of host memory used
-host_seconds 14.99 # Real time elapsed on the host
-host_tick_rate 124797908529 # Simulator tick rate (ticks/s)
+host_inst_rate 2090501 # Simulator instruction rate (inst/s)
+host_mem_usage 278608 # Number of bytes of host memory used
+host_seconds 30.21 # Real time elapsed on the host
+host_tick_rate 61910551280 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63154034 # Number of instructions simulated
sim_seconds 1.870336 # Number of seconds simulated
sim_ticks 1870335522500 # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses
-system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses
-system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses
-system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits
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+system.cpu0.dcache.WriteReq_misses::0 373808 # number of WriteReq misses
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.dcache.occ_%::0 0.985990 # Average percentage of cache occupancy
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system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 12672559 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dtb.write_acv 99 # DTB write access violations
system.cpu0.dtb.write_hits 5936899 # DTB write hits
system.cpu0.dtb.write_misses 726 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses
+system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits
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+system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks.
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
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+system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
+system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 0 # average overall miss latency
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41727 # number of demand (read+write) misses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 41727 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 0 # average overall miss latency
+system.iocache.occ_%::1 0.027215 # Average percentage of cache occupancy
+system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41727 # number of overall misses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 41727 # number of overall misses
+system.iocache.overall_misses::total 41727 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1759731 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 964536 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses
-system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 427641 # number of Writeback hits
+system.l2c.ReadExReq_accesses::0 282023 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1 24224 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 306247 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 282023 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 24224 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 306247 # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0 2581928 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 142339 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2724267 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0 1623113 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 136618 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1759731 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0 0.371356 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.040193 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses::0 117429 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 7578 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 125007 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 117429 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 7578 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 125007 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 427641 # number of Writeback hits
+system.l2c.Writeback_hits::total 427641 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 1.788900 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 0 # average overall miss latency
+system.l2c.demand_accesses::0 2863951 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 166563 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3030514 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency
+system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits 1759731 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1623113 # number of demand (read+write) hits
+system.l2c.demand_hits::1 136618 # number of demand (read+write) hits
+system.l2c.demand_hits::2 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1759731 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses
-system.l2c.demand_misses 1270783 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.433261 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.179782 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.demand_misses::0 1240838 # number of demand (read+write) misses
+system.l2c.demand_misses::1 29945 # number of demand (read+write) misses
+system.l2c.demand_misses::2 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1270783 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 0 # average overall miss latency
+system.l2c.occ_%::0 0.079636 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.003863 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.382298 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 5219.016701 # Average occupied blocks per context
+system.l2c.occ_blocks::1 253.146931 # Average occupied blocks per context
+system.l2c.occ_blocks::2 25054.312004 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2863951 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 166563 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3030514 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency
+system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits 1759731 # number of overall hits
+system.l2c.overall_hits::0 1623113 # number of overall hits
+system.l2c.overall_hits::1 136618 # number of overall hits
+system.l2c.overall_hits::2 0 # number of overall hits
+system.l2c.overall_hits::total 1759731 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses
-system.l2c.overall_misses 1270783 # number of overall misses
+system.l2c.overall_miss_rate::0 0.433261 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.179782 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.overall_misses::0 1240838 # number of overall misses
+system.l2c.overall_misses::1 29945 # number of overall misses
+system.l2c.overall_misses::2 0 # number of overall misses
+system.l2c.overall_misses::total 1270783 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=atomic
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:10:46
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332258000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 4370209 # Simulator instruction rate (inst/s)
-host_mem_usage 276044 # Number of bytes of host memory used
-host_seconds 13.74 # Real time elapsed on the host
-host_tick_rate 133154437863 # Simulator tick rate (ticks/s)
+host_inst_rate 2156504 # Simulator instruction rate (inst/s)
+host_mem_usage 277176 # Number of bytes of host memory used
+host_seconds 27.84 # Real time elapsed on the host
+host_tick_rate 65706739181 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60038305 # Number of instructions simulated
sim_seconds 1.829332 # Number of seconds simulated
sim_ticks 1829332258000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses
-system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses
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system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
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system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 1.727246 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 0 # average overall miss latency
+system.l2c.demand_accesses::0 2963417 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2963417 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits 1696652 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits
+system.l2c.demand_hits::1 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses
-system.l2c.demand_misses 1266765 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses
+system.l2c.demand_misses::1 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 0 # average overall miss latency
+system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context
+system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits 1696652 # number of overall hits
+system.l2c.overall_hits::0 1696652 # number of overall hits
+system.l2c.overall_hits::1 0 # number of overall hits
+system.l2c.overall_hits::total 1696652 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses
-system.l2c.overall_misses 1266765 # number of overall misses
+system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.overall_misses::0 1266765 # number of overall misses
+system.l2c.overall_misses::1 0 # number of overall misses
+system.l2c.overall_misses::total 1266765 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=2
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:10:47
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:33:27
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1972135461000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1978894 # Simulator instruction rate (inst/s)
-host_mem_usage 274156 # Number of bytes of host memory used
-host_seconds 30.03 # Real time elapsed on the host
-host_tick_rate 65677834484 # Simulator tick rate (ticks/s)
+host_inst_rate 561145 # Simulator instruction rate (inst/s)
+host_mem_usage 275328 # Number of bytes of host memory used
+host_seconds 105.89 # Real time elapsed on the host
+host_tick_rate 18624028525 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 59420593 # Number of instructions simulated
sim_seconds 1.972135 # Number of seconds simulated
sim_ticks 1972135461000 # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses 192630 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_accesses::0 192630 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 192630 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14259.465279 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits 175911 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0 175911 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 175911 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.086793 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 16719 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.086793 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0 16719 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 16719 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086793 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.086793 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses 8488393 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_accesses::0 8488393 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8488393 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 25694.266311 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits 7449690 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::0 7449690 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7449690 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.122367 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1038703 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_miss_rate::0 0.122367 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0 1038703 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1038703 # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122367 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122367 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses 191666 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_accesses::0 191666 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 191666 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55344.484086 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits 163357 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::0 163357 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 163357 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate 0.147700 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 28309 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.147700 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0 28309 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 28309 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147700 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.147700 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 5847430 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_accesses::0 5847430 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5847430 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 55891.373878 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits 5468175 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::0 5468175 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 5468175 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.064858 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 379255 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_miss_rate::0 0.064858 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0 379255 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 379255 # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064858 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency
+system.cpu0.dcache.demand_accesses::0 14335823 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 14335823 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 33770.954076 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 12917865 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::0 12917865 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 12917865 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.098910 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 1417958 # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate::0 0.098910 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu0.dcache.demand_misses::0 1417958 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1417958 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.098910 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::0 0.098910 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 14335823 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 33770.954076 # average overall miss latency
+system.cpu0.dcache.occ_%::0 0.983612 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 503.609177 # Average occupied blocks per context
+system.cpu0.dcache.overall_accesses::0 14335823 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 14335823 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 33770.954076 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 12917865 # number of overall hits
+system.cpu0.dcache.overall_hits::0 12917865 # number of overall hits
+system.cpu0.dcache.overall_hits::1 0 # number of overall hits
+system.cpu0.dcache.overall_hits::total 12917865 # number of overall hits
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dtb.write_acv 115 # DTB write access violations
system.cpu0.dtb.write_hits 6040102 # DTB write hits
system.cpu0.dtb.write_misses 798 # DTB write misses
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses
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system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency
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system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency
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system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.numCycles 3944270922 # number of cpu cycles simulated
system.cpu0.num_insts 54155641 # Number of instructions executed
system.cpu0.num_refs 14946215 # Number of memory references
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system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency
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system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles
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system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles
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system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses
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system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
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system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits 9848 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::0 9848 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 9848 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles
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+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.197392 # miss rate for StoreCondReq accesses
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system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197392 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.197392 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 650008 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_avg_miss_latency::0 54644.846691 # average WriteReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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+system.cpu1.dcache.WriteReq_hits::0 623656 # number of WriteReq hits
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system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles
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+system.cpu1.dcache.WriteReq_miss_rate::0 0.040541 # miss rate for WriteReq accesses
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system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.040541 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency
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+system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles
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-system.cpu1.dcache.demand_misses 62092 # number of demand (read+write) misses
+system.cpu1.dcache.demand_miss_rate::0 0.037169 # miss rate for demand accesses
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system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.demand_mshr_miss_rate::0 0.037169 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.overall_avg_miss_latency 32269.608001 # average overall miss latency
+system.cpu1.dcache.occ_%::0 0.759529 # Average percentage of cache occupancy
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+system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1608459 # number of overall hits
+system.cpu1.dcache.overall_hits::0 1608459 # number of overall hits
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+system.l2c.ReadReq_mshr_miss_rate::0 0.156063 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 2.550363 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 127238 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 50741.170091 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0 120870 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 6368 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 127238 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 53414.453545 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 1013851.287688 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 127238 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 120870 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 6368 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 127238 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.052685 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 19.980842 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430351 # number of Writeback hits
+system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 430351 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 430351 # number of Writeback hits
+system.l2c.Writeback_hits::total 430351 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 4.554189 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency
+system.l2c.demand_accesses::0 2255308 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 141811 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2397119 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 54160.431067 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 1309581.638928 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
+system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency
-system.l2c.demand_hits 1782886 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1665469 # number of demand (read+write) hits
+system.l2c.demand_hits::1 117417 # number of demand (read+write) hits
+system.l2c.demand_hits::2 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1782886 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.256238 # miss rate for demand accesses
-system.l2c.demand_misses 614233 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.261534 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.172018 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.demand_misses::0 589839 # number of demand (read+write) misses
+system.l2c.demand_misses::1 24394 # number of demand (read+write) misses
+system.l2c.demand_misses::2 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 614233 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.256233 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 0.272345 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 4.331272 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2397119 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52009.472790 # average overall miss latency
+system.l2c.occ_%::0 0.090499 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.002713 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.377667 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 5930.966720 # Average occupied blocks per context
+system.l2c.occ_blocks::1 177.784506 # Average occupied blocks per context
+system.l2c.occ_blocks::2 24750.754224 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2255308 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 141811 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2397119 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 54160.431067 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 1309581.638928 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
+system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1782886 # number of overall hits
+system.l2c.overall_hits::0 1665469 # number of overall hits
+system.l2c.overall_hits::1 117417 # number of overall hits
+system.l2c.overall_hits::2 0 # number of overall hits
+system.l2c.overall_hits::total 1782886 # number of overall hits
system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.256238 # miss rate for overall accesses
-system.l2c.overall_misses 614233 # number of overall misses
+system.l2c.overall_miss_rate::0 0.261534 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.172018 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.overall_misses::0 589839 # number of overall misses
+system.l2c.overall_misses::1 24394 # number of overall misses
+system.l2c.overall_misses::2 0 # number of overall misses
+system.l2c.overall_misses::total 614233 # number of overall misses
system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.256233 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 0.272345 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 4.331272 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:10:46
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:12
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1930164593000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1870819 # Simulator instruction rate (inst/s)
-host_mem_usage 272832 # Number of bytes of host memory used
-host_seconds 30.04 # Real time elapsed on the host
-host_tick_rate 64245310717 # Simulator tick rate (ticks/s)
+host_inst_rate 828053 # Simulator instruction rate (inst/s)
+host_mem_usage 274124 # Number of bytes of host memory used
+host_seconds 67.88 # Real time elapsed on the host
+host_tick_rate 28436098912 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56205703 # Number of instructions simulated
sim_seconds 1.930165 # Number of seconds simulated
sim_ticks 1930164593000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses
+system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency
+system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1710971 # number of ReadReq hits
+system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 307593 # number of ReadReq misses
+system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0 126223 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 126223 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 52001.810288 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 126223 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 126223 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430459 # number of Writeback hits
+system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 430459 # number of Writeback hits
+system.l2c.Writeback_hits::total 430459 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 4.436562 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency
+system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
+system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
-system.l2c.demand_hits 1710971 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits
+system.l2c.demand_hits::1 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses
-system.l2c.demand_misses 612229 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.demand_misses::0 612229 # number of demand (read+write) misses
+system.l2c.demand_misses::1 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 612229 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency
+system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context
+system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
+system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1710971 # number of overall hits
+system.l2c.overall_hits::0 1710971 # number of overall hits
+system.l2c.overall_hits::1 0 # number of overall hits
+system.l2c.overall_hits::total 1710971 # number of overall hits
system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses
-system.l2c.overall_misses 612229 # number of overall misses
+system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.overall_misses::0 612229 # number of overall misses
+system.l2c.overall_misses::1 0 # number of overall misses
+system.l2c.overall_misses::total 612229 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:57:23
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:02:04
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 3016706 # Simulator instruction rate (inst/s)
-host_mem_usage 191632 # Number of bytes of host memory used
+host_inst_rate 3013906 # Simulator instruction rate (inst/s)
+host_mem_usage 181592 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
-host_tick_rate 1506280802 # Simulator tick rate (ticks/s)
+host_tick_rate 1504585693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:17:24
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:33:34
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2302773 # Simulator instruction rate (inst/s)
-host_mem_usage 201032 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
-host_tick_rate 3391978546 # Simulator tick rate (ticks/s)
+host_inst_rate 1409192 # Simulator instruction rate (inst/s)
+host_mem_usage 189184 # Number of bytes of host memory used
+host_seconds 0.36 # Real time elapsed on the host
+host_tick_rate 2076450214 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000737 # Number of seconds simulated
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.069937 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 286.463742 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.129067 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 264.328816 # Average occupied blocks per context
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.011298 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 370.220381 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=4
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:17:24
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:22:16
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 4530821 # Simulator instruction rate (inst/s)
-host_mem_usage 1125932 # Number of bytes of host memory used
-host_seconds 0.44 # Real time elapsed on the host
-host_tick_rate 566039081 # Simulator tick rate (ticks/s)
+host_inst_rate 1651065 # Simulator instruction rate (inst/s)
+host_mem_usage 1114084 # Number of bytes of host memory used
+host_seconds 1.21 # Real time elapsed on the host
+host_tick_rate 206342663 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.l2c.overall_miss_latency 0 # number of overall miss cycles
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system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
type=EioProcess
chkpt=
errout=cerr
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
latency=10000
max_miss_count=0
mshrs=92
-prefetch_cache_check_push=true
+num_cpus=4
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:17:25
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:28:17
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2185563 # Simulator instruction rate (inst/s)
-host_mem_usage 208428 # Number of bytes of host memory used
-host_seconds 0.92 # Real time elapsed on the host
-host_tick_rate 806662952 # Simulator tick rate (ticks/s)
+host_inst_rate 1192031 # Simulator instruction rate (inst/s)
+host_mem_usage 196580 # Number of bytes of host memory used
+host_seconds 1.68 # Real time elapsed on the host
+host_tick_rate 440023932 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1999941 # Number of instructions simulated
sim_seconds 0.000738 # Number of seconds simulated
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy
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system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.occ_%::0 0.421784 # Average percentage of cache occupancy
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system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy
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system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses
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env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
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input=cin
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=92
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prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
All Rights Reserved
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:25
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:02
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 21799 # Simulator instruction rate (inst/s)
-host_mem_usage 200132 # Number of bytes of host memory used
-host_seconds 20.14 # Real time elapsed on the host
-host_tick_rate 10950015 # Simulator tick rate (ticks/s)
+host_inst_rate 38759 # Simulator instruction rate (inst/s)
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+host_seconds 11.32 # Real time elapsed on the host
+host_tick_rate 19469095 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 438923 # Number of instructions simulated
sim_seconds 0.000220 # Number of seconds simulated
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.overall_accesses 40537 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 20113.149847 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.overall_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
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system.cpu1.dcache.overall_avg_miss_latency 20280.063291 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency
system.cpu1.icache.fast_writes 0 # number of fast writes performed
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latency=1000
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env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
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All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:58
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:16
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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-host_seconds 0.40 # Real time elapsed on the host
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+host_inst_rate 1722968 # Simulator instruction rate (inst/s)
+host_mem_usage 1115976 # Number of bytes of host memory used
+host_seconds 0.39 # Real time elapsed on the host
+host_tick_rate 222951866 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 677340 # Number of instructions simulated
sim_seconds 0.000088 # Number of seconds simulated
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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latency=1000
max_miss_count=0
mshrs=4
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env=
errout=cerr
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All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:59
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:17
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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+host_inst_rate 920855 # Simulator instruction rate (inst/s)
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+host_seconds 0.71 # Real time elapsed on the host
+host_tick_rate 372636983 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 650423 # Number of instructions simulated
sim_seconds 0.000263 # Number of seconds simulated
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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latency=1000
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All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:17:27
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:22:18
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
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-host_seconds 137.46 # Real time elapsed on the host
-host_tick_rate 1956295 # Simulator tick rate (ticks/s)
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+host_seconds 287.16 # Real time elapsed on the host
+host_tick_rate 936456 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_seconds 0.000269 # Number of seconds simulated
sim_ticks 268915439 # Number of ticks simulated
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
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system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses
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system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses
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+system.l2c.ReadReq_mshr_miss_rate::6 2.732399 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::7 2.737970 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 21.810119 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0 2273 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 2288 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2 2314 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3 2311 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::4 2383 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::5 2289 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::6 2257 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::7 2313 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 18428 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 226995.596128 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 225507.425699 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 222973.634399 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3 223263.085244 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::4 216517.410827 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::5 225408.907820 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::6 228604.780682 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::7 223070.034587 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 1792340.875388 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::4 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::5 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::6 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::7 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 8 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 2273 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 2288 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2 2314 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3 2311 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::4 2383 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::5 2289 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::6 2257 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::7 2313 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 18428 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 8.087549 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 8.034528 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 7.944252 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3 7.954565 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::4 7.714226 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::5 8.031018 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::6 8.144883 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::7 7.947687 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 63.858708 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 86929 # number of Writeback hits
+system.l2c.Writeback_accesses::0 86929 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 86929 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 86929 # number of Writeback hits
+system.l2c.Writeback_hits::total 86929 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs 7154.090909 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 2.005630 # Average number of references to valid blocks.
system.l2c.blocked_cycles::no_mshrs 78695 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 213064 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency
+system.l2c.demand_accesses::0 26724 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 26611 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 26527 # number of demand (read+write) accesses
+system.l2c.demand_accesses::3 26761 # number of demand (read+write) accesses
+system.l2c.demand_accesses::4 26621 # number of demand (read+write) accesses
+system.l2c.demand_accesses::5 26631 # number of demand (read+write) accesses
+system.l2c.demand_accesses::6 26586 # number of demand (read+write) accesses
+system.l2c.demand_accesses::7 26603 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 213064 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 398767.217784 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 397036.815997 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 397371.390355 # average overall miss latency
+system.l2c.demand_avg_miss_latency::3 397062.532483 # average overall miss latency
+system.l2c.demand_avg_miss_latency::4 400617.464318 # average overall miss latency
+system.l2c.demand_avg_miss_latency::5 401667.438016 # average overall miss latency
+system.l2c.demand_avg_miss_latency::6 396087.642243 # average overall miss latency
+system.l2c.demand_avg_miss_latency::7 397088.252300 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3185698.753496 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
-system.l2c.demand_hits 89906 # number of demand (read+write) hits
+system.l2c.demand_hits::0 11351 # number of demand (read+write) hits
+system.l2c.demand_hits::1 11171 # number of demand (read+write) hits
+system.l2c.demand_hits::2 11100 # number of demand (read+write) hits
+system.l2c.demand_hits::3 11322 # number of demand (read+write) hits
+system.l2c.demand_hits::4 11319 # number of demand (read+write) hits
+system.l2c.demand_hits::5 11369 # number of demand (read+write) hits
+system.l2c.demand_hits::6 11109 # number of demand (read+write) hits
+system.l2c.demand_hits::7 11165 # number of demand (read+write) hits
+system.l2c.demand_hits::total 89906 # number of demand (read+write) hits
system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses
-system.l2c.demand_misses 123158 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.575251 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.580211 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 0.581558 # miss rate for demand accesses
+system.l2c.demand_miss_rate::3 0.576922 # miss rate for demand accesses
+system.l2c.demand_miss_rate::4 0.574809 # miss rate for demand accesses
+system.l2c.demand_miss_rate::5 0.573092 # miss rate for demand accesses
+system.l2c.demand_miss_rate::6 0.582148 # miss rate for demand accesses
+system.l2c.demand_miss_rate::7 0.580310 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 4.624302 # miss rate for demand accesses
+system.l2c.demand_misses::0 15373 # number of demand (read+write) misses
+system.l2c.demand_misses::1 15440 # number of demand (read+write) misses
+system.l2c.demand_misses::2 15427 # number of demand (read+write) misses
+system.l2c.demand_misses::3 15439 # number of demand (read+write) misses
+system.l2c.demand_misses::4 15302 # number of demand (read+write) misses
+system.l2c.demand_misses::5 15262 # number of demand (read+write) misses
+system.l2c.demand_misses::6 15477 # number of demand (read+write) misses
+system.l2c.demand_misses::7 15438 # number of demand (read+write) misses
+system.l2c.demand_misses::total 123158 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0 4.548533 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 4.567848 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 4.582312 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3 4.542244 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::4 4.566132 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::5 4.564417 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::6 4.572143 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::7 4.569222 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 36.512852 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 213064 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency
+system.l2c.occ_%::0 0.025896 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.025716 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.025892 # Average percentage of cache occupancy
+system.l2c.occ_%::3 0.026232 # Average percentage of cache occupancy
+system.l2c.occ_%::4 0.025792 # Average percentage of cache occupancy
+system.l2c.occ_%::5 0.026195 # Average percentage of cache occupancy
+system.l2c.occ_%::6 0.026471 # Average percentage of cache occupancy
+system.l2c.occ_%::7 0.026663 # Average percentage of cache occupancy
+system.l2c.occ_%::8 0.410030 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 26.517416 # Average occupied blocks per context
+system.l2c.occ_blocks::1 26.332816 # Average occupied blocks per context
+system.l2c.occ_blocks::2 26.512954 # Average occupied blocks per context
+system.l2c.occ_blocks::3 26.861209 # Average occupied blocks per context
+system.l2c.occ_blocks::4 26.410697 # Average occupied blocks per context
+system.l2c.occ_blocks::5 26.823356 # Average occupied blocks per context
+system.l2c.occ_blocks::6 27.106140 # Average occupied blocks per context
+system.l2c.occ_blocks::7 27.302482 # Average occupied blocks per context
+system.l2c.occ_blocks::8 419.870758 # Average occupied blocks per context
+system.l2c.overall_accesses::0 26724 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 26611 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 26527 # number of overall (read+write) accesses
+system.l2c.overall_accesses::3 26761 # number of overall (read+write) accesses
+system.l2c.overall_accesses::4 26621 # number of overall (read+write) accesses
+system.l2c.overall_accesses::5 26631 # number of overall (read+write) accesses
+system.l2c.overall_accesses::6 26586 # number of overall (read+write) accesses
+system.l2c.overall_accesses::7 26603 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 213064 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 398767.217784 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 397036.815997 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 397371.390355 # average overall miss latency
+system.l2c.overall_avg_miss_latency::3 397062.532483 # average overall miss latency
+system.l2c.overall_avg_miss_latency::4 400617.464318 # average overall miss latency
+system.l2c.overall_avg_miss_latency::5 401667.438016 # average overall miss latency
+system.l2c.overall_avg_miss_latency::6 396087.642243 # average overall miss latency
+system.l2c.overall_avg_miss_latency::7 397088.252300 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3185698.753496 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 89906 # number of overall hits
+system.l2c.overall_hits::0 11351 # number of overall hits
+system.l2c.overall_hits::1 11171 # number of overall hits
+system.l2c.overall_hits::2 11100 # number of overall hits
+system.l2c.overall_hits::3 11322 # number of overall hits
+system.l2c.overall_hits::4 11319 # number of overall hits
+system.l2c.overall_hits::5 11369 # number of overall hits
+system.l2c.overall_hits::6 11109 # number of overall hits
+system.l2c.overall_hits::7 11165 # number of overall hits
+system.l2c.overall_hits::total 89906 # number of overall hits
system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses
-system.l2c.overall_misses 123158 # number of overall misses
+system.l2c.overall_miss_rate::0 0.575251 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.580211 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 0.581558 # miss rate for overall accesses
+system.l2c.overall_miss_rate::3 0.576922 # miss rate for overall accesses
+system.l2c.overall_miss_rate::4 0.574809 # miss rate for overall accesses
+system.l2c.overall_miss_rate::5 0.573092 # miss rate for overall accesses
+system.l2c.overall_miss_rate::6 0.582148 # miss rate for overall accesses
+system.l2c.overall_miss_rate::7 0.580310 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 4.624302 # miss rate for overall accesses
+system.l2c.overall_misses::0 15373 # number of overall misses
+system.l2c.overall_misses::1 15440 # number of overall misses
+system.l2c.overall_misses::2 15427 # number of overall misses
+system.l2c.overall_misses::3 15439 # number of overall misses
+system.l2c.overall_misses::4 15302 # number of overall misses
+system.l2c.overall_misses::5 15262 # number of overall misses
+system.l2c.overall_misses::6 15477 # number of overall misses
+system.l2c.overall_misses::7 15438 # number of overall misses
+system.l2c.overall_misses::total 123158 # number of overall misses
system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0 4.548533 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 4.567848 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 4.582312 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3 4.542244 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::4 4.566132 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::5 4.564417 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::6 4.572143 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::7 4.569222 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 36.512852 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
boot_cpu_frequency=1
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=atomic
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=drivesys.physmem
-readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS
+readfile=/proj/aatl_perfmod_arch/users/lihsu/m5/m5/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
[drivesys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[drivesys.disk2]
[drivesys.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[drivesys.intrctrl]
[drivesys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[drivesys.terminal]
children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
boot_cpu_frequency=1
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
mem_mode=atomic
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=testsys.physmem
-readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS
+readfile=/proj/aatl_perfmod_arch/users/lihsu/m5/m5/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
[testsys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[testsys.disk2]
[testsys.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[testsys.intrctrl]
[testsys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[testsys.terminal]
All Rights Reserved
-M5 compiled Jul 6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:10:47
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:12
+M5 executing on SC2B0619
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 4300236804024 because checkpoint
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
drivesys.cpu.dtb.write_hits 230735 # DTB write hits
drivesys.cpu.dtb.write_misses 82 # DTB write misses
-drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles
+drivesys.cpu.idle_fraction 0.999990 # Percentage of idle cycles
drivesys.cpu.itb.data_accesses 0 # DTB accesses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_hits 0 # DTB hits
drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed
drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
-drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles
+drivesys.cpu.not_idle_fraction 0.000010 # Percentage of non-idle cycles
drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated
drivesys.cpu.num_insts 1958129 # Number of instructions executed
drivesys.cpu.num_refs 626223 # Number of memory references
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-host_inst_rate 214917322 # Simulator instruction rate (inst/s)
-host_mem_usage 463572 # Number of bytes of host memory used
-host_seconds 1.27 # Real time elapsed on the host
-host_tick_rate 157210213175 # Simulator tick rate (ticks/s)
+host_inst_rate 70382622 # Simulator instruction rate (inst/s)
+host_mem_usage 464660 # Number of bytes of host memory used
+host_seconds 3.88 # Real time elapsed on the host
+host_tick_rate 51489346502 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273374833 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_hits 504853 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
-testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles
+testsys.cpu.idle_fraction 0.999982 # Percentage of idle cycles
testsys.cpu.itb.data_accesses 0 # DTB accesses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_hits 0 # DTB hits
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
-testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles
+testsys.cpu.not_idle_fraction 0.000018 # Percentage of non-idle cycles
testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated
testsys.cpu.num_insts 3560411 # Number of instructions executed
testsys.cpu.num_refs 1173571 # Number of memory references
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-host_inst_rate 134733776737 # Simulator instruction rate (inst/s)
-host_mem_usage 463572 # Number of bytes of host memory used
+host_inst_rate 166997454490 # Simulator instruction rate (inst/s)
+host_mem_usage 464660 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 366594216 # Simulator tick rate (ticks/s)
+host_tick_rate 453274510 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273374833 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
projects / gem5.git / commitdiff