arm: Fix system register fpcxt_ns and fpcxt_s naming convention.
authorSrinath Parvathaneni <srinath.parvathaneni@arm.com>
Thu, 19 May 2022 15:51:10 +0000 (16:51 +0100)
committerSrinath Parvathaneni <srinath.parvathaneni@arm.com>
Thu, 19 May 2022 15:51:21 +0000 (16:51 +0100)
The current assembler accepts system registers FPCXTNS and FPCXTS for Armv8.1-M
Mainline Instructions VSTR, VLDR, VMRS and VMSR.
Assembler should be also allowing FPCXT_NS, fpcxt_ns, fpcxtns, FPCXT_S, fpcxt_s
and fpcxts. This patch fixes the issue.

gas/config/tc-arm.c
gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.d [new file with mode: 0644]
gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.s [new file with mode: 0644]

index 8873269d76a482352c69d2d40a248549e7d6ba90..538d83f546276b8c55d872cba1a50ff01ed0555b 100644 (file)
@@ -6565,7 +6565,13 @@ parse_sys_vldr_vstr (char **str)
     {"VPR",            0x4, 0x1},
     {"P0",             0x5, 0x1},
     {"FPCXTNS",                0x6, 0x1},
-    {"FPCXTS",         0x7, 0x1}
+    {"FPCXT_NS",       0x6, 0x1},
+    {"fpcxtns",                0x6, 0x1},
+    {"fpcxt_ns",       0x6, 0x1},
+    {"FPCXTS",         0x7, 0x1},
+    {"FPCXT_S",                0x7, 0x1},
+    {"fpcxts",         0x7, 0x1},
+    {"fpcxt_s",                0x7, 0x1}
   };
   char *op_end = strchr (*str, ',');
   size_t op_strlen = op_end - *str;
@@ -10161,8 +10167,8 @@ do_vmrs (void)
                  _(BAD_FPU));
       break;
 
-    case 14: /* fpcxt_ns.  */
-    case 15: /* fpcxt_s.  */
+    case 14: /* fpcxt_ns, fpcxtns, FPCXT_NS, FPCXTNS.  */
+    case 15: /* fpcxt_s, fpcxts, FPCXT_S, FPCXTS.  */
       constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
                  _("selected processor does not support instruction"));
       break;
@@ -23991,6 +23997,8 @@ static const struct reg_entry reg_names[] =
   REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
   REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
   REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
+  REGDEF(fpcxtns,14,VFC), REGDEF(FPCXTNS,14,VFC),
+  REGDEF(fpcxts,15,VFC), REGDEF(FPCXTS,15,VFC),
 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.d b/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.d
new file mode 100644 (file)
index 0000000..a25bc45
--- /dev/null
@@ -0,0 +1,40 @@
+#name: Valid Armv8.1-M Mainline FPCXT_NS and FPCXT_S register usage
+#source: armv8_1-m-fpcxt-reg.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^*]+> ed6d cf81       vstr    FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81       vstr    FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81       vstr    FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81       vstr    FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81       vstr    FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81       vstr    FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81       vstr    FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81       vstr    FPCXTS, \[sp, #-4\]!
+0+.* <[^>]*> edd3 cf80         vldr    FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80         vldr    FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80         vldr    FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80         vldr    FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 ef80         vldr    FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80         vldr    FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80         vldr    FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80         vldr    FPCXTS, \[r3\]
+[^*]+> eefe 4a10       vmrs    r4, fpcxt_ns
+[^*]+> eefe 4a10       vmrs    r4, fpcxt_ns
+[^*]+> eeff 5a10       vmrs    r5, fpcxt_s
+[^*]+> eeff 5a10       vmrs    r5, fpcxt_s
+[^*]+> eefe 4a10       vmrs    r4, fpcxt_ns
+[^*]+> eefe 4a10       vmrs    r4, fpcxt_ns
+[^*]+> eeff 5a10       vmrs    r5, fpcxt_s
+[^*]+> eeff 5a10       vmrs    r5, fpcxt_s
+[^*]+> eeee 4a10       vmsr    fpcxt_ns, r4
+[^*]+> eeee 4a10       vmsr    fpcxt_ns, r4
+[^*]+> eeef 5a10       vmsr    fpcxt_s, r5
+[^*]+> eeef 5a10       vmsr    fpcxt_s, r5
+[^*]+> eeee 4a10       vmsr    fpcxt_ns, r4
+[^*]+> eeee 4a10       vmsr    fpcxt_ns, r4
+[^*]+> eeef 5a10       vmsr    fpcxt_s, r5
+[^*]+> eeef 5a10       vmsr    fpcxt_s, r5
diff --git a/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.s b/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.s
new file mode 100644 (file)
index 0000000..6863c32
--- /dev/null
@@ -0,0 +1,37 @@
+       .syntax unified
+func:
+       vstr fpcxtns,[sp,#-4]!
+       vstr fpcxts,[sp,#-4]!
+       vstr FPCXTNS,[sp,#-4]!
+       vstr FPCXTS,[sp,#-4]!
+       vstr fpcxt_ns,[sp,#-4]!
+       vstr fpcxt_s,[sp,#-4]!
+       vstr FPCXT_NS,[sp,#-4]!
+       vstr FPCXT_S,[sp,#-4]!
+
+       vldr FPCXTNS, [r3]
+       vldr FPCXT_NS, [r3]
+       vldr fpcxtns, [r3]
+       vldr fpcxt_ns, [r3]
+       vldr FPCXTS, [r3]
+       vldr FPCXT_S, [r3]
+       vldr fpcxt_s, [r3]
+       vldr fpcxts, [r3]
+
+       vmrs r4, FPCXT_NS
+       vmrs r4, FPCXTNS
+       vmrs r5, FPCXTS
+       vmrs r5, FPCXT_S
+       vmrs r4, fpcxt_ns
+       vmrs r4, fpcxtns
+       vmrs r5, fpcxts
+       vmrs r5, fpcxt_s
+
+       vmsr FPCXT_NS, r4
+       vmsr FPCXTNS, r4
+       vmsr FPCXTS, r5
+       vmsr FPCXT_S, r5
+       vmsr fpcxt_ns, r4
+       vmsr fpcxtns, r4
+       vmsr fpcxts, r5
+       vmsr fpcxt_s, r5