{"VPR", 0x4, 0x1},
{"P0", 0x5, 0x1},
{"FPCXTNS", 0x6, 0x1},
- {"FPCXTS", 0x7, 0x1}
+ {"FPCXT_NS", 0x6, 0x1},
+ {"fpcxtns", 0x6, 0x1},
+ {"fpcxt_ns", 0x6, 0x1},
+ {"FPCXTS", 0x7, 0x1},
+ {"FPCXT_S", 0x7, 0x1},
+ {"fpcxts", 0x7, 0x1},
+ {"fpcxt_s", 0x7, 0x1}
};
char *op_end = strchr (*str, ',');
size_t op_strlen = op_end - *str;
_(BAD_FPU));
break;
- case 14: /* fpcxt_ns. */
- case 15: /* fpcxt_s. */
+ case 14: /* fpcxt_ns, fpcxtns, FPCXT_NS, FPCXTNS. */
+ case 15: /* fpcxt_s, fpcxts, FPCXT_S, FPCXTS. */
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
_("selected processor does not support instruction"));
break;
REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
+ REGDEF(fpcxtns,14,VFC), REGDEF(FPCXTNS,14,VFC),
+ REGDEF(fpcxts,15,VFC), REGDEF(FPCXTS,15,VFC),
/* Maverick DSP coprocessor registers. */
REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
--- /dev/null
+#name: Valid Armv8.1-M Mainline FPCXT_NS and FPCXT_S register usage
+#source: armv8_1-m-fpcxt-reg.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^*]+> ed6d cf81 vstr FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 vstr FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81 vstr FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 vstr FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81 vstr FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 vstr FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81 vstr FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 vstr FPCXTS, \[sp, #-4\]!
+0+.* <[^>]*> edd3 cf80 vldr FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80 vldr FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80 vldr FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80 vldr FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 ef80 vldr FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80 vldr FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80 vldr FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80 vldr FPCXTS, \[r3\]
+[^*]+> eefe 4a10 vmrs r4, fpcxt_ns
+[^*]+> eefe 4a10 vmrs r4, fpcxt_ns
+[^*]+> eeff 5a10 vmrs r5, fpcxt_s
+[^*]+> eeff 5a10 vmrs r5, fpcxt_s
+[^*]+> eefe 4a10 vmrs r4, fpcxt_ns
+[^*]+> eefe 4a10 vmrs r4, fpcxt_ns
+[^*]+> eeff 5a10 vmrs r5, fpcxt_s
+[^*]+> eeff 5a10 vmrs r5, fpcxt_s
+[^*]+> eeee 4a10 vmsr fpcxt_ns, r4
+[^*]+> eeee 4a10 vmsr fpcxt_ns, r4
+[^*]+> eeef 5a10 vmsr fpcxt_s, r5
+[^*]+> eeef 5a10 vmsr fpcxt_s, r5
+[^*]+> eeee 4a10 vmsr fpcxt_ns, r4
+[^*]+> eeee 4a10 vmsr fpcxt_ns, r4
+[^*]+> eeef 5a10 vmsr fpcxt_s, r5
+[^*]+> eeef 5a10 vmsr fpcxt_s, r5