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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index fa4ccd2d93b550f2ed3e00b270e9f26827e20852..11e6b8b621d331a92840250562e668323d10204f 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -17,10 +17,15 @@ task?
 Hints as to the answer emerge from an article
 "[SIMD considered harmful](https://www.sigarch.org/simd-instructions-considered-harmful/)"
 which illustrates a catastrophic rabbit-hole taken by Industry Giants
-since the 90s (over 3 decades) whereby SIMD width, an Order(N^6) opcode
+ARM, Intel, AMD,
+since the 90s (over 3 decades) whereby SIMD, an Order(N^6) opcode
 proliferation nightmare, with its mantra "make it easy for hardware engineers,
 let software sort out the mess" literally overwhelming programmers.
 Worse than that, specialists in charging clients Optimisation Services
 are finding that AVX-512, to take an example, is anything but optimal:
 overall performance actually *decreases* even as power consumption goes
 up.
+
+Cray-style Vectors solved, over thirty years ago, the opcode proliferation
+nightmare.  Only the NEC SX Aurora however truly kept the Cray Vector flame
+alive, until RISC-V RVV and now SVP64 and recently MRISC32 joined it.