const char *
MiscRegFile::CP0Event::description()
{
- return "Coprocessor-0 event";
+ return "Coprocessor-0";
}
void
const char *
CPUProgressEvent::description()
{
- return "CPU Progress event";
+ return "CPU Progress";
}
#if FULL_SYSTEM
const char *
DefaultCommit<Impl>::TrapEvent::description()
{
- return "Trap event";
+ return "Trap";
}
template <class Impl>
const char *
FullO3CPU<Impl>::TickEvent::description()
{
- return "FullO3CPU tick event";
+ return "FullO3CPU tick";
}
template <class Impl>
const char *
FullO3CPU<Impl>::ActivateThreadEvent::description()
{
- return "FullO3CPU \"Activate Thread\" event";
+ return "FullO3CPU \"Activate Thread\"";
}
template <class Impl>
const char *
FullO3CPU<Impl>::DeallocateContextEvent::description()
{
- return "FullO3CPU \"Deallocate Context\" event";
+ return "FullO3CPU \"Deallocate Context\"";
}
template <class Impl>
const char *
InstructionQueue<Impl>::FUCompletion::description()
{
- return "Functional unit completion event";
+ return "Functional unit completion";
}
template <class Impl>
const char *
LSQUnit<Impl>::WritebackEvent::description()
{
- return "Store writeback event";
+ return "Store writeback";
}
template<class Impl>
const char *
BackEnd<Impl>::LdWritebackEvent::description()
{
- return "Load writeback event";
+ return "Load writeback";
}
const char *
BackEnd<Impl>::DCacheCompletionEvent::description()
{
- return "Cache completion event";
+ return "Cache completion";
}
template <class Impl>
const char *
OzoneCPU<Impl>::TickEvent::description()
{
- return "OzoneCPU tick event";
+ return "OzoneCPU tick";
}
template <class Impl>
const char *
InorderBackEnd<Impl>::DCacheCompletionEvent::description()
{
- return "DCache completion event";
+ return "DCache completion";
}
const char *
InstQueue<Impl>::FUCompletion::description()
{
- return "Functional unit completion event";
+ return "Functional unit completion";
}
#endif
template <class Impl>
const char *
OzoneLSQ<Impl>::StoreCompletionEvent::description()
{
- return "LSQ store completion event";
+ return "LSQ store completion";
}
template <class Impl>
const char *
LWBackEnd<Impl>::TrapEvent::description()
{
- return "Trap event";
+ return "Trap";
}
template <class Impl>
const char *
OzoneLWLSQ<Impl>::WritebackEvent::description()
{
- return "Store writeback event";
+ return "Store writeback";
}
template <class Impl>
const char*
EndQuiesceEvent::description()
{
- return "End Quiesce Event.";
+ return "End Quiesce";
}
const char *
AtomicSimpleCPU::TickEvent::description()
{
- return "AtomicSimpleCPU tick event";
+ return "AtomicSimpleCPU tick";
}
Port *
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() { return "Timing CPU tick"; }
void schedule(PacketPtr _pkt, Tick t);
};
ITickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() { return "Timing CPU icache tick"; }
};
ITickEvent tickEvent;
DTickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() { return "Timing CPU dcache tick"; }
};
DTickEvent tickEvent;
const char *
OptCPU::TickEvent::description()
{
- return "OptCPU tick event";
+ return "OptCPU tick";
}
const char *
TraceCPU::TickEvent::description()
{
- return "TraceCPU tick event";
+ return "TraceCPU tick";
}
TxEvent(EtherTap *_tap)
: Event(&mainEventQueue), tap(_tap) {}
void process() { tap->retransmit(); }
- virtual const char *description() { return "retransmit event"; }
+ virtual const char *description() { return "EtherTap retransmit"; }
};
friend class TxEvent;
const char *
Uart8250::IntrEvent::description()
{
- return "uart interrupt delay event";
+ return "uart interrupt delay";
}
void
virtual void process() { port->trySend(); }
- virtual const char *description() { return "bridge send event"; }
+ virtual const char *description() { return "bridge send"; }
};
SendEvent sendEvent;