S/390: Sync with IBM z14 POP - SI_RD format

The recent POP adjusted a few of the instruction formats.  This patch
adjusts our optable accordingly.  No user visible change - hopefully.

opcodes/ChangeLog:

2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>

	* s390-opc.c (INSTR_SI_RD): New macro.
	(INSTR_S_RD): Adjust example instruction.
	* s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
	SI_RD.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c90f097503ac0d662d72e0b6138501b508b1626b..cde21effd0e75bf5e0477436e10dbbc0b9fab6d0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
+
+       * s390-opc.c (INSTR_SI_RD): New macro.
+       (INSTR_S_RD): Adjust example instruction.
+       * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
+       SI_RD.
+
 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 
        * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,

diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 6d4f91ae398a866d3e72dc52f11531c882d141a8..a1e761cdf9a09363055e36040820d7514f04eb38 100644 (file)
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -436,6 +436,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RX_RRRD      4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
 #define INSTR_RX_RERRD     4, { RE_8,D_20,X_12,B_16,0,0 }        /* e.g. d     */
 #define INSTR_RX_URRD      4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
+#define INSTR_SI_RD        4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
 #define INSTR_SI_URD       4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
 #define INSTR_SIY_URD      6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
 #define INSTR_SIY_IRD      6, { D20_20,B_16,I8_8,0,0,0 }         /* e.g. asi   */
@@ -453,7 +454,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_SSF_RRDRD    6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
 #define INSTR_SSF_RERDRD2  6, { RE_8,D_20,B_16,D_36,B_32,0 }     /* e.g. lpd   */
 #define INSTR_S_00         4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
-#define INSTR_S_RD         4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
+#define INSTR_S_RD         4, { D_20,B_16,0,0,0,0 }              /* e.g. stck  */
 #define INSTR_VRV_VVXRDU   6, { V_8,D_20,VX_12,B_16,U4_32,0 }    /* e.g. vgef  */
 #define INSTR_VRI_V0U      6, { V_8,U16_16,0,0,0,0 }             /* e.g. vgbm  */
 #define INSTR_VRI_V        6, { V_8,0,0,0,0,0 }                  /* e.g. vzero */
@@ -654,6 +655,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RX_RRRD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_RERRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_URRD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SI_RD        { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SI_URD       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SIY_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_SIY_IRD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 535d6c9b3f3950bd595d9f39f718e9fe3e747ba3..67683b1e55ac16f8af638af8a15dd2ce08fbff8b 100644 (file)
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -103,7 +103,7 @@ b7 lctl RS_CCRD "load control" g5 esa,zarch
 20 lpdr RR_FF "load positive (long)" g5 esa,zarch
 30 lper RR_FF "load positive (short)" g5 esa,zarch
 10 lpr RR_RR "load positive" g5 esa,zarch
-82 lpsw S_RD "load PSW" g5 esa,zarch
+82 lpsw SI_RD "load PSW" g5 esa,zarch
 18 lr RR_RR "load" g5 esa,zarch
 b1 lra RX_RRRD "load real address" g5 esa,zarch
 25 ldxr RR_FFE "load rounded (ext. to long)" g5 esa,zarch
@@ -199,7 +199,7 @@ b25e srst RRE_RR "search string" g5 esa,zarch
 b225 ssar RRE_R0 "set secondary ASN" g5 esa,zarch
 b233 ssch S_RD "start subchannel" g5 esa,zarch
 b22b sske RRE_RR "set storage key extended" g5 esa,zarch
-80 ssm S_RD "set system mask" g5 esa,zarch
+80 ssm SI_RD "set system mask" g5 esa,zarch
 50 st RX_RRRD "store" g5 esa,zarch
 9b stam RS_AARD "store access multiple" g5 esa,zarch
 b212 stap S_RD "store CPU address" g5 esa,zarch
@@ -235,7 +235,7 @@ e501 tprot SSE_RDRD "test protection" g5 esa,zarch
 dc tr SS_L0RDRD "translate" g5 esa,zarch
 99 trace RS_RRRD "trace" g5 esa,zarch
 dd trt SS_L0RDRD "translate and test" g5 esa,zarch
-93 ts S_RD "test and set" g5 esa,zarch
+93 ts SI_RD "test and set" g5 esa,zarch
 b235 tsch S_RD "test subchannel" g5 esa,zarch
 f3 unpk SS_LLRDRD "unpack" g5 esa,zarch
 0102 upt E "update tree" g5 esa,zarch