fhdl.ir: add tests for port propagation.

diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py
index 6770b12a60ee192d6a0592a8ab7357e504a404de..2c410e2225ad67739e73e172f272ceb63eb0b468 100644 (file)
--- a/nmigen/fhdl/ir.py
+++ b/nmigen/fhdl/ir.py
@@ -50,7 +50,7 @@ class Fragment:
         assert isinstance(subfragment, Fragment)
         self.subfragments.append((subfragment, name))
 
-    def _propagate_ports(self, ports, clock_domains):
+    def _propagate_ports(self, ports, clock_domains={}):
         # Collect all signals we're driving (on LHS of statements), and signals we're using
         # (on RHS of statements, or in clock domains).
         self_driven = union(s._lhs_signals() for s in self.statements)

diff --git a/nmigen/test/test_fhdl_dsl.py b/nmigen/test/test_fhdl_dsl.py
index 5837caf2389daf7053d75aa2a42cef7fea4af45a..22019b1a028c003a109b60ad458d3d48cdf0bc68 100644 (file)
--- a/nmigen/test/test_fhdl_dsl.py
+++ b/nmigen/test/test_fhdl_dsl.py
@@ -11,7 +11,6 @@ class DSLTestCase(unittest.TestCase):
         self.s1 = Signal()
         self.s2 = Signal()
         self.s3 = Signal()
-        self.s4 = Signal()
         self.c1 = Signal()
         self.c2 = Signal()
         self.c3 = Signal()

diff --git a/nmigen/test/test_fhdl_ir.py b/nmigen/test/test_fhdl_ir.py
new file mode 100644 (file)
index 0000000..c59464c
--- /dev/null
+++ b/nmigen/test/test_fhdl_ir.py
@@ -0,0 +1,77 @@
+import unittest
+
+from nmigen.fhdl.ast import *
+from nmigen.fhdl.ir import *
+
+
+class FragmentPortsTestCase(unittest.TestCase):
+    def setUp(self):
+        self.s1 = Signal()
+        self.s2 = Signal()
+        self.s3 = Signal()
+        self.c1 = Signal()
+        self.c2 = Signal()
+        self.c3 = Signal()
+
+    def test_self_contained(self):
+        f = Fragment()
+        f.add_statements(
+            self.c1.eq(self.s1),
+            self.s1.eq(self.c1)
+        )
+        ins, outs = f._propagate_ports(ports=())
+        self.assertEqual(ins, ValueSet())
+        self.assertEqual(outs, ValueSet())
+        self.assertEqual(f.ports, ValueSet())
+
+    def test_infer_input(self):
+        f = Fragment()
+        f.add_statements(
+            self.c1.eq(self.s1)
+        )
+        ins, outs = f._propagate_ports(ports=())
+        self.assertEqual(ins, ValueSet((self.s1,)))
+        self.assertEqual(outs, ValueSet())
+        self.assertEqual(f.ports, ValueSet((self.s1,)))
+
+    def test_request_output(self):
+        f = Fragment()
+        f.add_statements(
+            self.c1.eq(self.s1)
+        )
+        ins, outs = f._propagate_ports(ports=(self.c1,))
+        self.assertEqual(ins, ValueSet((self.s1,)))
+        self.assertEqual(outs, ValueSet((self.c1,)))
+        self.assertEqual(f.ports, ValueSet((self.s1, self.c1)))
+
+    def test_input_in_subfragment(self):
+        f1 = Fragment()
+        f1.add_statements(
+            self.c1.eq(self.s1)
+        )
+        f2 = Fragment()
+        f2.add_statements(
+            self.s1.eq(0)
+        )
+        f1.add_subfragment(f2)
+        ins, outs = f1._propagate_ports(ports=())
+        self.assertEqual(ins, ValueSet())
+        self.assertEqual(outs, ValueSet())
+        self.assertEqual(f1.ports, ValueSet())
+        self.assertEqual(f2.ports, ValueSet((self.s1,)))
+
+    def test_output_from_subfragment(self):
+        f1 = Fragment()
+        f1.add_statements(
+            self.c1.eq(0)
+        )
+        f2 = Fragment()
+        f2.add_statements(
+            self.c2.eq(1)
+        )
+        f1.add_subfragment(f2)
+        ins, outs = f1._propagate_ports(ports=(self.c2,))
+        self.assertEqual(ins, ValueSet())
+        self.assertEqual(outs, ValueSet((self.c2,)))
+        self.assertEqual(f1.ports, ValueSet((self.c2,)))
+        self.assertEqual(f2.ports, ValueSet((self.c2,)))