[xcc, sim] eliminated zero-extended immediates

This is a big commit because it involved rewriting gcc's algorithm for
generating constants.

diff --git a/riscv/decode.h b/riscv/decode.h
index f99e9ebe30328ecdd3a0bbfe164bff7390d98dc3..125ba76280c8368b0782aabb2bf5668bbf25d300 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -78,7 +78,7 @@ const int JUMP_ALIGN_BITS = 1;
 // note: bit fields are in little-endian order
 struct itype_t
 {
-  unsigned imm12 : IMM_BITS;
+  signed imm12 : IMM_BITS;
   unsigned funct : FUNCT_BITS;
   unsigned rs1 : GPRID_BITS;
   unsigned rdi : GPRID_BITS;
@@ -139,8 +139,7 @@ union insn_t
 #define FRDR FR[insn.ftype.rdr]
 #define FRDI FR[insn.itype.rdi]
 #define BIGIMM insn.btype.bigimm
-#define IMM insn.itype.imm12
-#define SIMM ((int32_t)((uint32_t)insn.itype.imm12<<(32-IMM_BITS))>>(32-IMM_BITS))
+#define SIMM insn.itype.imm12
 #define SHAMT (insn.itype.imm12 & 0x3F)
 #define SHAMTW (insn.itype.imm12 & 0x1F)
 #define TARGET insn.jtype.target

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index ada6657d65e05b62f7576c1f3ccd2be012246ef9..2c90b8bd2844b439ed50c6efda23e39328609cc5 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RDI = IMM & RS1;
+RDI = SIMM & RS1;

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index d49c8c1ad0cbb29ff93c03160164207a0205112e..3ee429d00566fd6fc4fc4a0bb0869d419884e585 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RDI = IMM | RS1;
+RDI = SIMM | RS1;

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index fcf90429a264b3dce641961cab225aad2d96e9ad..039e1b72abbc1a73f7f809120b3503d485816444 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RDI = IMM ^ RS1;
+RDI = SIMM ^ RS1;