fixed parsing of constant with comment between size and value

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 37c3232aaa1c29e30874971a33802e49c3bb2b22..ce7b9927295d5c5b3b71647b319bec217e0ccfc5 100644 (file)
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -1140,6 +1140,13 @@ basic_expr:
                delete $1;
                delete $2;
        } |
+       TOK_CONST TOK_CONST {
+               $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
+               if ($$ == NULL || (*$2)[0] != '\'')
+                       log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
+               delete $1;
+               delete $2;
+       } |
        TOK_CONST {
                $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
                if ($$ == NULL)

diff --git a/tests/simple/macros.v b/tests/simple/macros.v
index cda46cb48d2d1dd089c197d5d25fba0b73da932d..a3e8d70f87e701312081391f43edd275d6e4a7b2 100644 (file)
--- a/tests/simple/macros.v
+++ b/tests/simple/macros.v
@@ -235,3 +235,10 @@ always @* begin
 end
 
 endmodule
+
+`define SIZE 4 // comment supported in this part
+module test ( din_a, dout_a );
+input [`SIZE-1:0] din_a;
+output [`SIZE-1:0] dout_a;
+assign dout_a = din_a | `SIZE'ha;
+endmodule