ecp5: Add LSRMODE to flipflops for PRLD support

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb189264396e4080e74eab398779583ea..ca5d020f38279854573110dbbbd52ba5c6908d02 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -203,13 +203,14 @@ endmodule
 
 // ---------------------------------------
 
-module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
        parameter GSR = "ENABLED";
        parameter [127:0] CEMUX = "1";
        parameter CLKMUX = "CLK";
        parameter LSRMUX = "LSR";
        parameter SRMODE = "LSR_OVER_CE";
        parameter REGSET = "RESET";
+       parameter [127:0] LSRMODE = "LSR";
 
        reg muxce;
        always @(*)
@@ -222,8 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 
        wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
        wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
-
-       localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+       generate
+               if (LSRMODE == "PRLD")
+                       wire srval = M;
+               else
+                       localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+       endgenerate
 
        initial Q = srval;
 
@@ -339,6 +344,8 @@ module TRELLIS_SLICE(
        parameter REG1_SD = "0";
        parameter REG0_REGSET = "RESET";
        parameter REG1_REGSET = "RESET";
+       parameter REG0_LSRMODE = "LSR";
+       parameter REG1_LSRMODE = "LSR";
        parameter [127:0] CCU2_INJECT1_0 = "NO";
        parameter [127:0] CCU2_INJECT1_1 = "NO";
        parameter WREMUX = "WRE";
@@ -428,10 +435,11 @@ module TRELLIS_SLICE(
                .CLKMUX(CLKMUX),
                .LSRMUX(LSRMUX),
                .SRMODE(SRMODE),
-               .REGSET(REG0_REGSET)
+               .REGSET(REG0_REGSET),
+               .LSRMODE(REG0_LSRMODE)
        ) ff_0 (
                .CLK(CLK), .LSR(LSR), .CE(CE),
-               .DI(muxdi0),
+               .DI(muxdi0), .M(M0),
                .Q(Q0)
        );
        TRELLIS_FF #(
@@ -440,10 +448,11 @@ module TRELLIS_SLICE(
                .CLKMUX(CLKMUX),
                .LSRMUX(LSRMUX),
                .SRMODE(SRMODE),
-               .REGSET(REG1_REGSET)
+               .REGSET(REG1_REGSET),
+               .LSRMODE(REG1_LSRMODE)
        ) ff_1 (
                .CLK(CLK), .LSR(LSR), .CE(CE),
-               .DI(muxdi1),
+               .DI(muxdi1), .M(M1),
                .Q(Q1)
        );
 endmodule