intel: Add IS_GT2 macro for recognizing Sandybridge GT2 systems.

Also, refactor IS_GEN6 to use the IS_GT1 and IS_GT2 macros.

diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index 4ff9140d56e1e2d0800fb6f9ebea778ac1f8f1d0..a3f40effc352c59950f8755c65cafa5349bcb3a0 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -125,18 +125,17 @@
 /* Compat macro for intel_decode.c */
 #define IS_IRONLAKE(devid)     IS_GEN5(devid)
 
-#define IS_GEN6(devid)         (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
-                                devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
-                                devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
-                                devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
-                                devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-                                devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
-                                devid == PCI_CHIP_SANDYBRIDGE_S)
-
 #define IS_GT1(devid)          (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
                                 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
                                 devid == PCI_CHIP_SANDYBRIDGE_S)
 
+#define IS_GT2(devid)          (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
+                                devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+                                devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+                                devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
+
+#define IS_GEN6(devid)         (IS_GT1(devid) || IS_GT2(devid))
+
 #define IS_965(devid)          (IS_GEN4(devid) || \
                                 IS_G4X(devid) || \
                                 IS_GEN5(devid) || \