Added logic-loop error handling to freduce

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 8a5301ec3d7ab433a3138fa7ccdba436f087c5dc..a60de4ee0195daba99a2175f79efdc5f011acd4e 100644 (file)
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -229,6 +229,7 @@ struct PerformReduction
        SigMap &sigmap;
        drivers_t &drivers;
        std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs;
+       pool<SigBit> recursion_guard;
 
        ezSatPtr ez;
        SatGen satgen;
@@ -246,6 +247,15 @@ struct PerformReduction
                if (sigdepth.count(out) != 0)
                        return sigdepth.at(out);
 
+               if (recursion_guard.count(out)) {
+                       string loop_signals;
+                       for (auto loop_bit : recursion_guard)
+                               loop_signals += string(" ") + log_signal(loop_bit);
+                       log_error("Found logic loop:%s\n", loop_signals.c_str());
+               }
+
+               recursion_guard.insert(out);
+
                if (drivers.count(out) != 0) {
                        std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
                        if (celldone.count(drv.first) == 0) {
@@ -264,6 +274,7 @@ struct PerformReduction
                        sigdepth[out] = 0;
                }
 
+               recursion_guard.erase(out);
                return sigdepth.at(out);
        }