```
move a 32/64-bit float from a FPR to a GPR, just copying bits of the
-IEEE 754 representation directly. This is equivalent to `stfs` followed
-by `lwz` or equivalent to `stfd` followed by `ld`. As `fmvtg` is just
+IEEE754 representation directly. This is equivalent to `stfs` followed
+by `lwz` or equivalent to `stfd` followed by `ld`. As `fmvtg` is just
copying bits, `FPSCR` is not affected in any way.
Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
result <- bfp64_CONVERT_FROM_BFP(rnd)
cls <- fprf_CLASS_BFP64(result)
-
if xx_flag = 1 then SetFX(FPSCR.XX)
-
FRT <- result
FPSCR.FPRF <- cls
FPSCR.FR <- inc_flag
Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit
float in FRT, following the usual 32-bit float in 64-bit float format.
-
If converting from a unsigned/signed 32-bit integer to a 64-bit float,
rounding is never necessary, so `FPSCR` is unmodified and exceptions are
never raised. Otherwise, `FPSCR` is modified and exceptions are raised
This conversion performs "saturation with NaN converted to minimum
valid integer". This is also exactly the same as the x86 ISA conversion
-semantics. OpenPOWER however has instructions for both:
+semantics. OpenPOWER however has instructions for both:
* rounding mode read from FPSCR
* rounding mode always set to truncate
`FPSCR` is modified and exceptions are raised as usual.
Both of these instructions have an Rc=1 mode which sets CR0 in the normal
-way for any instructions producing a GPR result. Additionally, when OE=1,
+way for any instructions producing a GPR result. Additionally, when OE=1,
if the numerical value of the FP number is not 100% accurately preserved
(due to truncation or saturation and including when the FP number was
NaN) then this is considered to be an integer Overflow condition, and
\newpage{}
-
----------
# Appendices