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diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
index 02feff5b21e1be932b080baa557ee7cbf7bca237..a574d0ebe2bea9b1684e8729a4791d944f661b13 100644 (file)
--- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn
+++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
@@ -46,6 +46,8 @@ A programmer can configure VCFG with any mix of these alternative configurations
 
 The above are pure subsets of valid RVV VCFG configurations (and hence forward compatible between RVP and RVV, whilst also keeping RVP simple).  Other useful element types are fixed point fraction types and small integer(4 bit to 7 bit) elements. However these are omitted for now as they aren’t currently part of RVV spec, and the intention of this proposal is to harmonise the Andes SIMD instructions into a subset of RVV.
 
+[[Comparative analysis Harmonised RVP vs Andes Packed SIMD ISA proposal]]
+
 # Comparative analysis with Andes Packed ISA proposal
 
 ## 16-bit Arithmetic