{
fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage));
- for (int i = 0; i < c->num_qpu_insts; i++) {
+ for (int i = 0; i < c->qpu_inst_count; i++) {
fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
vc4_qpu_disasm(&c->qpu_insts[i], 1);
fprintf(stderr, "\n");
}
}
+struct queued_qpu_inst {
+ struct simple_node link;
+ uint64_t inst;
+};
+
+static void
+queue(struct qcompile *c, uint64_t inst)
+{
+ struct queued_qpu_inst *q = calloc(1, sizeof(*q));
+ q->inst = inst;
+ insert_at_tail(&c->qpu_inst_list, &q->link);
+}
+
+static uint64_t *
+last_inst(struct qcompile *c)
+{
+ struct queued_qpu_inst *q =
+ (struct queued_qpu_inst *)last_elem(&c->qpu_inst_list);
+ return &q->inst;
+}
+
/**
* This is used to resolve the fact that we might register-allocate two
* different operands of an instruction to the same physical register file
* instruction, instead.
*/
static void
-fixup_raddr_conflict(uint64_t *insts, uint32_t *ni,
+fixup_raddr_conflict(struct qcompile *c,
struct qpu_reg src0, struct qpu_reg *src1)
{
if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) &&
(src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) &&
src0.addr != src1->addr) {
- insts[(*ni)++] = qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
+ qpu_m_NOP()));
*src1 = qpu_r3();
}
}
+static void
+serialize_one_inst(struct qcompile *c, uint64_t inst)
+{
+ if (c->qpu_inst_count >= c->qpu_inst_size) {
+ c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
+ c->qpu_insts = realloc(c->qpu_insts,
+ c->qpu_inst_size * sizeof(uint64_t));
+ }
+ c->qpu_insts[c->qpu_inst_count++] = inst;
+}
+
+static void
+serialize_insts(struct qcompile *c)
+{
+ int last_sfu_write = -10;
+
+ while (!is_empty_list(&c->qpu_inst_list)) {
+ struct queued_qpu_inst *q =
+ (struct queued_qpu_inst *)first_elem(&c->qpu_inst_list);
+ uint32_t last_waddr_a = QPU_W_NOP, last_waddr_b = QPU_W_NOP;
+ uint32_t raddr_a = QPU_GET_FIELD(q->inst, QPU_RADDR_A);
+ uint32_t raddr_b = QPU_GET_FIELD(q->inst, QPU_RADDR_B);
+
+ if (c->qpu_inst_count > 0) {
+ uint64_t last_inst = c->qpu_insts[c->qpu_inst_count -
+ 1];
+ uint32_t last_waddr_add = QPU_GET_FIELD(last_inst,
+ QPU_WADDR_ADD);
+ uint32_t last_waddr_mul = QPU_GET_FIELD(last_inst,
+ QPU_WADDR_MUL);
+
+ if (last_inst & QPU_WS) {
+ last_waddr_a = last_waddr_mul;
+ last_waddr_b = last_waddr_add;
+ } else {
+ last_waddr_a = last_waddr_add;
+ last_waddr_b = last_waddr_mul;
+ }
+ }
+
+ uint32_t src_muxes[] = {
+ QPU_GET_FIELD(q->inst, QPU_ADD_A),
+ QPU_GET_FIELD(q->inst, QPU_ADD_B),
+ QPU_GET_FIELD(q->inst, QPU_MUL_A),
+ QPU_GET_FIELD(q->inst, QPU_MUL_B),
+ };
+
+ /* "An instruction must not read from a location in physical
+ * regfile A or B that was written to by the previous
+ * instruction."
+ */
+ bool needs_raddr_vs_waddr_nop = false;
+ bool reads_r4 = false;
+ for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
+ if ((raddr_a < 32 &&
+ src_muxes[i] == QPU_MUX_A &&
+ last_waddr_a == raddr_a) ||
+ (raddr_b < 32 &&
+ src_muxes[i] == QPU_MUX_B &&
+ last_waddr_b == raddr_b)) {
+ needs_raddr_vs_waddr_nop = true;
+ }
+ if (src_muxes[i] == QPU_MUX_R4)
+ reads_r4 = true;
+ }
+
+ if (needs_raddr_vs_waddr_nop) {
+ serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
+ qpu_m_NOP()));
+ }
+
+ /* "After an SFU lookup instruction, accumulator r4 must not
+ * be read in the following two instructions. Any other
+ * instruction that results in r4 being written (that is, TMU
+ * read, TLB read, SFU lookup) cannot occur in the two
+ * instructions following an SFU lookup."
+ */
+ if (reads_r4) {
+ while (c->qpu_inst_count - last_sfu_write < 3) {
+ serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
+ qpu_m_NOP()));
+ }
+ }
+
+ uint32_t waddr_a = QPU_GET_FIELD(q->inst, QPU_WADDR_ADD);
+ uint32_t waddr_m = QPU_GET_FIELD(q->inst, QPU_WADDR_MUL);
+ if ((waddr_a >= QPU_W_SFU_RECIP && waddr_a <= QPU_W_SFU_LOG) ||
+ (waddr_m >= QPU_W_SFU_RECIP && waddr_m <= QPU_W_SFU_LOG)) {
+ last_sfu_write = c->qpu_inst_count;
+ }
+
+ serialize_one_inst(c, q->inst);
+
+ remove_from_list(&q->link);
+ free(q);
+ }
+}
+
void
vc4_generate_code(struct qcompile *c)
{
- uint64_t *insts = malloc(sizeof(uint64_t) * 1024); /* XXX: sizing */
- uint32_t ni = 0;
struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32];
bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
for (int i = 0; i < 32; i++)
allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i);
+ make_empty_list(&c->qpu_inst_list);
+
struct simple_node *node;
foreach(node, &c->instructions) {
struct qinst *qinst = (struct qinst *)node;
switch (c->stage) {
case QSTAGE_VERT:
case QSTAGE_COORD:
- insts[ni++] = qpu_load_imm_ui(qpu_vrsetup(), 0x00401a00);
- insts[ni++] = qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00);
+ queue(c, qpu_load_imm_ui(qpu_vrsetup(), 0x00401a00));
+ queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
break;
case QSTAGE_FRAG:
break;
/* Skip emitting the MOV if it's a no-op. */
if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B ||
dst.mux != src[0].mux || dst.addr != src[0].addr) {
- insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
+ qpu_m_NOP()));
}
break;
case QOP_SNE:
case QOP_SGE:
case QOP_SLT:
- fixup_raddr_conflict(insts, &ni, src[0], &src[1]);
- insts[ni++] = qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP),
- src[0], src[1]),
- qpu_m_NOP());
- insts[ni - 1] |= QPU_SF;
-
- insts[ni++] = qpu_load_imm_f(dst, 0.0);
- insts[ni++] = qpu_load_imm_f(dst, 1.0);
- insts[ni - 1] = ((insts[ni - 1] & ~QPU_COND_ADD_MASK)
+ fixup_raddr_conflict(c, src[0], &src[1]);
+ queue(c, qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP),
+ src[0], src[1]),
+ qpu_m_NOP()));
+ *last_inst(c) |= QPU_SF;
+
+ queue(c, qpu_load_imm_f(dst, 0.0));
+ queue(c, qpu_load_imm_f(dst, 1.0));
+ *last_inst(c) = ((*last_inst(c) & ~QPU_COND_ADD_MASK)
| QPU_SET_FIELD(compareflags[qinst->op - QOP_SEQ],
QPU_COND_ADD));
break;
case QOP_VPM_WRITE:
- insts[ni++] = qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM),
- src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0]),
+ qpu_m_NOP()));
break;
case QOP_VPM_READ:
- insts[ni++] = qpu_inst(qpu_a_MOV(dst,
- qpu_ra(QPU_R_VPM)),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(dst, qpu_ra(QPU_R_VPM)),
+ qpu_m_NOP()));
break;
case QOP_RCP:
case QOP_LOG2:
switch (qinst->op) {
case QOP_RCP:
- insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
- src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
+ src[0]),
+ qpu_m_NOP()));
break;
case QOP_RSQ:
- insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
- src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
+ src[0]),
+ qpu_m_NOP()));
break;
case QOP_EXP2:
- insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
- src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
+ src[0]),
+ qpu_m_NOP()));
break;
case QOP_LOG2:
- insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
- src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
+ src[0]),
+ qpu_m_NOP()));
break;
default:
abort();
}
- insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
- insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
-
- insts[ni++] = qpu_inst(qpu_a_MOV(dst, qpu_r4()),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
+ qpu_m_NOP()));
break;
case QOP_PACK_COLORS:
for (int i = 0; i < 4; i++) {
- insts[ni++] = qpu_inst(qpu_a_NOP(),
- qpu_m_MOV(qpu_r3(), src[i]));
- insts[ni - 1] |= QPU_PM;
- insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
+ queue(c, qpu_inst(qpu_a_NOP(),
+ qpu_m_MOV(qpu_r3(), src[i])));
+ *last_inst(c) |= QPU_PM;
+ *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
QPU_PACK);
}
- insts[ni++] = qpu_inst(qpu_a_MOV(dst, qpu_r3()),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r3()),
+ qpu_m_NOP()));
+
break;
case QOP_TLB_COLOR_WRITE:
- insts[ni++] = qpu_inst(qpu_a_MOV(qpu_tlbc(),
- src[0]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_MOV(qpu_tlbc(),
+ src[0]),
+ qpu_m_NOP()));
break;
case QOP_VARY_ADD_C:
- insts[ni++] = qpu_inst(qpu_a_FADD(dst,
- src[0], qpu_r5()),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_FADD(dst,
+ src[0], qpu_r5()),
+ qpu_m_NOP()));
break;
case QOP_PACK_SCALED:
- insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[0]),
- qpu_m_NOP());
- insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_A_16A, QPU_PACK);
+ queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
+ qpu_m_NOP()));
+ *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_A_16A,
+ QPU_PACK);
- insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[1]),
- qpu_m_NOP());
- insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_A_16B, QPU_PACK);
+ queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
+ qpu_m_NOP()));
+ *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_A_16B,
+ QPU_PACK);
break;
if (qir_get_op_nsrc(qinst->op) == 1)
src[1] = src[0];
- fixup_raddr_conflict(insts, &ni, src[0], &src[1]);
+ fixup_raddr_conflict(c, src[0], &src[1]);
if (translate[qinst->op].is_mul) {
- insts[ni++] = qpu_inst(qpu_a_NOP(),
- qpu_m_alu2(translate[qinst->op].op,
- dst, src[0], src[1]));
+ queue(c, qpu_inst(qpu_a_NOP(),
+ qpu_m_alu2(translate[qinst->op].op,
+ dst,
+ src[0], src[1])));
} else {
- insts[ni++] = qpu_inst(qpu_a_alu2(translate[qinst->op].op,
- dst, src[0], src[1]),
- qpu_m_NOP());
+ queue(c, qpu_inst(qpu_a_alu2(translate[qinst->op].op,
+ dst,
+ src[0], src[1]),
+ qpu_m_NOP()));
}
break;
}
-
- if ((dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B) &&
- dst.addr < 32)
- insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
}
+ serialize_insts(c);
+
/* thread end can't have VPM write */
- if (QPU_GET_FIELD(insts[ni - 1], QPU_WADDR_ADD) == QPU_W_VPM ||
- QPU_GET_FIELD(insts[ni - 1], QPU_WADDR_MUL) == QPU_W_VPM)
- insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
+ if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
+ QPU_WADDR_ADD) == QPU_W_VPM ||
+ QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
+ QPU_WADDR_MUL) == QPU_W_VPM) {
+ serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
+ }
- insts[ni - 1] = qpu_set_sig(insts[ni - 1], QPU_SIG_PROG_END);
- insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
- insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP());
+ c->qpu_insts[c->qpu_inst_count - 1] =
+ qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
+ QPU_SIG_PROG_END);
+ serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
+ serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
switch (c->stage) {
case QSTAGE_VERT:
case QSTAGE_COORD:
break;
case QSTAGE_FRAG:
- insts[2] = qpu_set_sig(insts[2], QPU_SIG_WAIT_FOR_SCOREBOARD);
- insts[ni - 1] = qpu_set_sig(insts[ni - 1],
- QPU_SIG_SCOREBOARD_UNLOCK);
+ c->qpu_insts[2] = qpu_set_sig(c->qpu_insts[2],
+ QPU_SIG_WAIT_FOR_SCOREBOARD);
+ c->qpu_insts[c->qpu_inst_count - 1] =
+ qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
+ QPU_SIG_SCOREBOARD_UNLOCK);
break;
}
- c->qpu_insts = insts;
- c->num_qpu_insts = ni;
-
if (vc4_debug & VC4_DEBUG_QPU)
vc4_dump_program(c);
- vc4_qpu_validate(insts, ni);
+ vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
}
-
projects / mesa.git / commitdiff