fastmodel: Implement readVecRegFlat for ArmThreadContext.

This just calls readVecReg after constructing a RegId.

Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
index 8a36ce3d34550ab54a3322f1257758139b24b002..c48ade817ca76c107dd6802c13b744cb019c4038 100644 (file)
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
@@ -201,6 +201,12 @@ ArmThreadContext::readVecReg(const RegId &reg_id) const
     return reg;
 }
 
+const ArmISA::VecRegContainer &
+ArmThreadContext::readVecRegFlat(RegIndex idx) const
+{
+    return readVecReg(RegId(VecRegClass, idx));
+}
+
 Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({
         { ArmISA::MISCREG_CPSR, "CPSR" },
         { ArmISA::MISCREG_SPSR, "SPSR" },

diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
index c7f26e3bd010b23bef0c58b1aeeeccd11483d8f9..8344f57b832ae3d650aee104841d51f175065aa0 100644 (file)
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
@@ -83,6 +83,7 @@ class ArmThreadContext : public Iris::ThreadContext
     }
 
     const VecRegContainer &readVecReg(const RegId &reg) const override;
+    const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
 };
 
 } // namespace Iris