BRIG Joined Alias(d)
fassume-phsa
-BRIG Report Var(flag_assume_phsa) Init(1) Optimization
+BRIG Var(flag_assume_phsa) Init(1) Optimization
Assume we are finalizing for phsa and its libhsail-rt. Enables additional
phsa-specific optimizations (default).
Recognize GNU-defined keywords.
fgnu-runtime
-ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)
+ObjC ObjC++ LTO RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)
Generate code for GNU runtime environment.
fgnu89-inline
C++ ObjC++ WarnRemoved
fkeep-inline-dllexport
-C C++ ObjC ObjC++ Var(flag_keep_inline_dllexport) Init(1) Report Condition(TARGET_DLLIMPORT_DECL_ATTRIBUTES)
+C C++ ObjC ObjC++ Var(flag_keep_inline_dllexport) Init(1) Condition(TARGET_DLLIMPORT_DECL_ATTRIBUTES)
Don't emit dllexported inline functions unless needed.
flabels-ok
Implement resolution of DR 150 for matching of template template arguments.
fnext-runtime
-ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime)
+ObjC ObjC++ LTO RejectNegative Var(flag_next_runtime)
Generate code for NeXT (Apple Mac OS X) runtime environment.
fnil-receivers
Treat a throw() exception specification as noexcept to improve code size.
fobjc-abi-version=
-ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi)
+ObjC ObjC++ LTO Joined RejectNegative UInteger Var(flag_objc_abi)
Specify which ABI to use for Objective-C family code and meta-data generation.
; Generate special '- .cxx_construct' and '- .cxx_destruct' methods
Display this information.
-help=
-Common Driver Report Joined
+Common Driver Joined
--help=<class> Display descriptions of a specific class of options. <class> is one or more of optimizers, target, warnings, undocumented, params.
-language
The version of the C++ ABI in use.
faggressive-loop-optimizations
-Common Report Var(flag_aggressive_loop_optimizations) Optimization Init(1)
+Common Var(flag_aggressive_loop_optimizations) Optimization Init(1)
Aggressively optimize loops using language constraints.
falign-functions
-Common Report Var(flag_align_functions) Optimization
+Common Var(flag_align_functions) Optimization
Align the start of functions.
falign-functions=
Common RejectNegative Joined Var(str_align_functions) Optimization
flimit-function-alignment
-Common Report Var(flag_limit_function_alignment) Optimization Init(0)
+Common Var(flag_limit_function_alignment) Optimization Init(0)
falign-jumps
-Common Report Var(flag_align_jumps) Optimization
+Common Var(flag_align_jumps) Optimization
Align labels which are only reached by jumping.
falign-jumps=
Common RejectNegative Joined Var(str_align_jumps) Optimization
falign-labels
-Common Report Var(flag_align_labels) Optimization
+Common Var(flag_align_labels) Optimization
Align all labels.
falign-labels=
Common RejectNegative Joined Var(str_align_labels) Optimization
falign-loops
-Common Report Var(flag_align_loops) Optimization
+Common Var(flag_align_loops) Optimization
Align the start of loops.
falign-loops=
Common RejectNegative Joined Var(str_align_loops) Optimization
fallow-store-data-races
-Common Report Var(flag_store_data_races) Optimization
+Common Var(flag_store_data_races) Optimization
Allow the compiler to introduce new data races on stores.
fanalyzer
Does nothing. Preserved for backward compatibility.
fsanitize=
-Common Driver Report Joined
+Common Driver Joined
Select what to sanitize.
fsanitize-coverage=
-Common Report Joined
+Common Joined
Select type of coverage sanitization.
fasan-shadow-offset=
in user-defined sections.
fsanitize-recover=
-Common Report Joined
+Common Joined
After diagnosing undefined behavior attempt to continue execution.
fsanitize-recover
-Common Report
+Common
This switch is deprecated; use -fsanitize-recover= instead.
fsanitize-address-use-after-scope
-Common Driver Report Var(flag_sanitize_address_use_after_scope) Init(0)
+Common Driver Var(flag_sanitize_address_use_after_scope) Init(0)
fsanitize-undefined-trap-on-error
-Common Driver Report Var(flag_sanitize_undefined_trap_on_error) Init(0)
+Common Driver Var(flag_sanitize_undefined_trap_on_error) Init(0)
Use trap instead of a library function for undefined behavior sanitization.
fasynchronous-unwind-tables
-Common Report Var(flag_asynchronous_unwind_tables) Optimization
+Common Var(flag_asynchronous_unwind_tables) Optimization
Generate unwind tables that are exact at each instruction boundary.
fauto-inc-dec
-Common Report Var(flag_auto_inc_dec) Init(1) Optimization
+Common Var(flag_auto_inc_dec) Init(1) Optimization
Generate auto-inc/dec instructions.
fauto-profile
-Common Report Var(flag_auto_profile)
+Common Var(flag_auto_profile)
Use sample profile information for call graph node weights. The default
profile file is fbdata.afdo in 'pwd'.
; For Java: defaults to on.
; For Fortran: defaults to off.
fbounds-check
-Common Report Var(flag_bounds_check)
+Common Var(flag_bounds_check)
Generate code to check bounds before indexing arrays.
fbranch-count-reg
-Common Report Var(flag_branch_on_count_reg) Optimization
+Common Var(flag_branch_on_count_reg) Optimization
Replace add, compare, branch with branch on count register.
fbranch-probabilities
-Common Report Var(flag_branch_probabilities) Optimization
+Common Var(flag_branch_probabilities) Optimization
Use profiling information for branch probabilities.
fbranch-target-load-optimize
Does nothing. Preserved for backward compatibility.
fcallgraph-info
-Common Report RejectNegative Var(flag_callgraph_info) Init(NO_CALLGRAPH_INFO);
+Common RejectNegative Var(flag_callgraph_info) Init(NO_CALLGRAPH_INFO);
Output callgraph information on a per-file basis.
fcallgraph-info=
-Common Report RejectNegative Joined
+Common RejectNegative Joined
Output callgraph information on a per-file basis with decorations.
fcall-saved-
; be saved across function calls, if that produces overall better code.
; Optional now, so people can test it.
fcaller-saves
-Common Report Var(flag_caller_saves) Optimization
+Common Var(flag_caller_saves) Optimization
Save registers around function calls.
fcheck-data-deps
Perform internal consistency checkings.
fcode-hoisting
-Common Report Var(flag_code_hoisting) Optimization
+Common Var(flag_code_hoisting) Optimization
Enable code hoisting.
fcombine-stack-adjustments
-Common Report Var(flag_combine_stack_adjustments) Optimization
+Common Var(flag_combine_stack_adjustments) Optimization
Looks for opportunities to reduce stack adjustments and stack references.
fcommon
-Common Report Var(flag_no_common,0) Init(1)
+Common Var(flag_no_common,0) Init(1)
Put uninitialized globals in the common section.
fcompare-debug
Run only the second compilation of -fcompare-debug.
fcompare-elim
-Common Report Var(flag_compare_elim_after_reload) Optimization
+Common Var(flag_compare_elim_after_reload) Optimization
Perform comparison elimination after register allocation has finished.
fconserve-stack
Do not perform optimizations increasing noticeably stack usage.
fcprop-registers
-Common Report Var(flag_cprop_registers) Optimization
+Common Var(flag_cprop_registers) Optimization
Perform a register copy-propagation optimization pass.
fcrossjumping
-Common Report Var(flag_crossjumping) Optimization
+Common Var(flag_crossjumping) Optimization
Perform cross-jumping optimization.
fcse-follow-jumps
-Common Report Var(flag_cse_follow_jumps) Optimization
+Common Var(flag_cse_follow_jumps) Optimization
When running CSE, follow jumps to their targets.
fcse-skip-blocks
Does nothing. Preserved for backward compatibility.
fcx-limited-range
-Common Report Var(flag_cx_limited_range) Optimization SetByCombined
+Common Var(flag_cx_limited_range) Optimization SetByCombined
Omit range reduction step when performing complex division.
fcx-fortran-rules
-Common Report Var(flag_cx_fortran_rules) Optimization
+Common Var(flag_cx_fortran_rules) Optimization
Complex multiplication and division follow Fortran rules.
fdata-sections
-Common Report Var(flag_data_sections)
+Common Var(flag_data_sections)
Place data items into their own section.
fdbg-cnt-list
-Common Report Var(flag_dbg_cnt_list)
+Common Var(flag_dbg_cnt_list)
List all available debugging counters with their limits and counts.
fdbg-cnt=
-ffile-prefix-map=<old>=<new> Map one directory name to another in compilation result.
fdebug-types-section
-Common Report Var(flag_debug_types_section) Init(0)
+Common Var(flag_debug_types_section) Init(0)
Output .debug_types section when using DWARF v4 debuginfo.
; Nonzero for -fdefer-pop: don't pop args after each function call
; instead save them up to pop many calls' args with one insns.
fdefer-pop
-Common Report Var(flag_defer_pop) Optimization
+Common Var(flag_defer_pop) Optimization
Defer popping functions args from stack until later.
fdelayed-branch
-Common Report Var(flag_delayed_branch) Optimization
+Common Var(flag_delayed_branch) Optimization
Attempt to fill delay slots of branch instructions.
fdelete-dead-exceptions
-Common Report Var(flag_delete_dead_exceptions) Init(0) Optimization
+Common Var(flag_delete_dead_exceptions) Init(0) Optimization
Delete dead instructions that may throw exceptions.
fdelete-null-pointer-checks
-Common Report Var(flag_delete_null_pointer_checks) Init(-1) Optimization
+Common Var(flag_delete_null_pointer_checks) Init(-1) Optimization
Delete useless null pointer checks.
fdevirtualize-at-ltrans
-Common Report Var(flag_ltrans_devirtualize)
+Common Var(flag_ltrans_devirtualize)
Stream extra data to support more aggressive devirtualization in LTO local transformation mode.
fdevirtualize-speculatively
-Common Report Var(flag_devirtualize_speculatively) Optimization
+Common Var(flag_devirtualize_speculatively) Optimization
Perform speculative devirtualization.
fdevirtualize
-Common Report Var(flag_devirtualize) Optimization
+Common Var(flag_devirtualize) Optimization
Try to convert virtual calls to direct ones.
fdiagnostics-show-location=
-fdump-go-spec=filename Write all declarations to file as Go code.
fdump-noaddr
-Common Report Var(flag_dump_noaddr)
+Common Var(flag_dump_noaddr)
Suppress output of addresses in debugging dumps.
freport-bug
Dump optimization passes.
fdump-unnumbered
-Common Report Var(flag_dump_unnumbered)
+Common Var(flag_dump_unnumbered)
Suppress output of instruction numbers, line number notes and addresses in debugging dumps.
fdump-unnumbered-links
-Common Report Var(flag_dump_unnumbered_links)
+Common Var(flag_dump_unnumbered_links)
Suppress output of previous and next insn numbers in debugging dumps.
fdwarf2-cfi-asm
-Common Report Var(flag_dwarf2_cfi_asm) Init(HAVE_GAS_CFI_DIRECTIVE)
+Common Var(flag_dwarf2_cfi_asm) Init(HAVE_GAS_CFI_DIRECTIVE)
Enable CFI tables via GAS assembler directives.
fearly-inlining
-Common Report Var(flag_early_inlining) Init(1) Optimization
+Common Var(flag_early_inlining) Init(1) Optimization
Perform early inlining.
feliminate-dwarf2-dups
Does nothing. Preserved for backward compatibility.
fipa-sra
-Common Report Var(flag_ipa_sra) Init(0) Optimization
+Common Var(flag_ipa_sra) Init(0) Optimization
Perform interprocedural reduction of aggregates.
feliminate-unused-debug-symbols
-Common Report Var(flag_debug_only_used_symbols) Init(1)
+Common Var(flag_debug_only_used_symbols) Init(1)
Perform unused symbol elimination in debug info.
feliminate-unused-debug-types
-Common Report Var(flag_eliminate_unused_debug_types) Init(1)
+Common Var(flag_eliminate_unused_debug_types) Init(1)
Perform unused type elimination in debug info.
femit-class-debug-always
-Common Report Var(flag_emit_class_debug_always) Init(0)
+Common Var(flag_emit_class_debug_always) Init(0)
Do not suppress C++ class debug information.
fexceptions
-Common Report Var(flag_exceptions) Optimization
+Common Var(flag_exceptions) Optimization
Enable exception handling.
fexpensive-optimizations
-Common Report Var(flag_expensive_optimizations) Optimization
+Common Var(flag_expensive_optimizations) Optimization
Perform a number of minor, expensive optimizations.
fexcess-precision=
Output lto objects containing both the intermediate language and binary output.
ffinite-math-only
-Common Report Var(flag_finite_math_only) Optimization SetByCombined
+Common Var(flag_finite_math_only) Optimization SetByCombined
Assume no NaNs or infinities are generated.
ffinite-loops
-Common Report Var(flag_finite_loops) Optimization Init(0)
+Common Var(flag_finite_loops) Optimization Init(0)
Assume that loops with an exit will terminate and not loop indefinitely.
ffixed-
-ffixed-<register> Mark <register> as being unavailable to the compiler.
ffloat-store
-Common Report Var(flag_float_store) Optimization
+Common Var(flag_float_store) Optimization
Don't allocate floats and doubles in extended-precision registers.
fforce-addr
Does nothing. Preserved for backward compatibility.
fforward-propagate
-Common Report Var(flag_forward_propagate) Optimization
+Common Var(flag_forward_propagate) Optimization
Perform a forward propagation pass on RTL.
ffp-contract=
Enum(fp_contract_mode) String(fast) Value(FP_CONTRACT_FAST)
ffp-int-builtin-inexact
-Common Report Var(flag_fp_int_builtin_inexact) Init(1) Optimization
+Common Var(flag_fp_int_builtin_inexact) Init(1) Optimization
Allow built-in functions ceil, floor, round, trunc to raise \"inexact\" exceptions.
; Nonzero means don't put addresses of constant functions in registers.
; Used for compiling the Unix kernel, where strange substitutions are
; done on the assembly output.
ffunction-cse
-Common Report Var(flag_no_function_cse,0) Optimization
+Common Var(flag_no_function_cse,0) Optimization
Allow function addresses to be held in registers.
ffunction-sections
-Common Report Var(flag_function_sections)
+Common Var(flag_function_sections)
Place each function into its own section.
fgcse
-Common Report Var(flag_gcse) Optimization
+Common Var(flag_gcse) Optimization
Perform global common subexpression elimination.
fgcse-lm
-Common Report Var(flag_gcse_lm) Init(1) Optimization
+Common Var(flag_gcse_lm) Init(1) Optimization
Perform enhanced load motion during global common subexpression elimination.
fgcse-sm
-Common Report Var(flag_gcse_sm) Init(0) Optimization
+Common Var(flag_gcse_sm) Init(0) Optimization
Perform store motion after global common subexpression elimination.
fgcse-las
-Common Report Var(flag_gcse_las) Init(0) Optimization
+Common Var(flag_gcse_las) Init(0) Optimization
Perform redundant load after store elimination in global common subexpression
elimination.
fgcse-after-reload
-Common Report Var(flag_gcse_after_reload) Optimization
+Common Var(flag_gcse_after_reload) Optimization
Perform global common subexpression elimination after register allocation has
finished.
Enum(dwarf_gnat_encodings) String(minimal) Value(DWARF_GNAT_ENCODINGS_MINIMAL)
fgnat-encodings=
-Common Enum(dwarf_gnat_encodings) Joined RejectNegative Report Undocumented Var(gnat_encodings)
+Common Enum(dwarf_gnat_encodings) Joined RejectNegative Undocumented Var(gnat_encodings)
-fgnat-encodings=[all|gdb|minimal] Select the balance between GNAT encodings and standard DWARF emitted in the debug information.
; This option is not documented yet as its semantics will change.
fgraphite
-Common Report Var(flag_graphite) Optimization
+Common Var(flag_graphite) Optimization
Enable in and out of Graphite representation.
fgraphite-identity
-Common Report Var(flag_graphite_identity) Optimization
+Common Var(flag_graphite_identity) Optimization
Enable Graphite Identity transformation.
fhoist-adjacent-loads
-Common Report Var(flag_hoist_adjacent_loads) Optimization
+Common Var(flag_hoist_adjacent_loads) Optimization
Enable hoisting adjacent loads to encourage generating conditional move
instructions.
fkeep-gc-roots-live
-Common Undocumented Report Var(flag_keep_gc_roots_live) Optimization
+Common Undocumented Var(flag_keep_gc_roots_live) Optimization
; Always keep a pointer to a live memory block
flarge-source-files
-Common Report Var(flag_large_source_files) Init(0)
+Common Var(flag_large_source_files) Init(0)
Improve GCC's ability to track column numbers in large source files,
at the expense of slower compilation.
floop-parallelize-all
-Common Report Var(flag_loop_parallelize_all) Optimization
+Common Var(flag_loop_parallelize_all) Optimization
Mark all loops as parallel.
floop-strip-mine
Enable loop nest transforms. Same as -floop-nest-optimize.
floop-interchange
-Common Report Var(flag_loop_interchange) Optimization
+Common Var(flag_loop_interchange) Optimization
Enable loop interchange on trees.
floop-block
Enable loop nest transforms. Same as -floop-nest-optimize.
floop-unroll-and-jam
-Common Report Var(flag_unroll_jam) Optimization
+Common Var(flag_unroll_jam) Optimization
Perform unroll-and-jam on loops.
fgnu-tm
-Common Report Var(flag_tm)
+Common Var(flag_tm)
Enable support for GNU transactional memory.
fgnu-unique
-Common Report Var(flag_gnu_unique) Init(1)
+Common Var(flag_gnu_unique) Init(1)
Use STB_GNU_UNIQUE if supported by the assembler.
floop-flatten
Does nothing. Preserved for backward compatibility.
floop-nest-optimize
-Common Report Var(flag_loop_nest_optimize) Optimization
+Common Var(flag_loop_nest_optimize) Optimization
Enable the loop nest optimizer.
fstrict-volatile-bitfields
-Common Report Var(flag_strict_volatile_bitfields) Init(-1) Optimization
+Common Var(flag_strict_volatile_bitfields) Init(-1) Optimization
Force bitfield accesses to match their type width.
fstore-merging
-Common Report Var(flag_store_merging) Optimization
+Common Var(flag_store_merging) Optimization
Merge adjacent stores.
fguess-branch-probability
-Common Report Var(flag_guess_branch_prob) Optimization
+Common Var(flag_guess_branch_prob) Optimization
Enable guessing of branch probabilities.
; Nonzero means ignore `#ident' directives. 0 means handle them.
; On SVR4 targets, it also controls whether or not to emit a
; string identifying the compiler.
fident
-Common Report Var(flag_no_ident,0)
+Common Var(flag_no_ident,0)
Process #ident directives.
fif-conversion
-Common Report Var(flag_if_conversion) Optimization
+Common Var(flag_if_conversion) Optimization
Perform conversion of conditional jumps to branchless equivalents.
fif-conversion2
-Common Report Var(flag_if_conversion2) Optimization
+Common Var(flag_if_conversion2) Optimization
Perform conversion of conditional jumps to conditional execution.
fstack-reuse=
Enum(stack_reuse_level) String(none) Value(SR_NONE)
ftree-loop-if-convert
-Common Report Var(flag_tree_loop_if_convert) Init(-1) Optimization
+Common Var(flag_tree_loop_if_convert) Init(-1) Optimization
Convert conditional jumps in innermost loops to branchless equivalents.
ftree-loop-if-convert-stores
; and it may be extended to other effects
; needed for crtstuff.c on other systems.
finhibit-size-directive
-Common Report Var(flag_inhibit_size_directive)
+Common Var(flag_inhibit_size_directive)
Do not generate .size directives.
findirect-inlining
-Common Report Var(flag_indirect_inlining) Optimization
+Common Var(flag_indirect_inlining) Optimization
Perform indirect inlining.
; General flag to enable inlining. Specifying -fno-inline will disable
; all inlining apart from always-inline functions.
finline
-Common Report Var(flag_no_inline,0) Init(0) Optimization
+Common Var(flag_no_inline,0) Init(0) Optimization
Enable inlining of function declared \"inline\", disabling disables all inlining.
finline-small-functions
-Common Report Var(flag_inline_small_functions) Optimization
+Common Var(flag_inline_small_functions) Optimization
Integrate functions into their callers when code size is known not to grow.
finline-functions
-Common Report Var(flag_inline_functions) Optimization
+Common Var(flag_inline_functions) Optimization
Integrate functions not declared \"inline\" into their callers when profitable.
finline-functions-called-once
-Common Report Var(flag_inline_functions_called_once) Optimization
+Common Var(flag_inline_functions_called_once) Optimization
Integrate functions only required by their single caller.
finline-limit-
-finline-limit=<number> Limit the size of inlined functions to <number>.
finline-atomics
-Common Report Var(flag_inline_atomics) Init(1) Optimization
+Common Var(flag_inline_atomics) Init(1) Optimization
Inline __atomic operations when a lock free instruction sequence is available.
fcf-protection
Common RejectNegative Alias(fcf-protection=,full)
fcf-protection=
-Common Report Joined RejectNegative Enum(cf_protection_level) Var(flag_cf_protection) Init(CF_NONE)
+Common Joined RejectNegative Enum(cf_protection_level) Var(flag_cf_protection) Init(CF_NONE)
-fcf-protection=[full|branch|return|none|check] Instrument functions with checks to verify jump/call/return control-flow transfer
instructions have valid targets.
Enum(cf_protection_level) String(none) Value(CF_NONE)
finstrument-functions
-Common Report Var(flag_instrument_function_entry_exit)
+Common Var(flag_instrument_function_entry_exit)
Instrument function entry and exit with profiling calls.
finstrument-functions-exclude-function-list=
-finstrument-functions-exclude-file-list=filename,... Do not instrument functions listed in files.
fipa-cp
-Common Report Var(flag_ipa_cp) Optimization
+Common Var(flag_ipa_cp) Optimization
Perform interprocedural constant propagation.
fipa-cp-clone
-Common Report Var(flag_ipa_cp_clone) Optimization
+Common Var(flag_ipa_cp_clone) Optimization
Perform cloning to make Interprocedural constant propagation stronger.
fipa-cp-alignment
Does nothing. Preserved for backward compatibility.
fipa-bit-cp
-Common Report Var(flag_ipa_bit_cp) Optimization
+Common Var(flag_ipa_bit_cp) Optimization
Perform interprocedural bitwise constant propagation.
fipa-modref
-Common Report Var(flag_ipa_modref) Optimization
+Common Var(flag_ipa_modref) Optimization
Perform interprocedural modref analysis.
fipa-profile
-Common Report Var(flag_ipa_profile) Init(0) Optimization
+Common Var(flag_ipa_profile) Init(0) Optimization
Perform interprocedural profile propagation.
fipa-pta
-Common Report Var(flag_ipa_pta) Init(0) Optimization
+Common Var(flag_ipa_pta) Init(0) Optimization
Perform interprocedural points-to analysis.
fipa-pure-const
-Common Report Var(flag_ipa_pure_const) Init(0) Optimization
+Common Var(flag_ipa_pure_const) Init(0) Optimization
Discover pure and const functions.
fipa-icf
-Common Report Var(flag_ipa_icf) Optimization
+Common Var(flag_ipa_icf) Optimization
Perform Identical Code Folding for functions and read-only variables.
fipa-icf-functions
-Common Report Var(flag_ipa_icf_functions) Optimization
+Common Var(flag_ipa_icf_functions) Optimization
Perform Identical Code Folding for functions.
fipa-icf-variables
-Common Report Var(flag_ipa_icf_variables) Optimization
+Common Var(flag_ipa_icf_variables) Optimization
Perform Identical Code Folding for variables.
fipa-reference
-Common Report Var(flag_ipa_reference) Init(0) Optimization
+Common Var(flag_ipa_reference) Init(0) Optimization
Discover read-only and non addressable static variables.
fipa-reference-addressable
-Common Report Var(flag_ipa_reference_addressable) Init(0) Optimization
+Common Var(flag_ipa_reference_addressable) Init(0) Optimization
Discover read-only, write-only and non-addressable static variables.
fipa-stack-alignment
-Common Report Var(flag_ipa_stack_alignment) Init(1) Optimization
+Common Var(flag_ipa_stack_alignment) Init(1) Optimization
Reduce stack alignment on call sites if possible.
fipa-matrix-reorg
Does nothing. Preserved for backward compatibility.
fipa-vrp
-Common Report Var(flag_ipa_vrp) Optimization
+Common Var(flag_ipa_vrp) Optimization
Perform IPA Value Range Propagation.
fira-algorithm=
Enum(ira_region) String(mixed) Value(IRA_REGION_MIXED)
fira-hoist-pressure
-Common Report Var(flag_ira_hoist_pressure) Init(1) Optimization
+Common Var(flag_ira_hoist_pressure) Init(1) Optimization
Use IRA based register pressure calculation
in RTL hoist optimizations.
fira-loop-pressure
-Common Report Var(flag_ira_loop_pressure) Optimization
+Common Var(flag_ira_loop_pressure) Optimization
Use IRA based register pressure calculation
in RTL loop optimizations.
fira-share-save-slots
-Common Report Var(flag_ira_share_save_slots) Init(1) Optimization
+Common Var(flag_ira_share_save_slots) Init(1) Optimization
Share slots for saving different hard registers.
fira-share-spill-slots
-Common Report Var(flag_ira_share_spill_slots) Init(1) Optimization
+Common Var(flag_ira_share_spill_slots) Init(1) Optimization
Share stack slots for spilled pseudo-registers.
fira-verbose=
-fira-verbose=<number> Control IRA's level of diagnostic messages.
fivopts
-Common Report Var(flag_ivopts) Init(1) Optimization
+Common Var(flag_ivopts) Init(1) Optimization
Optimize induction variables on trees.
fjump-tables
Use bit tests for sufficiently large switch statements.
fkeep-inline-functions
-Common Report Var(flag_keep_inline_functions)
+Common Var(flag_keep_inline_functions)
Generate code for functions even if they are fully inlined.
fkeep-static-functions
-Common Report Var(flag_keep_static_functions)
+Common Var(flag_keep_static_functions)
Generate code for static functions even if they are never called.
fkeep-static-consts
-Common Report Var(flag_keep_static_consts) Init(1)
+Common Var(flag_keep_static_consts) Init(1)
Emit static const variables even if they are not used.
fleading-underscore
-Common Report Var(flag_leading_underscore) Init(-1)
+Common Var(flag_leading_underscore) Init(-1)
Give external symbols a leading underscore.
floop-optimize
Does nothing. Preserved for backward compatibility.
flra-remat
-Common Report Var(flag_lra_remat) Optimization
+Common Var(flag_lra_remat) Optimization
Do CFG-sensitive rematerialization in LRA.
flto
Does nothing. Preserved for backward compatibility.
flto-report
-Common Report Var(flag_lto_report) Init(0)
+Common Var(flag_lto_report) Init(0)
Report various link-time optimization statistics.
flto-report-wpa
-Common Report Var(flag_lto_report_wpa) Init(0)
+Common Var(flag_lto_report_wpa) Init(0)
Report various link-time optimization statistics for WPA only.
fmath-errno
-Common Report Var(flag_errno_math) Init(1) Optimization SetByCombined
+Common Var(flag_errno_math) Init(1) Optimization SetByCombined
Set errno after built-in math functions.
fmax-errors=
-fmax-errors=<number> Maximum number of errors to report.
fmem-report
-Common Report Var(mem_report)
+Common Var(mem_report)
Report on permanent memory allocation.
fmem-report-wpa
-Common Report Var(mem_report_wpa)
+Common Var(mem_report_wpa)
Report on permanent memory allocation in WPA only.
; This will attempt to merge constant section constants, if 1 only
; string constants and constants from constant pool, if 2 also constant
; variables.
fmerge-all-constants
-Common Report Var(flag_merge_constants,2) Init(1)
+Common Var(flag_merge_constants,2) Init(1)
Attempt to merge identical constants and constant variables.
fmerge-constants
-Common Report Var(flag_merge_constants,1)
+Common Var(flag_merge_constants,1)
Attempt to merge identical constants across compilation units.
fmerge-debug-strings
-Common Report Var(flag_merge_debug_strings) Init(1)
+Common Var(flag_merge_debug_strings) Init(1)
Attempt to merge identical debug strings across compilation units.
fmessage-length=
-fmessage-length=<number> Limit diagnostics to <number> characters per line. 0 suppresses line-wrapping.
fmodulo-sched
-Common Report Var(flag_modulo_sched) Optimization
+Common Var(flag_modulo_sched) Optimization
Perform SMS based modulo scheduling before the first scheduling pass.
fmodulo-sched-allow-regmoves
-Common Report Var(flag_modulo_sched_allow_regmoves) Optimization
+Common Var(flag_modulo_sched_allow_regmoves) Optimization
Perform SMS based modulo scheduling with register moves allowed.
fmove-loop-invariants
-Common Report Var(flag_move_loop_invariants) Optimization
+Common Var(flag_move_loop_invariants) Optimization
Move loop invariant computations out of loops.
fdce
Use the RTL dead store elimination pass.
freschedule-modulo-scheduled-loops
-Common Report Var(flag_resched_modulo_sched) Optimization
+Common Var(flag_resched_modulo_sched) Optimization
Enable/Disable the traditional scheduling in loops that already passed modulo scheduling.
fnon-call-exceptions
-Common Report Var(flag_non_call_exceptions) Optimization
+Common Var(flag_non_call_exceptions) Optimization
Support synchronous non-call exceptions.
foffload=
Enum(offload_abi) String(lp64) Value(OFFLOAD_ABI_LP64)
fomit-frame-pointer
-Common Report Var(flag_omit_frame_pointer) Optimization
+Common Var(flag_omit_frame_pointer) Optimization
When possible do not generate stack frames.
fopt-info
-Common Report Var(flag_opt_info) Optimization
+Common Var(flag_opt_info) Optimization
Enable all optimization info dumps on stderr.
fopt-info-
-fopt-info[-<type>=filename] Dump compiler optimization details.
fsave-optimization-record
-Common Report Var(flag_save_optimization_record) Optimization
+Common Var(flag_save_optimization_record) Optimization
Write a SRCFILE.opt-record.json file detailing what optimizations were performed.
foptimize-register-move
Does nothing. Preserved for backward compatibility.
foptimize-sibling-calls
-Common Report Var(flag_optimize_sibling_calls) Optimization
+Common Var(flag_optimize_sibling_calls) Optimization
Optimize sibling and tail recursive calls.
fpartial-inlining
-Common Report Var(flag_partial_inlining) Optimization
+Common Var(flag_partial_inlining) Optimization
Perform partial inlining.
fpre-ipa-mem-report
-Common Report Var(pre_ipa_mem_report)
+Common Var(pre_ipa_mem_report)
Report on memory allocation before interprocedural optimization.
fpost-ipa-mem-report
-Common Report Var(post_ipa_mem_report)
+Common Var(post_ipa_mem_report)
Report on memory allocation before interprocedural optimization.
fpack-struct
-Common Report Var(flag_pack_struct) Optimization
+Common Var(flag_pack_struct) Optimization
Pack structure members together without holes.
fpack-struct=
-fpack-struct=<number> Set initial maximum structure member alignment.
fpcc-struct-return
-Common Report Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN)
+Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN)
Return small aggregates in memory, not registers.
fpeel-loops
-Common Report Var(flag_peel_loops) Optimization
+Common Var(flag_peel_loops) Optimization
Perform loop peeling.
fpeephole
-Common Report Var(flag_no_peephole,0) Optimization
+Common Var(flag_no_peephole,0) Optimization
Enable machine specific peephole optimizations.
fpeephole2
-Common Report Var(flag_peephole2) Optimization
+Common Var(flag_peephole2) Optimization
Enable an RTL peephole pass before sched2.
fPIC
-Common Report Var(flag_pic,2) Negative(fPIE) Init(-1)
+Common Var(flag_pic,2) Negative(fPIE) Init(-1)
Generate position-independent code if possible (large mode).
fPIE
-Common Report Var(flag_pie,2) Negative(fpic) Init(-1)
+Common Var(flag_pie,2) Negative(fpic) Init(-1)
Generate position-independent code for executables if possible (large mode).
fpic
-Common Report Var(flag_pic,1) Negative(fpie) Init(-1)
+Common Var(flag_pic,1) Negative(fpie) Init(-1)
Generate position-independent code if possible (small mode).
fpie
-Common Report Var(flag_pie,1) Negative(fPIC) Init(-1)
+Common Var(flag_pie,1) Negative(fPIC) Init(-1)
Generate position-independent code for executables if possible (small mode).
fplt
-Common Report Var(flag_plt) Init(1) Optimization
+Common Var(flag_plt) Init(1) Optimization
Use PLT for PIC calls (-fno-plt: load the address from GOT at call site).
fplugin=
-fplugin-arg-<name>-<key>[=<value>] Specify argument <key>=<value> for plugin <name>.
fpredictive-commoning
-Common Report Var(flag_predictive_commoning) Optimization
+Common Var(flag_predictive_commoning) Optimization
Run predictive commoning optimization.
fprefetch-loop-arrays
-Common Report Var(flag_prefetch_loop_arrays) Init(-1) Optimization
+Common Var(flag_prefetch_loop_arrays) Init(-1) Optimization
Generate prefetch instructions, if available, for arrays in loops.
fprofile
-Common Report Var(profile_flag)
+Common Var(profile_flag)
Enable basic program profiling code.
fprofile-abs-path
-Common Report Var(profile_abs_path_flag)
+Common Var(profile_abs_path_flag)
Generate absolute source path names for gcov.
fprofile-arcs
-Common Report Var(profile_arc_flag)
+Common Var(profile_arc_flag)
Insert arc-based program profiling code.
fprofile-dir=
Select the name for storing the profile note file.
fprofile-correction
-Common Report Var(flag_profile_correction)
+Common Var(flag_profile_correction)
Enable correction of flow inconsistent profile data input.
fprofile-update=
Register the profile information in the specified section instead of using a constructor/destructor.
fprofile-partial-training
-Common Report Var(flag_profile_partial_training) Optimization
+Common Var(flag_profile_partial_training) Optimization
Do not assume that functions never executed during the train run are cold.
fprofile-use
Enable common options for performing profile feedback directed optimizations, and set -fprofile-dir=.
fprofile-values
-Common Report Var(flag_profile_values)
+Common Var(flag_profile_values)
Insert code to profile values of expressions.
fprofile-report
-Common Report Var(profile_report)
+Common Var(profile_report)
Report on consistency of profile.
fprofile-reorder-functions
-Common Report Var(flag_profile_reorder_functions) Optimization
+Common Var(flag_profile_reorder_functions) Optimization
Enable function reordering that improves code placement.
fpatchable-function-entry=
; records information in the assembler output file as comments, so
; they never reach the object file.
frecord-gcc-switches
-Common Report Var(flag_record_gcc_switches)
+Common Var(flag_record_gcc_switches)
Record gcc command line switches in the object file.
freg-struct-return
-Common Report Var(flag_pcc_struct_return,0) Optimization
+Common Var(flag_pcc_struct_return,0) Optimization
Return small aggregates in registers.
fregmove
Does nothing. Preserved for backward compatibility.
flifetime-dse
-Common Report Var(flag_lifetime_dse,2) Init(2) Optimization
+Common Var(flag_lifetime_dse,2) Init(2) Optimization
Tell DSE that the storage for a C++ object is dead when the constructor
starts and when the destructor finishes.
Common RejectNegative Alias(flive-patching=,inline-clone) Optimization
flive-patching=
-Common Report Joined RejectNegative Enum(live_patching_level) Var(flag_live_patching) Init(LIVE_PATCHING_NONE) Optimization
+Common Joined RejectNegative Enum(live_patching_level) Var(flag_live_patching) Init(LIVE_PATCHING_NONE) Optimization
-flive-patching=[inline-only-static|inline-clone] Control IPA
optimizations to provide a safe compilation for live-patching. At the same
time, provides multiple-level control on the enabled IPA optimizations.
Enum(live_patching_level) String(inline-clone) Value(LIVE_PATCHING_INLINE_CLONE)
fallocation-dce
-Common Report Var(flag_allocation_dce) Init(1) Optimization
+Common Var(flag_allocation_dce) Init(1) Optimization
Tell DCE to remove unused C++ allocations.
flive-range-shrinkage
-Common Report Var(flag_live_range_shrinkage) Init(0) Optimization
+Common Var(flag_live_range_shrinkage) Init(0) Optimization
Relief of register pressure through live range shrinkage.
frename-registers
-Common Report Var(flag_rename_registers) Init(2) Optimization
+Common Var(flag_rename_registers) Init(2) Optimization
Perform a register renaming optimization pass.
fschedule-fusion
-Common Report Var(flag_schedule_fusion) Init(2) Optimization
+Common Var(flag_schedule_fusion) Init(2) Optimization
Perform a target dependent instruction fusion optimization pass.
freorder-blocks
-Common Report Var(flag_reorder_blocks) Optimization
+Common Var(flag_reorder_blocks) Optimization
Reorder basic blocks to improve code placement.
freorder-blocks-algorithm=
Enum(reorder_blocks_algorithm) String(stc) Value(REORDER_BLOCKS_ALGORITHM_STC)
freorder-blocks-and-partition
-Common Report Var(flag_reorder_blocks_and_partition) Optimization
+Common Var(flag_reorder_blocks_and_partition) Optimization
Reorder basic blocks and partition into hot and cold sections.
freorder-functions
-Common Report Var(flag_reorder_functions) Optimization
+Common Var(flag_reorder_functions) Optimization
Reorder functions to improve code placement.
frerun-cse-after-loop
-Common Report Var(flag_rerun_cse_after_loop) Optimization
+Common Var(flag_rerun_cse_after_loop) Optimization
Add a common subexpression elimination pass after loop optimizations.
frerun-loop-opt
Does nothing. Preserved for backward compatibility.
frounding-math
-Common Report Var(flag_rounding_math) Optimization SetByCombined
+Common Var(flag_rounding_math) Optimization SetByCombined
Disable optimizations that assume default FP rounding behavior.
fsched-interblock
-Common Report Var(flag_schedule_interblock) Init(1) Optimization
+Common Var(flag_schedule_interblock) Init(1) Optimization
Enable scheduling across basic blocks.
fsched-pressure
-Common Report Var(flag_sched_pressure) Init(0) Optimization
+Common Var(flag_sched_pressure) Init(0) Optimization
Enable register pressure sensitive insn scheduling.
fsched-spec
-Common Report Var(flag_schedule_speculative) Init(1) Optimization
+Common Var(flag_schedule_speculative) Init(1) Optimization
Allow speculative motion of non-loads.
fsched-spec-load
-Common Report Var(flag_schedule_speculative_load) Optimization
+Common Var(flag_schedule_speculative_load) Optimization
Allow speculative motion of some loads.
fsched-spec-load-dangerous
-Common Report Var(flag_schedule_speculative_load_dangerous) Optimization
+Common Var(flag_schedule_speculative_load_dangerous) Optimization
Allow speculative motion of more loads.
fsched-verbose=
-fsched-verbose=<number> Set the verbosity level of the scheduler.
fsched2-use-superblocks
-Common Report Var(flag_sched2_use_superblocks) Optimization
+Common Var(flag_sched2_use_superblocks) Optimization
If scheduling post reload, do superblock scheduling.
fsched2-use-traces
Does nothing. Preserved for backward compatibility.
fschedule-insns
-Common Report Var(flag_schedule_insns) Optimization
+Common Var(flag_schedule_insns) Optimization
Reschedule instructions before register allocation.
fschedule-insns2
-Common Report Var(flag_schedule_insns_after_reload) Optimization
+Common Var(flag_schedule_insns_after_reload) Optimization
Reschedule instructions after register allocation.
; This flag should be on when a target implements non-trivial
; scheduling hooks, maybe saving some information for its own sake.
; On IA64, for example, this is used for correct bundling.
fselective-scheduling
-Common Report Var(flag_selective_scheduling) Optimization
+Common Var(flag_selective_scheduling) Optimization
Schedule instructions using selective scheduling algorithm.
fselective-scheduling2
-Common Report Var(flag_selective_scheduling2) Optimization
+Common Var(flag_selective_scheduling2) Optimization
Run selective scheduling after reload.
fself-test=
Run self-tests, using the given path to locate test files.
fsel-sched-pipelining
-Common Report Var(flag_sel_sched_pipelining) Init(0) Optimization
+Common Var(flag_sel_sched_pipelining) Init(0) Optimization
Perform software pipelining of inner loops during selective scheduling.
fsel-sched-pipelining-outer-loops
-Common Report Var(flag_sel_sched_pipelining_outer_loops) Init(0) Optimization
+Common Var(flag_sel_sched_pipelining_outer_loops) Init(0) Optimization
Perform software pipelining of outer loops during selective scheduling.
fsel-sched-reschedule-pipelined
-Common Report Var(flag_sel_sched_reschedule_pipelined) Init(0) Optimization
+Common Var(flag_sel_sched_reschedule_pipelined) Init(0) Optimization
Reschedule pipelined regions without pipelining.
fsemantic-interposition
-Common Report Var(flag_semantic_interposition) Init(1)
+Common Var(flag_semantic_interposition) Init(1)
Allow interposing function (or variables) by ones with different semantics (or initializer) respectively by dynamic linker.
; sched_stalled_insns means that insns can be moved prematurely from the queue
; of stalled insns into the ready list.
fsched-stalled-insns
-Common Report Var(flag_sched_stalled_insns) Optimization UInteger
+Common Var(flag_sched_stalled_insns) Optimization UInteger
Allow premature scheduling of queued insns.
fsched-stalled-insns=
; premature removal from the queue of stalled insns into the ready list (has
; an effect only if the flag 'sched_stalled_insns' is set).
fsched-stalled-insns-dep
-Common Report Var(flag_sched_stalled_insns_dep,1) Init(1) Optimization UInteger
+Common Var(flag_sched_stalled_insns_dep,1) Init(1) Optimization UInteger
Set dependence distance checking in premature scheduling of queued insns.
fsched-stalled-insns-dep=
-fsched-stalled-insns-dep=<number> Set dependence distance checking in premature scheduling of queued insns.
fsched-group-heuristic
-Common Report Var(flag_sched_group_heuristic) Init(1) Optimization
+Common Var(flag_sched_group_heuristic) Init(1) Optimization
Enable the group heuristic in the scheduler.
fsched-critical-path-heuristic
-Common Report Var(flag_sched_critical_path_heuristic) Init(1) Optimization
+Common Var(flag_sched_critical_path_heuristic) Init(1) Optimization
Enable the critical path heuristic in the scheduler.
fsched-spec-insn-heuristic
-Common Report Var(flag_sched_spec_insn_heuristic) Init(1) Optimization
+Common Var(flag_sched_spec_insn_heuristic) Init(1) Optimization
Enable the speculative instruction heuristic in the scheduler.
fsched-rank-heuristic
-Common Report Var(flag_sched_rank_heuristic) Init(1) Optimization
+Common Var(flag_sched_rank_heuristic) Init(1) Optimization
Enable the rank heuristic in the scheduler.
fsched-last-insn-heuristic
-Common Report Var(flag_sched_last_insn_heuristic) Init(1) Optimization
+Common Var(flag_sched_last_insn_heuristic) Init(1) Optimization
Enable the last instruction heuristic in the scheduler.
fsched-dep-count-heuristic
-Common Report Var(flag_sched_dep_count_heuristic) Init(1) Optimization
+Common Var(flag_sched_dep_count_heuristic) Init(1) Optimization
Enable the dependent count heuristic in the scheduler.
fsection-anchors
-Common Report Var(flag_section_anchors) Optimization
+Common Var(flag_section_anchors) Optimization
Access data in the same section from shared anchor points.
fsee
Does nothing. Preserved for backward compatibility.
free
-Common Report Var(flag_ree) Init(0) Optimization
+Common Var(flag_ree) Init(0) Optimization
Turn on Redundant Extensions Elimination pass.
fshow-column
-Common Report Var(flag_show_column) Init(1)
+Common Var(flag_show_column) Init(1)
Show column numbers in diagnostics, when available. Default on.
fshrink-wrap
-Common Report Var(flag_shrink_wrap) Optimization
+Common Var(flag_shrink_wrap) Optimization
Emit function prologues only before parts of the function that need it,
rather than at the top of the function.
fshrink-wrap-separate
-Common Report Var(flag_shrink_wrap_separate) Init(1) Optimization
+Common Var(flag_shrink_wrap_separate) Init(1) Optimization
Shrink-wrap parts of the prologue and epilogue separately.
fsignaling-nans
-Common Report Var(flag_signaling_nans) Optimization SetByCombined
+Common Var(flag_signaling_nans) Optimization SetByCombined
Disable optimizations observable by IEEE signaling NaNs.
fsigned-zeros
-Common Report Var(flag_signed_zeros) Init(1) Optimization SetByCombined
+Common Var(flag_signed_zeros) Init(1) Optimization SetByCombined
Disable floating point optimizations that ignore the IEEE signedness of zero.
fsingle-precision-constant
-Common Report Var(flag_single_precision_constant) Optimization
+Common Var(flag_single_precision_constant) Optimization
Convert floating point constants to single precision constants.
fsplit-ivs-in-unroller
-Common Report Var(flag_split_ivs_in_unroller) Init(1) Optimization
+Common Var(flag_split_ivs_in_unroller) Init(1) Optimization
Split lifetimes of induction variables when loops are unrolled.
fsplit-stack
-Common Report Var(flag_split_stack) Init(-1)
+Common Var(flag_split_stack) Init(-1)
Generate discontiguous stack frames.
fsplit-wide-types
-Common Report Var(flag_split_wide_types) Optimization
+Common Var(flag_split_wide_types) Optimization
Split wide types into independent registers.
fsplit-wide-types-early
-Common Report Var(flag_split_wide_types_early) Optimization
+Common Var(flag_split_wide_types_early) Optimization
Split wide types into independent registers earlier.
fssa-backprop
-Common Report Var(flag_ssa_backprop) Init(1) Optimization
+Common Var(flag_ssa_backprop) Init(1) Optimization
Enable backward propagation of use properties at the SSA level.
fssa-phiopt
-Common Report Var(flag_ssa_phiopt) Optimization
+Common Var(flag_ssa_phiopt) Optimization
Optimize conditional patterns using SSA PHI nodes.
fstdarg-opt
-Common Report Var(flag_stdarg_opt) Init(1) Optimization
+Common Var(flag_stdarg_opt) Init(1) Optimization
Optimize amount of stdarg registers saved to stack at start of function.
fvariable-expansion-in-unroller
-Common Report Var(flag_variable_expansion_in_unroller) Optimization
+Common Var(flag_variable_expansion_in_unroller) Optimization
Apply variable expansion when loops are unrolled.
fstack-check=
-Common Report RejectNegative Joined Optimization
+Common RejectNegative Joined Optimization
-fstack-check=[no|generic|specific] Insert stack checking code into the program.
fstack-check
Insert stack checking code into the program. Same as -fstack-check=specific.
fstack-clash-protection
-Common Report Var(flag_stack_clash_protection) Optimization
+Common Var(flag_stack_clash_protection) Optimization
Insert code to probe each page of stack space as it is allocated to protect
from stack-clash style attacks.
-fstack-limit-symbol=<name> Trap if the stack goes past symbol <name>.
fstack-protector
-Common Report Var(flag_stack_protect, 1) Init(-1) Optimization
+Common Var(flag_stack_protect, 1) Init(-1) Optimization
Use propolice as a stack protection method.
fstack-protector-all
-Common Report RejectNegative Var(flag_stack_protect, 2) Init(-1) Optimization
+Common RejectNegative Var(flag_stack_protect, 2) Init(-1) Optimization
Use a stack protection method for every function.
fstack-protector-strong
-Common Report RejectNegative Var(flag_stack_protect, 3) Init(-1) Optimization
+Common RejectNegative Var(flag_stack_protect, 3) Init(-1) Optimization
Use a smart stack protection method for certain functions.
fstack-protector-explicit
-Common Report RejectNegative Var(flag_stack_protect, 4) Optimization
+Common RejectNegative Var(flag_stack_protect, 4) Optimization
Use stack protection method only for functions with the stack_protect attribute.
fstack-usage
; types do not alias expressions of certain other types. Only used
; if alias analysis (in general) is enabled.
fstrict-aliasing
-Common Report Var(flag_strict_aliasing) Optimization
+Common Var(flag_strict_aliasing) Optimization
Assume strict aliasing rules apply.
fstrict-overflow
-Common Report
+Common
Treat signed overflow as undefined. Negated as -fwrapv -fwrapv-pointer.
fsync-libcalls
-Common Report Var(flag_sync_libcalls) Init(1)
+Common Var(flag_sync_libcalls) Init(1)
Implement __atomic operations via libcalls to legacy __sync functions.
fsyntax-only
-Common Report Var(flag_syntax_only)
+Common Var(flag_syntax_only)
Check for syntax errors, then stop.
ftest-coverage
-Common Report Var(flag_test_coverage)
+Common Var(flag_test_coverage)
Create data files needed by \"gcov\".
fthread-jumps
-Common Report Var(flag_thread_jumps) Optimization
+Common Var(flag_thread_jumps) Optimization
Perform jump threading optimizations.
ftime-report
-Common Report Var(time_report)
+Common Var(time_report)
Report the time taken by each compiler pass.
ftime-report-details
-Common Report Var(time_report_details)
+Common Var(time_report_details)
Record times taken by sub-phases separately.
ftls-model=
Enum(tls_model) String(local-exec) Value(TLS_MODEL_LOCAL_EXEC)
ftoplevel-reorder
-Common Report Var(flag_toplevel_reorder) Init(2) Optimization
+Common Var(flag_toplevel_reorder) Init(2) Optimization
Reorder top level functions, variables, and asms.
ftracer
-Common Report Var(flag_tracer) Optimization
+Common Var(flag_tracer) Optimization
Perform superblock formation via tail duplication.
ftrampolines
-Common Report Var(flag_trampolines) Init(0)
+Common Var(flag_trampolines) Init(0)
For targets that normally need trampolines for nested functions, always
generate them instead of using descriptors.
; (user-visible) trap. This is the case, for example, in nonstop
; IEEE 754 arithmetic.
ftrapping-math
-Common Report Var(flag_trapping_math) Init(1) Optimization SetByCombined
+Common Var(flag_trapping_math) Init(1) Optimization SetByCombined
Assume floating-point operations can trap.
ftrapv
-Common Report Var(flag_trapv) Optimization
+Common Var(flag_trapv) Optimization
Trap for signed overflow in addition, subtraction and multiplication.
ftree-ccp
-Common Report Var(flag_tree_ccp) Optimization
+Common Var(flag_tree_ccp) Optimization
Enable SSA-CCP optimization on trees.
ftree-bit-ccp
-Common Report Var(flag_tree_bit_ccp) Optimization
+Common Var(flag_tree_bit_ccp) Optimization
Enable SSA-BIT-CCP optimization on trees.
ftree-store-ccp
Does nothing. Preserved for backward compatibility.
ftree-ch
-Common Report Var(flag_tree_ch) Optimization
+Common Var(flag_tree_ch) Optimization
Enable loop header copying on trees.
ftree-coalesce-inlined-vars
Does nothing. Preserved for backward compatibility.
ftree-coalesce-vars
-Common Report Var(flag_tree_coalesce_vars) Optimization
+Common Var(flag_tree_coalesce_vars) Optimization
Enable SSA coalescing of user variables.
ftree-copyrename
Does nothing. Preserved for backward compatibility.
ftree-copy-prop
-Common Report Var(flag_tree_copy_prop) Optimization
+Common Var(flag_tree_copy_prop) Optimization
Enable copy propagation on trees.
ftree-store-copy-prop
Does nothing. Preserved for backward compatibility.
ftree-cselim
-Common Report Var(flag_tree_cselim) Init(2) Optimization
+Common Var(flag_tree_cselim) Init(2) Optimization
Transform condition stores into unconditional ones.
ftree-switch-conversion
-Common Report Var(flag_tree_switch_conversion) Optimization
+Common Var(flag_tree_switch_conversion) Optimization
Perform conversions of switch initializations.
ftree-dce
-Common Report Var(flag_tree_dce) Optimization
+Common Var(flag_tree_dce) Optimization
Enable SSA dead code elimination optimization on trees.
ftree-dominator-opts
-Common Report Var(flag_tree_dom) Optimization
+Common Var(flag_tree_dom) Optimization
Enable dominator optimizations.
ftree-tail-merge
-Common Report Var(flag_tree_tail_merge) Optimization
+Common Var(flag_tree_tail_merge) Optimization
Enable tail merging on trees.
ftree-dse
-Common Report Var(flag_tree_dse) Optimization
+Common Var(flag_tree_dse) Optimization
Enable dead store elimination.
ftree-forwprop
-Common Report Var(flag_tree_forwprop) Init(1) Optimization
+Common Var(flag_tree_forwprop) Init(1) Optimization
Enable forward propagation on trees.
ftree-fre
-Common Report Var(flag_tree_fre) Optimization
+Common Var(flag_tree_fre) Optimization
Enable Full Redundancy Elimination (FRE) on trees.
foptimize-strlen
-Common Report Var(flag_optimize_strlen) Optimization
+Common Var(flag_optimize_strlen) Optimization
Enable string length optimizations on trees.
fisolate-erroneous-paths-dereference
-Common Report Var(flag_isolate_erroneous_paths_dereference) Optimization
+Common Var(flag_isolate_erroneous_paths_dereference) Optimization
Detect paths that trigger erroneous or undefined behavior due to
dereferencing a null pointer. Isolate those paths from the main control
flow and turn the statement with erroneous or undefined behavior into a trap.
fisolate-erroneous-paths-attribute
-Common Report Var(flag_isolate_erroneous_paths_attribute) Optimization
+Common Var(flag_isolate_erroneous_paths_attribute) Optimization
Detect paths that trigger erroneous or undefined behavior due to a null value
being used in a way forbidden by a returns_nonnull or nonnull
attribute. Isolate those paths from the main control flow and turn the
statement with erroneous or undefined behavior into a trap.
ftree-loop-distribution
-Common Report Var(flag_tree_loop_distribution) Optimization
+Common Var(flag_tree_loop_distribution) Optimization
Enable loop distribution on trees.
ftree-loop-distribute-patterns
-Common Report Var(flag_tree_loop_distribute_patterns) Optimization
+Common Var(flag_tree_loop_distribute_patterns) Optimization
Enable loop distribution for patterns transformed into a library call.
ftree-loop-im
-Common Report Var(flag_tree_loop_im) Init(1) Optimization
+Common Var(flag_tree_loop_im) Init(1) Optimization
Enable loop invariant motion on trees.
ftree-loop-linear
Enable loop nest transforms. Same as -floop-nest-optimize.
ftree-loop-ivcanon
-Common Report Var(flag_tree_loop_ivcanon) Init(1) Optimization
+Common Var(flag_tree_loop_ivcanon) Init(1) Optimization
Create canonical induction variables in loops.
ftree-loop-optimize
-Common Report Var(flag_tree_loop_optimize) Init(1) Optimization
+Common Var(flag_tree_loop_optimize) Init(1) Optimization
Enable loop optimizations on tree level.
ftree-parallelize-loops=
-Common Report Joined RejectNegative UInteger Var(flag_tree_parallelize_loops) Init(1) Optimization
+Common Joined RejectNegative UInteger Var(flag_tree_parallelize_loops) Init(1) Optimization
-ftree-parallelize-loops=<number> Enable automatic parallelization of loops.
ftree-phiprop
-Common Report Var(flag_tree_phiprop) Init(1) Optimization
+Common Var(flag_tree_phiprop) Init(1) Optimization
Enable hoisting loads from conditional pointers.
ftree-pre
-Common Report Var(flag_tree_pre) Optimization
+Common Var(flag_tree_pre) Optimization
Enable SSA-PRE optimization on trees.
ftree-partial-pre
-Common Report Var(flag_tree_partial_pre) Optimization
+Common Var(flag_tree_partial_pre) Optimization
In SSA-PRE optimization on trees, enable partial-partial redundancy elimination.
ftree-pta
-Common Report Var(flag_tree_pta) Optimization
+Common Var(flag_tree_pta) Optimization
Perform function-local points-to analysis on trees.
ftree-reassoc
-Common Report Var(flag_tree_reassoc) Init(1) Optimization
+Common Var(flag_tree_reassoc) Init(1) Optimization
Enable reassociation on tree level.
ftree-salias
Does nothing. Preserved for backward compatibility.
ftree-sink
-Common Report Var(flag_tree_sink) Optimization
+Common Var(flag_tree_sink) Optimization
Enable SSA code sinking on trees.
ftree-slsr
-Common Report Var(flag_tree_slsr) Optimization
+Common Var(flag_tree_slsr) Optimization
Perform straight-line strength reduction.
ftree-sra
-Common Report Var(flag_tree_sra) Optimization
+Common Var(flag_tree_sra) Optimization
Perform scalar replacement of aggregates.
ftree-ter
-Common Report Var(flag_tree_ter) Optimization
+Common Var(flag_tree_ter) Optimization
Replace temporary expressions in the SSA->normal pass.
ftree-lrs
-Common Report Var(flag_tree_live_range_split) Optimization
+Common Var(flag_tree_live_range_split) Optimization
Perform live range splitting during the SSA->normal pass.
ftree-vrp
-Common Report Var(flag_tree_vrp) Init(0) Optimization
+Common Var(flag_tree_vrp) Init(0) Optimization
Perform Value Range Propagation on trees.
fsplit-paths
-Common Report Var(flag_split_paths) Init(0) Optimization
+Common Var(flag_split_paths) Init(0) Optimization
Split paths leading to loop backedges.
funconstrained-commons
trailing array.
funit-at-a-time
-Common Report Var(flag_unit_at_a_time) Init(1)
+Common Var(flag_unit_at_a_time) Init(1)
Compile whole compilation unit at a time.
funroll-loops
-Common Report Var(flag_unroll_loops) Optimization
+Common Var(flag_unroll_loops) Optimization
Perform loop unrolling when iteration count is known.
funroll-all-loops
-Common Report Var(flag_unroll_all_loops) Optimization
+Common Var(flag_unroll_all_loops) Optimization
Perform loop unrolling for all loops.
funroll-completely-grow-size
Does nothing. Preserved for backward compatibility.
fassociative-math
-Common Report Var(flag_associative_math) SetByCombined Optimization
+Common Var(flag_associative_math) SetByCombined Optimization
Allow optimization for floating-point arithmetic which may change the
result of the operation due to rounding.
freciprocal-math
-Common Report Var(flag_reciprocal_math) SetByCombined Optimization
+Common Var(flag_reciprocal_math) SetByCombined Optimization
Same as -fassociative-math for expressions which include division.
; Nonzero means that unsafe floating-point math optimizations are allowed
; are allowed to assume that their arguments and results are "normal"
; (e.g., nonnegative for SQRT).
funsafe-math-optimizations
-Common Report Var(flag_unsafe_math_optimizations) Optimization SetByCombined
+Common Var(flag_unsafe_math_optimizations) Optimization SetByCombined
Allow math optimizations that may violate IEEE or ISO standards.
funswitch-loops
-Common Report Var(flag_unswitch_loops) Optimization
+Common Var(flag_unswitch_loops) Optimization
Perform loop unswitching.
fsplit-loops
-Common Report Var(flag_split_loops) Optimization
+Common Var(flag_split_loops) Optimization
Perform loop splitting.
fversion-loops-for-strides
-Common Report Var(flag_version_loops_for_strides) Optimization
+Common Var(flag_version_loops_for_strides) Optimization
Version loops based on whether indices have a stride of one.
funwind-tables
-Common Report Var(flag_unwind_tables) Optimization
+Common Var(flag_unwind_tables) Optimization
Just generate unwind tables for exception handling.
fuse-ld=bfd
; will be set according to optimize, debug_info_level and debug_hooks
; in process_options ().
fvar-tracking
-Common Report Var(flag_var_tracking) Init(2) PerFunction
+Common Var(flag_var_tracking) Init(2) PerFunction
Perform variable tracking.
; Positive if we should track variables at assignments, negative if
; annotations. When flag_var_tracking_assignments ==
; AUTODETECT_VALUE it will be set according to flag_var_tracking.
fvar-tracking-assignments
-Common Report Var(flag_var_tracking_assignments) Init(2) PerFunction
+Common Var(flag_var_tracking_assignments) Init(2) PerFunction
Perform variable tracking by annotating assignments.
; Nonzero if we should toggle flag_var_tracking_assignments after
; processing options and computing its default. */
fvar-tracking-assignments-toggle
-Common Report Var(flag_var_tracking_assignments_toggle) PerFunction
+Common Var(flag_var_tracking_assignments_toggle) PerFunction
Toggle -fvar-tracking-assignments.
; Positive if we should track uninitialized variables, negative if
; annotations. When flag_var_tracking_uninit == AUTODETECT_VALUE it
; will be set according to flag_var_tracking.
fvar-tracking-uninit
-Common Report Var(flag_var_tracking_uninit) PerFunction
+Common Var(flag_var_tracking_uninit) PerFunction
Perform variable tracking and also tag variables that are uninitialized.
; Alias to enable both -ftree-loop-vectorize and -ftree-slp-vectorize.
ftree-vectorize
-Common Report Optimization
+Common Optimization
Enable vectorization on trees.
ftree-vectorizer-verbose=
Does nothing. Preserved for backward compatibility.
ftree-loop-vectorize
-Common Report Var(flag_tree_loop_vectorize) Optimization EnabledBy(ftree-vectorize)
+Common Var(flag_tree_loop_vectorize) Optimization EnabledBy(ftree-vectorize)
Enable loop vectorization on trees.
ftree-slp-vectorize
-Common Report Var(flag_tree_slp_vectorize) Optimization EnabledBy(ftree-vectorize)
+Common Var(flag_tree_slp_vectorize) Optimization EnabledBy(ftree-vectorize)
Enable basic block vectorization (SLP) on trees.
fvect-cost-model=
Does nothing. Preserved for backward compatibility.
ftree-scev-cprop
-Common Report Var(flag_tree_scev_cprop) Init(1) Optimization
+Common Var(flag_tree_scev_cprop) Init(1) Optimization
Enable copy propagation of scalar-evolution information.
; -fverbose-asm causes extra commentary information to be produced in
; -fno-verbose-asm, the default, causes the extra information
; to not be added and is useful when comparing two assembler files.
fverbose-asm
-Common Report Var(flag_verbose_asm)
+Common Var(flag_verbose_asm)
Add extra commentary to assembler output.
fvisibility=
Output vtable verification pointer sets information.
fvpt
-Common Report Var(flag_value_profile_transformations) Optimization
+Common Var(flag_value_profile_transformations) Optimization
Use expression value profiles in optimizations.
fweb
-Common Report Var(flag_web) Init(2) Optimization
+Common Var(flag_web) Init(2) Optimization
Construct webs and split unrelated uses of single variable.
ftree-builtin-call-dce
-Common Report Var(flag_tree_builtin_call_dce) Init(0) Optimization
+Common Var(flag_tree_builtin_call_dce) Init(0) Optimization
Enable conditional dead code elimination for builtin calls.
fwhole-program
-Common Report Var(flag_whole_program) Init(0)
+Common Var(flag_whole_program) Init(0)
Perform whole program optimizations.
fwrapv-pointer
-Common Report Var(flag_wrapv_pointer) Optimization
+Common Var(flag_wrapv_pointer) Optimization
Assume pointer overflow wraps around.
fwrapv
-Common Report Var(flag_wrapv) Optimization
+Common Var(flag_wrapv) Optimization
Assume signed arithmetic overflow wraps around.
fzero-initialized-in-bss
-Common Report Var(flag_zero_initialized_in_bss) Init(1)
+Common Var(flag_zero_initialized_in_bss) Init(1)
Put zero initialized data in the bss section.
fzero-call-used-regs=
-Common Report RejectNegative Joined
+Common RejectNegative Joined
Clear call-used registers upon function return.
g
Emit progressive recommended breakpoint locations.
gstrict-dwarf
-Common Driver Report Var(dwarf_strict) Init(0)
+Common Driver Var(dwarf_strict) Init(0)
Don't emit DWARF additions beyond selected version.
gdescribe-dies
-Common Driver Report Var(flag_describe_dies) Init(0)
+Common Driver Var(flag_describe_dies) Init(0)
Add description attributes to some DWARF DIEs that have no name attribute.
gtoggle
-Common Driver Report Var(flag_gtoggle)
+Common Driver Var(flag_gtoggle)
Toggle debug information generation.
gvariable-location-views
Driver Joined Separate
fipa-ra
-Common Report Var(flag_ipa_ra) Optimization
+Common Var(flag_ipa_ra) Optimization
Use caller save register across calls if possible.
; This comment is to ensure we retain the blank line above.
Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE)
mbig-endian
-Target Report RejectNegative Mask(BIG_END)
+Target RejectNegative Mask(BIG_END)
Assume target CPU is configured as big endian.
mgeneral-regs-only
-Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
+Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
Generate code which uses only the general registers.
mharden-sls=
Generate code to mitigate against straight line speculation.
mfix-cortex-a53-835769
-Target Report Var(aarch64_fix_a53_err835769) Init(2) Save
+Target Var(aarch64_fix_a53_err835769) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 835769.
mfix-cortex-a53-843419
-Target Report Var(aarch64_fix_a53_err843419) Init(2) Save
+Target Var(aarch64_fix_a53_err843419) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 843419.
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_END)
+Target RejectNegative InverseMask(BIG_END)
Assume target CPU is configured as little endian.
mcmodel=
Specify the code model.
mstrict-align
-Target Report Mask(STRICT_ALIGN) Save
+Target Mask(STRICT_ALIGN) Save
Don't assume that unaligned accesses are handled by the system.
momit-leaf-frame-pointer
-Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save
+Target Var(flag_omit_leaf_frame_pointer) Init(2) Save
Omit the frame pointer in leaf functions.
mtls-dialect=
Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
mpc-relative-literal-loads
-Target Report Save Var(pcrelative_literal_loads) Init(2) Save
+Target Save Var(pcrelative_literal_loads) Init(2) Save
PC relative literal loads.
mbranch-protection=
long aarch64_stack_protector_guard_offset = 0
moutline-atomics
-Target Report Var(aarch64_flag_outline_atomics) Init(2) Save
+Target Var(aarch64_flag_outline_atomics) Init(2) Save
Generate local calls to out-of-line atomic operations.
-param=aarch64-sve-compare-costs=
; <http://www.gnu.org/licenses/>.
msoft-float
-Target Report Mask(SOFT_FP)
+Target Mask(SOFT_FP)
Do not use hardware fp.
mfp-regs
-Target Report Mask(FPREGS)
+Target Mask(FPREGS)
Use fp registers.
mgas
Request IEEE-conformant math library routines (OSF/1).
mieee
-Target Report RejectNegative Mask(IEEE)
+Target RejectNegative Mask(IEEE)
Emit IEEE-conformant code, without inexact exceptions.
mieee-with-inexact
-Target Report RejectNegative Mask(IEEE_WITH_INEXACT)
+Target RejectNegative Mask(IEEE_WITH_INEXACT)
mbuild-constants
-Target Report Mask(BUILD_CONSTANTS)
+Target Mask(BUILD_CONSTANTS)
Do not emit complex integer constants to read-only memory.
mfloat-vax
-Target Report RejectNegative Mask(FLOAT_VAX)
+Target RejectNegative Mask(FLOAT_VAX)
Use VAX fp.
mfloat-ieee
-Target Report RejectNegative InverseMask(FLOAT_VAX)
+Target RejectNegative InverseMask(FLOAT_VAX)
Do not use VAX fp.
mbwx
-Target Report Mask(BWX)
+Target Mask(BWX)
Emit code for the byte/word ISA extension.
mmax
-Target Report Mask(MAX)
+Target Mask(MAX)
Emit code for the motion video ISA extension.
mfix
-Target Report Mask(FIX)
+Target Mask(FIX)
Emit code for the fp move and sqrt ISA extension.
mcix
-Target Report Mask(CIX)
+Target Mask(CIX)
Emit code for the counting ISA extension.
mexplicit-relocs
-Target Report Mask(EXPLICIT_RELOCS)
+Target Mask(EXPLICIT_RELOCS)
Emit code using explicit relocation directives.
msmall-data
-Target Report RejectNegative Mask(SMALL_DATA)
+Target RejectNegative Mask(SMALL_DATA)
Emit 16-bit relocations to the small data areas.
mlarge-data
-Target Report RejectNegative InverseMask(SMALL_DATA)
+Target RejectNegative InverseMask(SMALL_DATA)
Emit 32-bit relocations to the small data areas.
msmall-text
-Target Report RejectNegative Mask(SMALL_TEXT)
+Target RejectNegative Mask(SMALL_TEXT)
Emit direct branches to local functions.
mlarge-text
-Target Report RejectNegative InverseMask(SMALL_TEXT)
+Target RejectNegative InverseMask(SMALL_TEXT)
Emit indirect branches to local functions.
mtls-kernel
-Target Report Mask(TLS_KERNEL)
+Target Mask(TLS_KERNEL)
Emit rdval instead of rduniq for thread pointer.
mlong-double-128
-Target Report RejectNegative Mask(LONG_DOUBLE_128)
+Target RejectNegative Mask(LONG_DOUBLE_128)
Use 128-bit long double.
mlong-double-64
-Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
+Target RejectNegative InverseMask(LONG_DOUBLE_128)
Use 64-bit long double.
mcpu=
config/arc/arc-opts.h
mbig-endian
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Compile code for big endian mode.
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Compile code for little endian mode. This is the default.
mno-cond-exec
-Target Report RejectNegative Mask(NO_COND_EXEC)
+Target RejectNegative Mask(NO_COND_EXEC)
Disable ARCompact specific pass to generate conditional execution instructions.
mA6
-Target Report
+Target
Generate ARCompact 32-bit code for ARC600 processor.
mARC600
-Target Report
+Target
Same as -mA6.
mARC601
-Target Report
+Target
Generate ARCompact 32-bit code for ARC601 processor.
mA7
-Target Report
+Target
Generate ARCompact 32-bit code for ARC700 processor.
mARC700
-Target Report
+Target
Same as -mA7.
mjli-always
-Target Report Mask(JLI_ALWAYS)
+Target Mask(JLI_ALWAYS)
Force all calls to be made via a jli instruction.
mmpy-option=
Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
mdiv-rem
-Target Report Mask(DIVREM)
+Target Mask(DIVREM)
Enable DIV-REM instructions for ARCv2.
mcode-density
-Target Report Mask(CODE_DENSITY)
+Target Mask(CODE_DENSITY)
Enable code density instructions for ARCv2.
mmixed-code
-Target Report Mask(MIXED_CODE_SET)
+Target Mask(MIXED_CODE_SET)
Tweak register allocation to help 16-bit instruction generation.
; originally this was:
;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
; We use an explict definition for the negative form because that is the
; actually interesting option, and we want that to have its own comment.
mvolatile-cache
-Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
+Target RejectNegative Mask(VOLATILE_CACHE_SET)
Use ordinarily cached memory accesses for volatile references.
mno-volatile-cache
-Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
+Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
Enable cache bypass for volatile references.
mbarrel-shifter
-Target Report Mask(BARREL_SHIFTER)
+Target Mask(BARREL_SHIFTER)
Generate instructions supported by barrel shifter.
mnorm
-Target Report Mask(NORM_SET)
+Target Mask(NORM_SET)
Generate norm instruction.
mswap
-Target Report Mask(SWAP_SET)
+Target Mask(SWAP_SET)
Generate swap instruction.
mmul64
-Target Report Mask(MUL64_SET)
+Target Mask(MUL64_SET)
Generate mul64 and mulu64 instructions.
mno-mpy
-Target Report Mask(NOMPY_SET) Warn(%qs is deprecated)
+Target Mask(NOMPY_SET) Warn(%qs is deprecated)
Do not generate mpy instructions for ARC700.
mea
-Target Report Mask(EA_SET)
+Target Mask(EA_SET)
Generate extended arithmetic instructions, only valid for ARC700.
msoft-float
-Target Report Mask(0)
+Target Mask(0)
Dummy flag. This is the default unless FPX switches are provided explicitly.
mlong-calls
-Target Report Mask(LONG_CALLS_SET)
+Target Mask(LONG_CALLS_SET)
Generate call insns as register indirect calls.
mno-brcc
-Target Report Mask(NO_BRCC_SET)
+Target Mask(NO_BRCC_SET)
Do no generate BRcc instructions in arc_reorg.
msdata
-Target Report InverseMask(NO_SDATA_SET)
+Target InverseMask(NO_SDATA_SET)
Generate sdata references. This is the default, unless you compile for PIC.
mmillicode
-Target Report Mask(MILLICODE_THUNK_SET)
+Target Mask(MILLICODE_THUNK_SET)
Generate millicode thunks.
mspfp
-Target Report Mask(SPFP_COMPACT_SET)
+Target Mask(SPFP_COMPACT_SET)
FPX: Generate Single Precision FPX (compact) instructions.
mspfp-compact
-Target Report Mask(SPFP_COMPACT_SET) MaskExists
+Target Mask(SPFP_COMPACT_SET) MaskExists
FPX: Generate Single Precision FPX (compact) instructions.
mspfp-fast
-Target Report Mask(SPFP_FAST_SET)
+Target Mask(SPFP_FAST_SET)
FPX: Generate Single Precision FPX (fast) instructions.
margonaut
-Target Report Mask(ARGONAUT_SET)
+Target Mask(ARGONAUT_SET)
FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
mdpfp
-Target Report Mask(DPFP_COMPACT_SET)
+Target Mask(DPFP_COMPACT_SET)
FPX: Generate Double Precision FPX (compact) instructions.
mdpfp-compact
-Target Report Mask(DPFP_COMPACT_SET) MaskExists
+Target Mask(DPFP_COMPACT_SET) MaskExists
FPX: Generate Double Precision FPX (compact) instructions.
mdpfp-fast
-Target Report Mask(DPFP_FAST_SET)
+Target Mask(DPFP_FAST_SET)
FPX: Generate Double Precision FPX (fast) instructions.
mno-dpfp-lrsr
-Target Report Mask(DPFP_DISABLE_LRSR)
+Target Mask(DPFP_DISABLE_LRSR)
Disable LR and SR instructions from using FPX extension aux registers.
msimd
-Target Report Mask(SIMD_SET)
+Target Mask(SIMD_SET)
Enable generation of ARC SIMD instructions via target-specific builtins.
mcpu=
Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
misize
-Target Report PchIgnore Var(TARGET_DUMPISIZE)
+Target PchIgnore Var(TARGET_DUMPISIZE)
Annotate assembler instructions with estimated addresses.
mmultcost=
Enable the use of pre/post modify with register displacement.
mmul32x16
-Target Report Mask(MULMAC_32BY16_SET)
+Target Mask(MULMAC_32BY16_SET)
Generate 32x16 multiply and mac instructions.
; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
; Flags used by the assembler, but for which we define preprocessor
; macro symbols as well.
mcrc
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable variable polynomial CRC extension.
mdsp-packa
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable DSP 3.1 Pack A extensions.
mdvbf
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable dual viterbi butterfly extension.
mmac-d16
-Target Report Undocumented Warn(%qs is deprecated)
+Target Undocumented Warn(%qs is deprecated)
mmac-24
-Target Report Undocumented Warn(%qs is deprecated)
+Target Undocumented Warn(%qs is deprecated)
mtelephony
-Target Report RejectNegative Warn(%qs is deprecated)
+Target RejectNegative Warn(%qs is deprecated)
Enable Dual and Single Operand Instructions for Telephony.
mxy
-Target Report
+Target
Enable XY Memory extension (DSP version 3).
; ARC700 4.10 extension instructions
mlock
-Target Report
+Target
Enable Locked Load/Store Conditional extension.
mswape
-Target Report
+Target
Enable swap byte ordering extension instruction.
mrtsc
-Target Report Warn(%qs is deprecated)
+Target Warn(%qs is deprecated)
Enable 64-bit Time-Stamp Counter extension instruction.
EB
;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
mlra
-Target Report Var(arc_lra_flag) Init(1) Save
+Target Var(arc_lra_flag) Init(1) Save
Use LRA instead of reload.
mlra-priority-none
Target RejectNegative Joined
matomic
-Target Report Mask(ATOMIC)
+Target Mask(ATOMIC)
Enable atomic instructions.
mll64
-Target Report Mask(LL64)
+Target Mask(LL64)
Enable double load/store instructions for ARC HS.
mfpu=
Target RejectNegative Var(arc_tp_regno,-1)
mbitops
-Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
+Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
Enable use of NPS400 bit operations.
mcmem
-Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
+Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
Enable use of NPS400 xld/xst extension.
munaligned-access
-Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
+Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
Enable unaligned word and halfword accesses to packed data.
mirq-ctrl-saved=
Enum(arc_lpc) String(32) Value(32)
mrf16
-Target Report Mask(RF16)
+Target Mask(RF16)
Enable 16-entry register file.
mbranch-index
-Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
+Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
Enable use of BI/BIH instructions when available.
mcode-density-frame
-Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
+Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
Enable ENTER_S and LEAVE_S opcodes for ARCv2.
Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX)
mabort-on-noreturn
-Target Report Mask(ABORT_NORETURN)
+Target Mask(ABORT_NORETURN)
Generate a call to abort if a noreturn function returns.
mapcs
Target RejectNegative Mask(APCS_FRAME) Undocumented
mapcs-frame
-Target Report Mask(APCS_FRAME)
+Target Mask(APCS_FRAME)
Generate APCS conformant stack frames.
mapcs-reentrant
-Target Report Mask(APCS_REENT)
+Target Mask(APCS_REENT)
Generate re-entrant, PIC code.
mapcs-stack-check
-Target Report Mask(APCS_STACK) Undocumented
+Target Mask(APCS_STACK) Undocumented
march=
Target Save RejectNegative Negative(march=) ToLower Joined Var(arm_arch_string)
Enum(arm_arch) String(native) Value(-1) DriverOnly
marm
-Target Report RejectNegative Negative(mthumb) InverseMask(THUMB)
+Target RejectNegative Negative(mthumb) InverseMask(THUMB)
Generate code in 32 bit ARM state.
mbig-endian
-Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END)
+Target RejectNegative Negative(mlittle-endian) Mask(BIG_END)
Assume target CPU is configured as big endian.
mcallee-super-interworking
-Target Report Mask(CALLEE_INTERWORKING)
+Target Mask(CALLEE_INTERWORKING)
Thumb: Assume non-static functions may be called from ARM code.
mcaller-super-interworking
-Target Report Mask(CALLER_INTERWORKING)
+Target Mask(CALLER_INTERWORKING)
Thumb: Assume function pointers may go to non-Thumb aware code.
mcpu=
Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD)
mflip-thumb
-Target Report Var(TARGET_FLIP_THUMB) Undocumented
+Target Var(TARGET_FLIP_THUMB) Undocumented
Switch ARM/Thumb modes on alternating functions for compiler testing.
mfp16-format=
Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
mlittle-endian
-Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END)
+Target RejectNegative Negative(mbig-endian) InverseMask(BIG_END)
Assume target CPU is configured as little endian.
mlong-calls
-Target Report Mask(LONG_CALLS)
+Target Mask(LONG_CALLS)
Generate call insns as indirect calls, if necessary.
mpic-data-is-text-relative
-Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
+Target Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
Assume data segments are relative to text segment.
mpic-register=
Specify the register to be used for PIC addressing.
mpoke-function-name
-Target Report Mask(POKE_FUNCTION_NAME)
+Target Mask(POKE_FUNCTION_NAME)
Store function names in object code.
msched-prolog
-Target Report Mask(SCHED_PROLOG)
+Target Mask(SCHED_PROLOG)
Permit scheduling of a function's prologue sequence.
msingle-pic-base
-Target Report Mask(SINGLE_PIC_BASE)
+Target Mask(SINGLE_PIC_BASE)
Do not load the PIC register in function prologues.
msoft-float
Specify the minimum bit alignment of structures. (Deprecated).
mthumb
-Target Report RejectNegative Negative(marm) Mask(THUMB) Save
+Target RejectNegative Negative(marm) Mask(THUMB) Save
Generate code for Thumb state.
mthumb-interwork
-Target Report Mask(INTERWORK)
+Target Mask(INTERWORK)
Support calls between Thumb and ARM instruction sets.
mtls-dialect=
Enum(arm_tp_type) String(cp15) Value(TP_CP15)
mtpcs-frame
-Target Report Mask(TPCS_FRAME)
+Target Mask(TPCS_FRAME)
Thumb: Generate (non-leaf) stack frames even if not needed.
mtpcs-leaf-frame
-Target Report Mask(TPCS_LEAF_FRAME)
+Target Mask(TPCS_LEAF_FRAME)
Thumb: Generate (leaf) stack frames even if not needed.
mtune=
Tune code for the given processor.
mprint-tune-info
-Target Report RejectNegative Var(print_tune_info) Init(0)
+Target RejectNegative Var(print_tune_info) Init(0)
Print CPU tuning information as comment in assembler file. This is
an option used only for regression testing of the compiler and not
intended for ordinary use in compiling code.
Enum(processor_type) String(native) Value(-1) DriverOnly
mvectorize-with-neon-quad
-Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE)
+Target RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE)
Use Neon quad-word (rather than double-word) registers for vectorization.
mvectorize-with-neon-double
-Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE)
+Target RejectNegative Mask(NEON_VECTORIZE_DOUBLE)
Use Neon double-word (rather than quad-word) registers for vectorization.
mverbose-cost-dump
Enable more verbose RTX cost dumps during debug. For GCC developers use only.
mword-relocations
-Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
+Target Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
Only generate absolute relocations on word sized values.
mrestrict-it
-Target Report Var(arm_restrict_it) Init(2) Save
+Target Var(arm_restrict_it) Init(2) Save
Generate IT blocks appropriate for ARMv8.
mfix-cortex-m3-ldrd
-Target Report Var(fix_cm3_ldrd) Init(2)
+Target Var(fix_cm3_ldrd) Init(2)
Avoid overlapping destination and address registers on LDRD instructions
that may trigger Cortex-M3 errata.
munaligned-access
-Target Report Var(unaligned_access) Init(2) Save
+Target Var(unaligned_access) Init(2) Save
Enable unaligned word and halfword accesses to packed data.
mneon-for-64bits
This option is deprecated and has no effect.
mslow-flash-data
-Target Report Var(target_slow_flash_data) Init(0)
+Target Var(target_slow_flash_data) Init(0)
Assume loading data from flash is slower than fetching instructions.
masm-syntax-unified
-Target Report Var(inline_asm_unified) Init(0) Save
+Target Var(inline_asm_unified) Init(0) Save
Assume unified syntax for inline assembly code.
mpure-code
-Target Report Var(target_pure_code) Init(0)
+Target Var(target_pure_code) Init(0)
Do not allow constant data to be placed in code sections.
mbe8
-Target Report RejectNegative Negative(mbe32) Mask(BE8)
+Target RejectNegative Negative(mbe32) Mask(BE8)
When linking for big-endian targets, generate a BE8 format image.
mbe32
-Target Report RejectNegative Negative(mbe8) InverseMask(BE8)
+Target RejectNegative Negative(mbe8) InverseMask(BE8)
When linking for big-endian targets, generate a legacy BE32 format image.
mbranch-cost=
Cost to assume for a branch insn.
mgeneral-regs-only
-Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
+Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
Generate code which uses the core registers only (r0-r14).
mfdpic
-Target Report Mask(FDPIC)
+Target Mask(FDPIC)
Enable Function Descriptor PIC mode.
; <http://www.gnu.org/licenses/>.
mcall-prologues
-Target Report Mask(CALL_PROLOGUES)
+Target Mask(CALL_PROLOGUES)
Use subroutines for function prologues and epilogues.
mmcu=
-mmcu=MCU Select the target MCU.
mgas-isr-prologues
-Target Report Var(avr_gasisr_prologues) UInteger Init(0)
+Target Var(avr_gasisr_prologues) UInteger Init(0)
Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues.
mn-flash=
Set the number of 64 KiB flash segments.
mskip-bug
-Target Report Mask(SKIP_BUG)
+Target Mask(SKIP_BUG)
Indicate presence of a processor erratum.
mrmw
-Target Report Mask(RMW)
+Target Mask(RMW)
Enable Read-Modify-Write (RMW) instructions support/use.
mdeb
-Target Report Undocumented Mask(ALL_DEBUG)
+Target Undocumented Mask(ALL_DEBUG)
mlog=
Target RejectNegative Joined Undocumented Var(avr_log_details)
mshort-calls
-Target Report RejectNegative Mask(SHORT_CALLS)
+Target RejectNegative Mask(SHORT_CALLS)
Use RJMP / RCALL even though CALL / JMP are available.
mint8
-Target Report Mask(INT8)
+Target Mask(INT8)
Use an 8-bit 'int' type.
mno-interrupts
-Target Report RejectNegative Mask(NO_INTERRUPTS)
+Target RejectNegative Mask(NO_INTERRUPTS)
Change the stack pointer without disabling interrupts.
mbranch-cost=
-Target Report Joined RejectNegative UInteger Var(avr_branch_cost) Init(0)
+Target Joined RejectNegative UInteger Var(avr_branch_cost) Init(0)
Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 0.
mmain-is-OS_task
-Target Report Mask(MAIN_IS_OS_TASK)
+Target Mask(MAIN_IS_OS_TASK)
Treat main as if it had attribute OS_task.
morder1
-Target Report Undocumented Mask(ORDER_1)
+Target Undocumented Mask(ORDER_1)
morder2
-Target Report Undocumented Mask(ORDER_2)
+Target Undocumented Mask(ORDER_2)
mtiny-stack
-Target Report Mask(TINY_STACK)
+Target Mask(TINY_STACK)
Change only the low 8 bits of the stack pointer.
mrelax
-Target Report
+Target
Relax branches.
mpmem-wrap-around
-Target Report
+Target
Make the linker relaxation machine assume that a program counter wrap-around occurs.
maccumulate-args
-Target Report Mask(ACCUMULATE_OUTGOING_ARGS)
+Target Mask(ACCUMULATE_OUTGOING_ARGS)
Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf.
mstrict-X
-Target Report Var(avr_strict_X) Init(0)
+Target Var(avr_strict_X) Init(0)
When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X.
;; For rationale behind -msp8 see explanation in avr.h.
msp8
-Target Report RejectNegative Var(avr_sp8) Init(0)
+Target RejectNegative Var(avr_sp8) Init(0)
The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU.
Waddr-space-convert
-Warning C Report Var(avr_warn_addr_space_convert) Init(0)
+Warning C Var(avr_warn_addr_space_convert) Init(0)
Warn if the address space of an address is changed.
Wmisspelled-isr
-Warning C C++ Report Var(avr_warn_misspelled_isr) Init(1)
+Warning C C++ Var(avr_warn_misspelled_isr) Init(1)
Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default.
mfract-convert-truncate
-Target Report Mask(FRACT_CONV_TRUNC)
+Target Mask(FRACT_CONV_TRUNC)
Allow to use truncation instead of rounding towards zero for fractional fixed-point types.
mabsdata
-Target Report Mask(ABSDATA)
+Target Mask(ABSDATA)
Assume that all data in static storage can be accessed by LDS / STS. This option is only useful for reduced Tiny devices.
mdouble=
-Target Report Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e)
+Target Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e)
-mdouble=<BITS> Use <BITS> bits wide double type.
mlong-double=
-Target Report Joined RejectNegative Var(avr_long_double) Init(0) Enum(avr_bits_e)
+Target Joined RejectNegative Var(avr_long_double) Init(0) Enum(avr_bits_e)
-mlong-double=<BITS> Use <BITS> bits wide long double type.
nodevicelib
-Driver Target Report RejectNegative
+Driver Target RejectNegative
Do not link against the device-specific library lib<MCU>.a.
nodevicespecs
-Driver Target Report RejectNegative
+Driver Target RejectNegative
Do not use the device-specific specs file device-specs/specs-<MCU>.
Enum
Specify the name of the target CPU.
momit-leaf-frame-pointer
-Target Report Mask(OMIT_LEAF_FRAME_POINTER)
+Target Mask(OMIT_LEAF_FRAME_POINTER)
Omit frame pointer for leaf functions.
mlow64k
-Target Report Mask(LOW_64K)
+Target Mask(LOW_64K)
Program is entirely located in low 64k of memory.
mcsync-anomaly
-Target Report Var(bfin_csync_anomaly) Init(-1)
+Target Var(bfin_csync_anomaly) Init(-1)
Work around a hardware anomaly by adding a number of NOPs before a
CSYNC or SSYNC instruction.
mspecld-anomaly
-Target Report Var(bfin_specld_anomaly) Init(-1)
+Target Var(bfin_specld_anomaly) Init(-1)
Avoid speculative loads to work around a hardware anomaly.
mid-shared-library
-Target Report Mask(ID_SHARED_LIBRARY)
+Target Mask(ID_SHARED_LIBRARY)
Enabled ID based shared library.
mleaf-id-shared-library
-Target Report Mask(LEAF_ID_SHARED_LIBRARY)
+Target Mask(LEAF_ID_SHARED_LIBRARY)
Generate code that won't be linked against any other ID shared libraries,
but may be used as a shared library.
ID of shared library to build.
msep-data
-Target Report Mask(SEP_DATA)
+Target Mask(SEP_DATA)
Enable separate data segment.
mlong-calls
-Target Report Mask(LONG_CALLS)
+Target Mask(LONG_CALLS)
Avoid generating pc-relative calls; use indirection.
mfast-fp
-Target Report Mask(FAST_FP)
+Target Mask(FAST_FP)
Link with the fast floating-point library.
mfdpic
-Target Report Mask(FDPIC)
+Target Mask(FDPIC)
Enable Function Descriptor PIC mode.
minline-plt
-Target Report Mask(INLINE_PLT)
+Target Mask(INLINE_PLT)
Enable inlining of PLT in function calls.
mstack-check-l1
-Target Report Mask(STACK_CHECK_L1)
+Target Mask(STACK_CHECK_L1)
Do stack checking using bounds in L1 scratch memory.
mmulticore
-Target Report Mask(MULTICORE)
+Target Mask(MULTICORE)
Enable multicore support.
mcorea
-Target Report Mask(COREA)
+Target Mask(COREA)
Build for Core A.
mcoreb
-Target Report Mask(COREB)
+Target Mask(COREB)
Build for Core B.
msdram
-Target Report Mask(SDRAM)
+Target Mask(SDRAM)
Build for SDRAM.
micplb
-Target Report Mask(ICPLB)
+Target Mask(ICPLB)
Assume ICPLBs are enabled at runtime.
; Use xBPF extensions.
mxbpf
-Target Report Mask(XBPF)
+Target Mask(XBPF)
Generate xBPF.
; Selecting big endian or little endian targets.
mbig-endian
-Target RejectNegative Report Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Generate big-endian eBPF.
mlittle-endian
-Target RejectNegative Report InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Generate little-endian eBPF.
mframe-limit=
config/c6x/c6x-opts.h
mbig-endian
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order.
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
Use little-endian byte order.
msim
Compile for the DSBT shared library ABI.
mlong-calls
-Target Report Mask(LONG_CALLS)
+Target Mask(LONG_CALLS)
Avoid generating pc-relative calls; use indirection.
march=
Use simulator runtime.
mbit-ops
-Target Report Mask(BIT_OPS)
+Target Mask(BIT_OPS)
Generate SBIT, CBIT instructions.
mmac
-Target Report Mask(MAC)
+Target Mask(MAC)
Support multiply accumulate instructions.
mdebug-addr
; driver-like program that gets a mapping of I/O registers (all
; on the same page, including the TLB registers).
mmul-bug-workaround
-Target Report Mask(MUL_BUG)
+Target Mask(MUL_BUG)
Work around bug in multiplication instruction.
; TARGET_ETRAX4_ADD: Instruction-set additions from Etrax 4 and up.
; (Just "lz".)
metrax4
-Target Report Mask(ETRAX4_ADD)
+Target Mask(ETRAX4_ADD)
Compile for ETRAX 4 (CRIS v3).
; See cris_handle_option.
metrax100
-Target Report RejectNegative
+Target RejectNegative
Compile for ETRAX 100 (CRIS v8).
; See cris_handle_option.
mno-etrax100
-Target Report RejectNegative Undocumented
+Target RejectNegative Undocumented
mpdebug
-Target Report Mask(PDEBUG)
+Target Mask(PDEBUG)
Emit verbose debug information in assembly code.
; TARGET_CCINIT: Whether to use condition-codes generated by
; insns other than the immediately preceding compare/test insn.
; Used to check for errors in notice_update_cc.
mcc-init
-Target Report Mask(CCINIT)
+Target Mask(CCINIT)
Do not use condition codes from normal instructions.
; TARGET_SIDE_EFFECT_PREFIXES: Whether to use side-effect
; patterns. Used to debug the [rx=ry+i] type patterns.
mside-effects
-Target Report RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented
+Target RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented
mno-side-effects
-Target Report RejectNegative InverseMask(SIDE_EFFECT_PREFIXES)
+Target RejectNegative InverseMask(SIDE_EFFECT_PREFIXES)
Do not emit addressing modes with side-effect assignment.
; TARGET_STACK_ALIGN: Whether to *keep* (not force) alignment of
; stack at 16 (or 32, depending on TARGET_ALIGN_BY_32) bits.
mstack-align
-Target Report RejectNegative Mask(STACK_ALIGN) Undocumented
+Target RejectNegative Mask(STACK_ALIGN) Undocumented
mno-stack-align
-Target Report RejectNegative InverseMask(STACK_ALIGN)
+Target RejectNegative InverseMask(STACK_ALIGN)
Do not tune stack alignment.
; TARGET_DATA_ALIGN: Whether to do alignment on individual
; modifiable objects.
mdata-align
-Target Report RejectNegative Mask(DATA_ALIGN) Undocumented
+Target RejectNegative Mask(DATA_ALIGN) Undocumented
mno-data-align
-Target Report RejectNegative InverseMask(DATA_ALIGN)
+Target RejectNegative InverseMask(DATA_ALIGN)
Do not tune writable data alignment.
; TARGET_CONST_ALIGN: Whether to do alignment on individual
; non-modifiable objects.
mconst-align
-Target Report RejectNegative Mask(CONST_ALIGN) Undocumented
+Target RejectNegative Mask(CONST_ALIGN) Undocumented
mno-const-align
-Target Report RejectNegative InverseMask(CONST_ALIGN)
+Target RejectNegative InverseMask(CONST_ALIGN)
Do not tune code and read-only data alignment.
; See cris_handle_option.
m32-bit
-Target Report RejectNegative Undocumented
+Target RejectNegative Undocumented
; See cris_handle_option.
m32bit
-Target Report RejectNegative
+Target RejectNegative
Align code and data to 32 bits.
; See cris_handle_option.
m16-bit
-Target Report RejectNegative Undocumented
+Target RejectNegative Undocumented
; See cris_handle_option.
m16bit
-Target Report RejectNegative Undocumented
+Target RejectNegative Undocumented
; See cris_handle_option.
m8-bit
-Target Report RejectNegative Undocumented
+Target RejectNegative Undocumented
; See cris_handle_option.
m8bit
-Target Report RejectNegative
+Target RejectNegative
Don't align items in code or data.
; TARGET_PROLOGUE_EPILOGUE: Whether or not to omit function
; prologue and epilogue.
mprologue-epilogue
-Target Report RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented
+Target RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented
mno-prologue-epilogue
-Target Report RejectNegative InverseMask(PROLOGUE_EPILOGUE)
+Target RejectNegative InverseMask(PROLOGUE_EPILOGUE)
Do not emit function prologue or epilogue.
; We have to handle this m-option here since we can't wash it
; off in both CC1_SPEC and CC1PLUS_SPEC.
mbest-lib-options
-Target Report RejectNegative
+Target RejectNegative
Use the most feature-enabling options allowed by other options.
; FIXME: The following comment relates to gcc before cris.opt.
; gcc.c to forget it, if there's a "later" -mbest-lib-options.
; Kludgy, but needed for some multilibbed files.
moverride-best-lib-options
-Target Report RejectNegative
+Target RejectNegative
Override -mbest-lib-options.
mcpu=
-Target Report RejectNegative Joined Undocumented Var(cris_cpu_str)
+Target RejectNegative Joined Undocumented Var(cris_cpu_str)
march=
-Target Report RejectNegative Joined Var(cris_cpu_str)
+Target RejectNegative Joined Var(cris_cpu_str)
-march=ARCH Generate code for the specified chip or CPU version.
mtune=
-Target Report RejectNegative Joined Var(cris_tune_str)
+Target RejectNegative Joined Var(cris_tune_str)
-mtune=ARCH Tune alignment for the specified chip or CPU version.
mmax-stackframe=
-Target Report RejectNegative Joined Var(cris_max_stackframe_str)
+Target RejectNegative Joined Var(cris_max_stackframe_str)
-mmax-stackframe=SIZE Warn when a stackframe is larger than the specified size.
max-stackframe=
-Target Report RejectNegative Joined Undocumented Var(cris_max_stackframe_str)
+Target RejectNegative Joined Undocumented Var(cris_max_stackframe_str)
mtrap-using-break8
-Target Report Var(cris_trap_using_break8) Init(2)
+Target Var(cris_trap_using_break8) Init(2)
Emit traps as \"break 8\", default for CRIS v3 and up. If disabled, calls to abort() are used.
mtrap-unaligned-atomic
-Target Report Var(cris_trap_unaligned_atomic) Init(2)
+Target Var(cris_trap_unaligned_atomic) Init(2)
Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory.
munaligned-atomic-may-use-library
-Target Report Var(cris_atomics_calling_libfunc) Init(2)
+Target Var(cris_atomics_calling_libfunc) Init(2)
Handle atomic builtins that may be applied to unaligned data by calling library functions. Overrides -mtrap-unaligned-atomic.
; TARGET_SVINTO: Currently this just affects alignment. FIXME:
; <http://www.gnu.org/licenses/>.
melf
-Target Report RejectNegative Undocumented
+Target RejectNegative Undocumented
sim
Driver JoinedOrMissing
; For backward compatibility only.
march=ck803s
-Target Report Var(flag_arch_ck803s) Undocumented
+Target Var(flag_arch_ck803s) Undocumented
march=
Target RejectNegative ToLower Joined Enum(csky_arch) Var(csky_arch_option) Save
;; Endianness options.
mbig-endian
-Target RejectNegative Report Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Generate big-endian code.
EB
-Target RejectNegative Report Alias(mbig-endian) Undocumented
+Target RejectNegative Alias(mbig-endian) Undocumented
mlittle-endian
-Target RejectNegative Report InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Generate little-endian code.
EL
-Target RejectNegative Report Alias(mlittle-endian) Undocumented
+Target RejectNegative Alias(mlittle-endian) Undocumented
;; Floating point options. These affect code generation but not
;; assembly.
Specify the target floating-point hardware/format.
mdouble-float
-Target Report Var(TARGET_DOUBLE_FLOAT) Init(-1)
+Target Var(TARGET_DOUBLE_FLOAT) Init(-1)
Generate C-SKY FPU double float instructions (default for hard float).
mfdivdu
-Target Report Var(TARGET_FDIVDU) Init(-1)
+Target Var(TARGET_FDIVDU) Init(-1)
Generate frecipd/fsqrtd/fdivd instructions (default for hard float).
;; Instruction set extensions. Most of these don't affect code
;; There are builtin preprocessor defines for each of these.
melrw
-Target Report Var(TARGET_ELRW) Init(-1)
+Target Var(TARGET_ELRW) Init(-1)
Enable the extended LRW instruction (default for CK801).
mistack
-Target Report Mask(ISTACK)
+Target Mask(ISTACK)
Enable interrupt stack instructions.
mmp
-Target Report RejectNegative Mask(MP)
+Target RejectNegative Mask(MP)
Enable multiprocessor instructions.
mcp
-Target Report RejectNegative Mask(CP)
+Target RejectNegative Mask(CP)
Enable coprocessor instructions.
mcache
-Target Report RejectNegative Mask(CACHE)
+Target RejectNegative Mask(CACHE)
Enable cache prefetch instructions.
msecurity
-Target Report RejectNegative Mask(SECURITY)
+Target RejectNegative Mask(SECURITY)
Enable C-SKY SECURE instructions.
mmac
-Target Report RejectNegative Alias(msecurity) Undocumented
+Target RejectNegative Alias(msecurity) Undocumented
mtrust
-Target Report RejectNegative Mask(TRUST)
+Target RejectNegative Mask(TRUST)
Enable C-SKY TRUST instructions.
mdsp
-Target Report RejectNegative Var(TARGET_DSP)
+Target RejectNegative Var(TARGET_DSP)
Enable C-SKY DSP instructions.
medsp
-Target Report RejectNegative Mask(EDSP)
+Target RejectNegative Mask(EDSP)
Enable C-SKY Enhanced DSP instructions.
mvdsp
-Target Report RejectNegative Mask(VDSP)
+Target RejectNegative Mask(VDSP)
Enable C-SKY Vector DSP instructions.
;; Code generation options not passed to the assembler.
mdiv
-Target Report Var(TARGET_DIV) Init(-1)
+Target Var(TARGET_DIV) Init(-1)
Generate divide instructions.
msmart
-Target Report Var(TARGET_MINI_REGISTERS) Init(-1)
+Target Var(TARGET_MINI_REGISTERS) Init(-1)
Generate code for Smart Mode.
mhigh-registers
-Target Report Var(TARGET_HIGH_REGISTERS) Init(-1)
+Target Var(TARGET_HIGH_REGISTERS) Init(-1)
Enable use of R16-R31 (default).
manchor
-Target Report Var(TARGET_ANCHOR)
+Target Var(TARGET_ANCHOR)
Generate code using global anchor symbol addresses.
mpushpop
-Target Report Var(TARGET_PUSHPOP) Init(1)
+Target Var(TARGET_PUSHPOP) Init(1)
Generate push/pop instructions (default).
mmultiple-stld
-Target Report Var(TARGET_MULTIPLE_STLD) Init(-1)
+Target Var(TARGET_MULTIPLE_STLD) Init(-1)
Generate stm/ldm instructions (default).
mstm
-Target Report Alias(mmultiple-stld) Undocumented
+Target Alias(mmultiple-stld) Undocumented
mconstpool
-Target Report Var(TARGET_CONSTANT_POOL) Init(-1)
+Target Var(TARGET_CONSTANT_POOL) Init(-1)
Generate constant pools in the compiler instead of assembler.
mstack-size
-Target Report Var(TARGET_STACK_SIZE) Init(0)
+Target Var(TARGET_STACK_SIZE) Init(0)
Emit .stack_size directives.
mccrt
-Target Report Var(TARGET_LIBCCRT) Init(0)
+Target Var(TARGET_LIBCCRT) Init(0)
Generate code for C-SKY compiler runtime instead of libgcc.
mbranch-cost=
-Target Report Joined RejectNegative UInteger Var(csky_branch_cost) Init(1)
+Target Joined RejectNegative UInteger Var(csky_branch_cost) Init(1)
Set the branch costs to roughly the specified number of instructions.
msched-prolog
-Target Report Var(flag_sched_prolog) Init(0)
+Target Var(flag_sched_prolog) Init(0)
Permit scheduling of function prologue and epilogue sequences.
msim
C ObjC C++ ObjC++ Separate Alias(MF) MissingArgError(missing filename after %qs)
fapple-kext
-Target Report C++ Var(flag_apple_kext)
+Target C++ Var(flag_apple_kext)
Generate code for darwin loadable kernel extensions.
iframework
-iframework <dir> Add <dir> to the end of the system framework include path.
mconstant-cfstrings
-Target Report Var(darwin_constant_cfstrings) Init(1)
+Target Var(darwin_constant_cfstrings) Init(1)
Generate compile-time CFString objects.
Wnonportable-cfstrings
-Target Report Var(darwin_warn_nonportable_cfstrings) Init(1) Warning
+Target Var(darwin_warn_nonportable_cfstrings) Init(1) Warning
Warn if constant CFString objects contain non-portable characters.
; Use new-style pic stubs if this is true, x86 only so far.
matt-stubs
-Target Report Var(darwin_macho_att_stub) Init(1)
+Target Var(darwin_macho_att_stub) Init(1)
Generate AT&T-style stubs for Mach-O.
mdynamic-no-pic
-Target Common Report Mask(MACHO_DYNAMIC_NO_PIC)
+Target Common Mask(MACHO_DYNAMIC_NO_PIC)
Generate code suitable for executables (NOT shared libs).
mfix-and-continue
-Target Report Var(darwin_fix_and_continue)
+Target Var(darwin_fix_and_continue)
Generate code suitable for fast turn around debugging.
mkernel
-Target Report Var(flag_mkernel)
+Target Var(flag_mkernel)
Generate code for the kernel or loadable kernel extensions.
; The Init here is for the convenience of GCC developers, so that cc1
; driver will always pass a -mmacosx-version-min, so in normal use the
; Init is never used.
mmacosx-version-min=
-Target RejectNegative Joined Report Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION)
+Target RejectNegative Joined Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION)
The earliest macOS version on which this program will run.
; Really, only relevant to PowerPC which has a 4 byte bool by default.
mone-byte-bool
-Target RejectNegative Report Var(darwin_one_byte_bool)
+Target RejectNegative Var(darwin_one_byte_bool)
Set sizeof(bool) to 1.
msymbol-stubs
-Target Report Var(darwin_symbol_stubs) Init(0)
+Target Var(darwin_symbol_stubs) Init(0)
Force generation of external symbol indirection stubs.
; Some code-gen may be improved / adjusted if the linker is sufficiently modern.
mtarget-linker=
-Target RejectNegative Joined Report Alias(mtarget-linker)
+Target RejectNegative Joined Alias(mtarget-linker)
mtarget-linker
-Target RejectNegative Joined Separate Report Var(darwin_target_linker) Init(LD64_VERSION)
+Target RejectNegative Joined Separate Var(darwin_target_linker) Init(LD64_VERSION)
-mtarget-linker <version> Specify that ld64 <version> is the toolchain linker for the current invocation.
; Driver options.
; <http://www.gnu.org/licenses/>.
msmall-model
-Target Report Mask(SMALL_MODEL)
+Target Mask(SMALL_MODEL)
Assume small address space.
mno-lsim
frv_cpu_t frv_cpu_type = CPU_TYPE
macc-4
-Target Report RejectNegative Mask(ACC_4)
+Target RejectNegative Mask(ACC_4)
Use 4 media accumulators.
macc-8
-Target Report RejectNegative InverseMask(ACC_4, ACC_8)
+Target RejectNegative InverseMask(ACC_4, ACC_8)
Use 8 media accumulators.
malign-labels
-Target Report Mask(ALIGN_LABELS)
+Target Mask(ALIGN_LABELS)
Enable label alignment optimizations.
malloc-cc
-Target Report RejectNegative Mask(ALLOC_CC)
+Target RejectNegative Mask(ALLOC_CC)
Dynamically allocate cc registers.
; We used to default the branch cost to 2, but it was changed it to 1 to avoid
Set the cost of branches.
mcond-exec
-Target Report Mask(COND_EXEC)
+Target Mask(COND_EXEC)
Enable conditional execution other than moves/scc.
mcond-exec-insns=
Change the number of temporary registers that are available to conditionally-executed sequences.
mcond-move
-Target Report Mask(COND_MOVE)
+Target Mask(COND_MOVE)
Enable conditional moves.
mcpu=
Target Undocumented Var(TARGET_DEBUG_STACK)
mdouble
-Target Report Mask(DOUBLE)
+Target Mask(DOUBLE)
Use fp double instructions.
mdword
-Target Report Mask(DWORD)
+Target Mask(DWORD)
Change the ABI to allow double word insns.
mfdpic
-Target Report Mask(FDPIC)
+Target Mask(FDPIC)
Enable Function Descriptor PIC mode.
mfixed-cc
-Target Report RejectNegative InverseMask(ALLOC_CC, FIXED_CC)
+Target RejectNegative InverseMask(ALLOC_CC, FIXED_CC)
Just use icc0/fcc0.
mfpr-32
-Target Report RejectNegative Mask(FPR_32)
+Target RejectNegative Mask(FPR_32)
Only use 32 FPRs.
mfpr-64
-Target Report RejectNegative InverseMask(FPR_32, FPR_64)
+Target RejectNegative InverseMask(FPR_32, FPR_64)
Use 64 FPRs.
mgpr-32
-Target Report RejectNegative Mask(GPR_32)
+Target RejectNegative Mask(GPR_32)
Only use 32 GPRs.
mgpr-64
-Target Report RejectNegative InverseMask(GPR_32, GPR_64)
+Target RejectNegative InverseMask(GPR_32, GPR_64)
Use 64 GPRs.
mgprel-ro
-Target Report Mask(GPREL_RO)
+Target Mask(GPREL_RO)
Enable use of GPREL for read-only data in FDPIC.
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
+Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
Use hardware floating point.
minline-plt
-Target Report Mask(INLINE_PLT)
+Target Mask(INLINE_PLT)
Enable inlining of PLT in function calls.
mlibrary-pic
-Target Report Mask(LIBPIC)
+Target Mask(LIBPIC)
Enable PIC support for building libraries.
mlinked-fp
-Target Report Mask(LINKED_FP)
+Target Mask(LINKED_FP)
Follow the EABI linkage requirements.
mlong-calls
-Target Report Mask(LONG_CALLS)
+Target Mask(LONG_CALLS)
Disallow direct calls to global functions.
mmedia
-Target Report Mask(MEDIA)
+Target Mask(MEDIA)
Use media instructions.
mmuladd
-Target Report Mask(MULADD)
+Target Mask(MULADD)
Use multiply add/subtract instructions.
mmulti-cond-exec
-Target Report Mask(MULTI_CE)
+Target Mask(MULTI_CE)
Enable optimizing &&/|| in conditional execution.
mnested-cond-exec
-Target Report Mask(NESTED_CE)
+Target Mask(NESTED_CE)
Enable nested conditional execution optimizations.
; Not used by the compiler proper.
Do not mark ABI switches in e_flags.
moptimize-membar
-Target Report Mask(OPTIMIZE_MEMBAR)
+Target Mask(OPTIMIZE_MEMBAR)
Remove redundant membars.
mpack
-Target Report Mask(PACK)
+Target Mask(PACK)
Pack VLIW instructions.
mscc
-Target Report Mask(SCC)
+Target Mask(SCC)
Enable setting GPRs to the result of comparisons.
msched-lookahead=
Change the amount of scheduler lookahead.
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT)
+Target RejectNegative Mask(SOFT_FLOAT)
Use software floating point.
mTLS
-Target Report RejectNegative Mask(BIG_TLS)
+Target RejectNegative Mask(BIG_TLS)
Assume a large TLS segment.
mtls
-Target Report RejectNegative InverseMask(BIG_TLS)
+Target RejectNegative InverseMask(BIG_TLS)
Do not assume a large TLS segment.
; Not used by the compiler proper.
Link with the library-pic libraries.
mvliw-branch
-Target Report Mask(VLIW_BRANCH)
+Target Mask(VLIW_BRANCH)
Allow branches to be packed with other instructions.
; <http://www.gnu.org/licenses/>.
msim
-Target Report Mask(SIM)
+Target Mask(SIM)
Target the software simulator.
mlra
-Target Report Var(ft32_lra_flag) Init(0) Save
+Target Var(ft32_lra_flag) Init(0) Save
Use LRA instead of reload.
mnodiv
-Target Report Mask(NODIV)
+Target Mask(NODIV)
Avoid use of the DIV and MOD instructions.
mft32b
-Target Report Mask(FT32B)
+Target Mask(FT32B)
Target the FT32B architecture.
mcompress
-Target Report Mask(COMPRESS)
+Target Mask(COMPRESS)
Enable FT32B code compression.
mnopm
-Target Report Mask(NOPM)
+Target Mask(NOPM)
Avoid placing any readable data in program memory.
Specify the name of the target GPU.
m32
-Target Report RejectNegative InverseMask(ABI64)
+Target RejectNegative InverseMask(ABI64)
Generate code for a 32-bit ABI.
m64
-Target Report RejectNegative Mask(ABI64)
+Target RejectNegative Mask(ABI64)
Generate code for a 64-bit ABI.
mgomp
-Target Report RejectNegative
+Target RejectNegative
Enable OpenMP GPU offloading.
bool flag_bypass_init_error = false
mbypass-init-error
-Target Report RejectNegative Var(flag_bypass_init_error)
+Target RejectNegative Var(flag_bypass_init_error)
bool flag_worker_partitioning = false
macc-experimental-workers
-Target Report Var(flag_worker_partitioning) Init(0)
+Target Var(flag_worker_partitioning) Init(0)
int stack_size_opt = -1
mstack-size=
-Target Report RejectNegative Joined UInteger Var(stack_size_opt) Init(-1)
+Target RejectNegative Joined UInteger Var(stack_size_opt) Init(-1)
-mstack-size=<number> Set the private segment size per wave-front, in bytes.
Wopenacc-dims
Generate code for a DLL.
mnop-fun-dllimport
-Target Report Var(TARGET_NOP_FUN_DLLIMPORT)
+Target Var(TARGET_NOP_FUN_DLLIMPORT)
Ignore dllimport for functions.
mthreads
Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement.
fset-stack-executable
-Common Report Var(flag_setstackexecutable) Init(1) Optimization
+Common Var(flag_setstackexecutable) Init(1) Optimization
For nested functions on stack executable permission is set.
posix
Driver
fwritable-relocated-rdata
-Common Report Var(flag_writable_rel_rdata) Init(0)
+Common Var(flag_writable_rel_rdata) Init(0)
Put relocated read-only data into .data section.
; Retain blank line above
;; x86 options
m128bit-long-double
-Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
+Target RejectNegative Mask(128BIT_LONG_DOUBLE) Save
sizeof(long double) is 16.
m80387
-Target Report Mask(80387) Save
+Target Mask(80387) Save
Use hardware fp.
m96bit-long-double
-Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
+Target RejectNegative InverseMask(128BIT_LONG_DOUBLE) Save
sizeof(long double) is 12.
mlong-double-80
-Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
+Target RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
Use 80-bit long double.
mlong-double-64
-Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
+Target RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
Use 64-bit long double.
mlong-double-128
-Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
+Target RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
Use 128-bit long double.
maccumulate-outgoing-args
-Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
+Target Mask(ACCUMULATE_OUTGOING_ARGS) Save
Reserve space for outgoing arguments in the function prologue.
malign-double
-Target Report Mask(ALIGN_DOUBLE) Save
+Target Mask(ALIGN_DOUBLE) Save
Align some doubles on dword boundary.
malign-functions=
Loop code aligned to this power of 2.
malign-stringops
-Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
+Target RejectNegative InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
Align destination of the string operations.
malign-data=
Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
mfancy-math-387
-Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
+Target RejectNegative InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
Generate sin, cos, sqrt for FPU.
mforce-drap
-Target Report Var(ix86_force_drap)
+Target Var(ix86_force_drap)
Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack.
mfp-ret-in-387
-Target Report Mask(FLOAT_RETURNS) Save
+Target Mask(FLOAT_RETURNS) Save
Return values of functions in FPU registers.
mfpmath=
Use hardware fp.
mieee-fp
-Target Report Mask(IEEE_FP) Save
+Target Mask(IEEE_FP) Save
Use IEEE math for fp comparisons.
minline-all-stringops
-Target Report Mask(INLINE_ALL_STRINGOPS) Save
+Target Mask(INLINE_ALL_STRINGOPS) Save
Inline all known string operations.
minline-stringops-dynamically
-Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
+Target Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
Inline memset/memcpy string operations, but perform inline version only for small blocks.
mintel-syntax
Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
mms-bitfields
-Target Report Mask(MS_BITFIELD_LAYOUT) Save
+Target Mask(MS_BITFIELD_LAYOUT) Save
Use native (MS) bitfield layout.
mno-align-stringops
-Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
+Target RejectNegative Mask(NO_ALIGN_STRINGOPS) Undocumented Save
mno-fancy-math-387
-Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
+Target RejectNegative Mask(NO_FANCY_MATH_387) Undocumented Save
mno-push-args
-Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
+Target RejectNegative Mask(NO_PUSH_ARGS) Undocumented Save
mno-red-zone
-Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
+Target RejectNegative Mask(NO_RED_ZONE) Undocumented Save
momit-leaf-frame-pointer
-Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
+Target Mask(OMIT_LEAF_FRAME_POINTER) Save
Omit the frame pointer in leaf functions.
mpc32
-Target RejectNegative Report
+Target RejectNegative
Set 80387 floating-point precision to 32-bit.
mpc64
-Target RejectNegative Report
+Target RejectNegative
Set 80387 floating-point precision to 64-bit.
mpc80
-Target RejectNegative Report
+Target RejectNegative
Set 80387 floating-point precision to 80-bit.
mpreferred-stack-boundary=
Assume incoming stack aligned to this power of 2.
mpush-args
-Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
+Target InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
Use push instructions to save outgoing arguments.
mred-zone
-Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
+Target RejectNegative InverseMask(NO_RED_ZONE, RED_ZONE) Save
Use red-zone in the x86-64 code.
mregparm=
Number of registers used to pass integer arguments.
mrtd
-Target Report Mask(RTD) Save
+Target Mask(RTD) Save
Alternate calling convention.
msoft-float
Use SSE register passing conventions for SF and DF mode.
mstackrealign
-Target Report Var(ix86_force_align_arg_pointer)
+Target Var(ix86_force_align_arg_pointer)
Realign stack in prologue.
mstack-arg-probe
-Target Report Mask(STACK_PROBE) Save
+Target Mask(STACK_PROBE) Save
Enable stack probing.
mmemcpy-strategy=
Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
mtls-direct-seg-refs
-Target Report Mask(TLS_DIRECT_SEG_REFS)
+Target Mask(TLS_DIRECT_SEG_REFS)
Use direct references against %gs when accessing tls data.
mtune=
Target RejectNegative Var(ix86_dump_tunes)
miamcu
-Target Report Mask(IAMCU)
+Target Mask(IAMCU)
Generate code that conforms to Intel MCU psABI.
mabi=
Enum(calling_abi) String(ms) Value(MS_ABI)
mcall-ms2sysv-xlogues
-Target Report Mask(CALL_MS2SYSV_XLOGUES) Save
+Target Mask(CALL_MS2SYSV_XLOGUES) Save
Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls.
mveclibabi=
Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
mvect8-ret-in-mem
-Target Report Mask(VECT8_RETURNS) Save
+Target Mask(VECT8_RETURNS) Save
Return 8-byte vectors in memory.
mrecip
-Target Report Mask(RECIP) Save
+Target Mask(RECIP) Save
Generate reciprocals instead of divss and sqrtss.
mrecip=
-Target Report RejectNegative Joined Var(ix86_recip_name)
+Target RejectNegative Joined Var(ix86_recip_name)
Control generation of reciprocal estimates.
mcld
-Target Report Mask(CLD) Save
+Target Mask(CLD) Save
Generate cld instruction in the function prologue.
mvzeroupper
-Target Report Mask(VZEROUPPER) Save
+Target Mask(VZEROUPPER) Save
Generate vzeroupper instruction before a transfer of control flow out of
the function.
mstv
-Target Report Mask(STV) Save
+Target Mask(STV) Save
Disable Scalar to Vector optimization pass transforming 64-bit integer
computations into a vector ones.
Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
mprefer-vector-width=
-Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save
+Target RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save
Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
Enum
;; ISA support
m32
-Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
+Target RejectNegative Negative(m64) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
Generate 32bit i386 code.
m64
-Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
+Target RejectNegative Negative(mx32) Mask(ABI_64) Var(ix86_isa_flags) Save
Generate 64bit x86-64 code.
mx32
-Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
+Target RejectNegative Negative(m16) Mask(ABI_X32) Var(ix86_isa_flags) Save
Generate 32bit x86-64 code.
m16
-Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
+Target RejectNegative Negative(m32) Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
Generate 16bit i386 code.
mmmx
-Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
+Target Mask(ISA_MMX) Var(ix86_isa_flags) Save
Support MMX built-in functions.
m3dnow
-Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
+Target Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
Support 3DNow! built-in functions.
m3dnowa
-Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
+Target Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
Support Athlon 3Dnow! built-in functions.
msse
-Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSE) Var(ix86_isa_flags) Save
Support MMX and SSE built-in functions and code generation.
msse2
-Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSE2) Var(ix86_isa_flags) Save
Support MMX, SSE and SSE2 built-in functions and code generation.
msse3
-Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSE3) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
mssse3
-Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
msse4.1
-Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
msse4.2
-Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
msse4
-Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
+Target RejectNegative Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
mno-sse4
-Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
+Target RejectNegative InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
msse5
;; Deprecated
mavx
-Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
mavx2
-Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation.
mavx512f
-Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation.
mavx512pf
-Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation.
mavx512er
-Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation.
mavx512cd
-Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation.
mavx512dq
-Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation.
mavx512bw
-Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation.
mavx512vl
-Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation.
mavx512ifma
-Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation.
mavx512vbmi
-Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation.
mavx5124fmaps
-Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation.
mavx5124vnniw
-Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation.
mavx512vpopcntdq
-Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation.
mavx512vbmi2
-Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation.
mavx512vnni
-Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save
Support AVX512VNNI built-in functions and code generation.
mavx512bitalg
-Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save
+Target Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation.
mavx512vp2intersect
-Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save
Support AVX512VP2INTERSECT built-in functions and code generation.
mfma
-Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
+Target Mask(ISA_FMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.
msse4a
-Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
+Target Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation.
mfma4
-Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
+Target Mask(ISA_FMA4) Var(ix86_isa_flags) Save
Support FMA4 built-in functions and code generation.
mxop
-Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
+Target Mask(ISA_XOP) Var(ix86_isa_flags) Save
Support XOP built-in functions and code generation.
mlwp
-Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
+Target Mask(ISA_LWP) Var(ix86_isa_flags) Save
Support LWP built-in functions and code generation.
mabm
-Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
+Target Mask(ISA_ABM) Var(ix86_isa_flags) Save
Support code generation of Advanced Bit Manipulation (ABM) instructions.
mpopcnt
-Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
+Target Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
Support code generation of popcnt instruction.
mpconfig
-Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save
Support PCONFIG built-in functions and code generation.
mwbnoinvd
-Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save
Support WBNOINVD built-in functions and code generation.
mptwrite
-Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save
Support PTWRITE built-in functions and code generation.
muintr
-Target Report Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save
Support UINTR built-in functions and code generation.
msgx
-Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
Support SGX built-in functions and code generation.
mrdpid
-Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save
Support RDPID built-in functions and code generation.
mgfni
-Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save
+Target Mask(ISA_GFNI) Var(ix86_isa_flags) Save
Support GFNI built-in functions and code generation.
mvaes
-Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_VAES) Var(ix86_isa_flags2) Save
Support VAES built-in functions and code generation.
mvpclmulqdq
-Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save
+Target Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save
Support VPCLMULQDQ built-in functions and code generation.
mbmi
-Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
+Target Mask(ISA_BMI) Var(ix86_isa_flags) Save
Support BMI built-in functions and code generation.
mbmi2
-Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
+Target Mask(ISA_BMI2) Var(ix86_isa_flags) Save
Support BMI2 built-in functions and code generation.
mlzcnt
-Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
+Target Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
Support LZCNT built-in function and code generation.
mhle
-Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_HLE) Var(ix86_isa_flags2) Save
Support Hardware Lock Elision prefixes.
mrdseed
-Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
+Target Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
Support RDSEED instruction.
mprfchw
-Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
+Target Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
Support PREFETCHW instruction.
madx
-Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
+Target Mask(ISA_ADX) Var(ix86_isa_flags) Save
Support flag-preserving add-carry instructions.
mclflushopt
-Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
+Target Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
Support CLFLUSHOPT instructions.
mclwb
-Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
+Target Mask(ISA_CLWB) Var(ix86_isa_flags) Save
Support CLWB instruction.
mpcommit
Target WarnRemoved
mfxsr
-Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
+Target Mask(ISA_FXSR) Var(ix86_isa_flags) Save
Support FXSAVE and FXRSTOR instructions.
mxsave
-Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
+Target Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
Support XSAVE and XRSTOR instructions.
mxsaveopt
-Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
+Target Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
Support XSAVEOPT instruction.
mxsavec
-Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
+Target Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
Support XSAVEC instructions.
mxsaves
-Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
+Target Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
Support XSAVES and XRSTORS instructions.
mtbm
-Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
+Target Mask(ISA_TBM) Var(ix86_isa_flags) Save
Support TBM built-in functions and code generation.
mcx16
-Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_CX16) Var(ix86_isa_flags2) Save
Support code generation of cmpxchg16b instruction.
msahf
-Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
+Target Mask(ISA_SAHF) Var(ix86_isa_flags) Save
Support code generation of sahf instruction in 64bit x86-64 code.
mmovbe
-Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save
Support code generation of movbe instruction.
mcrc32
-Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
+Target Mask(ISA_CRC32) Var(ix86_isa_flags) Save
Support code generation of crc32 instruction.
maes
-Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
+Target Mask(ISA_AES) Var(ix86_isa_flags) Save
Support AES built-in functions and code generation.
msha
-Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save
+Target Mask(ISA_SHA) Var(ix86_isa_flags) Save
Support SHA1 and SHA256 built-in functions and code generation.
mpclmul
-Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
+Target Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
Support PCLMUL built-in functions and code generation.
msse2avx
-Target Report Var(ix86_sse2avx)
+Target Var(ix86_sse2avx)
Encode SSE instructions with VEX prefix.
mfsgsbase
-Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
+Target Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
Support FSGSBASE built-in functions and code generation.
mrdrnd
-Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
+Target Mask(ISA_RDRND) Var(ix86_isa_flags) Save
Support RDRND built-in functions and code generation.
mf16c
-Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
+Target Mask(ISA_F16C) Var(ix86_isa_flags) Save
Support F16C built-in functions and code generation.
mprefetchwt1
-Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
+Target Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
Support PREFETCHWT1 built-in functions and code generation.
mfentry
-Target Report Var(flag_fentry)
+Target Var(flag_fentry)
Emit profiling counter call at function entry before prologue.
mrecord-mcount
-Target Report Var(flag_record_mcount)
+Target Var(flag_record_mcount)
Generate __mcount_loc section with all mcount or __fentry__ calls.
mnop-mcount
-Target Report Var(flag_nop_mcount)
+Target Var(flag_nop_mcount)
Generate mcount/__fentry__ calls as nops. To activate they need to be
patched in.
Set name of section to record mrecord-mcount calls.
mskip-rax-setup
-Target Report Var(flag_skip_rax_setup)
+Target Var(flag_skip_rax_setup)
Skip setting up RAX register when passing variable arguments.
m8bit-idiv
-Target Report Mask(USE_8BIT_IDIV) Save
+Target Mask(USE_8BIT_IDIV) Save
Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check.
mavx256-split-unaligned-load
-Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
+Target Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
Split 32-byte AVX unaligned load.
mavx256-split-unaligned-store
-Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
+Target Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
Split 32-byte AVX unaligned store.
mrtm
-Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
+Target Mask(ISA_RTM) Var(ix86_isa_flags) Save
Support RTM built-in functions and code generation.
mmpx
Removed in GCC 9. This switch has no effect.
mmwaitx
-Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save
Support MWAITX and MONITORX built-in functions and code generation.
mclzero
-Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save
Support CLZERO built-in functions and code generation.
mpku
-Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save
+Target Mask(ISA_PKU) Var(ix86_isa_flags) Save
Support PKU built-in functions and code generation.
mstack-protector-guard=
Target WarnRemoved
mgeneral-regs-only
-Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
+Target RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
Generate code which uses only the general registers.
mshstk
-Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save
+Target Mask(ISA_SHSTK) Var(ix86_isa_flags) Save
Enable shadow stack built-in functions from Control-flow Enforcement
Technology (CET).
mcet-switch
-Target Report Undocumented Var(flag_cet_switch) Init(0)
+Target Undocumented Var(flag_cet_switch) Init(0)
Turn on CET instrumentation for switch statements that use a jump table and
an indirect jump.
mmanual-endbr
-Target Report Var(flag_manual_endbr) Init(0)
+Target Var(flag_manual_endbr) Init(0)
Insert ENDBR instruction at function entry only via cf_check attribute
for CET instrumentation.
mforce-indirect-call
-Target Report Var(flag_force_indirect_call) Init(0)
+Target Var(flag_force_indirect_call) Init(0)
Make all function calls indirect.
mindirect-branch=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
Convert indirect call and jump to call and return thunks.
mfunction-return=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
Convert function return to call and return thunk.
Enum
Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
mindirect-branch-register
-Target Report Var(ix86_indirect_branch_register) Init(0)
+Target Var(ix86_indirect_branch_register) Init(0)
Force indirect call and jump via register.
mmovdiri
-Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save
+Target Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save
Support MOVDIRI built-in functions and code generation.
mmovdir64b
-Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save
Support MOVDIR64B built-in functions and code generation.
mwaitpkg
-Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save
Support WAITPKG built-in functions and code generation.
mcldemote
-Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save
Support CLDEMOTE built-in functions and code generation.
minstrument-return=
-Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none)
+Target RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none)
Instrument function exit in instrumented functions with __fentry__.
Enum
Enum(instrument_return) String(nop5) Value(instrument_return_nop5)
mrecord-return
-Target Report Var(ix86_flag_record_return) Init(0)
+Target Var(ix86_flag_record_return) Init(0)
Generate a __return_loc section pointing to all return instrumentation code.
mavx512bf16
-Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
AVX512BF16 built-in functions and code generation.
menqcmd
-Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
Support ENQCMD built-in functions and code generation.
mserialize
-Target Report Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save
Support SERIALIZE built-in functions and code generation.
mtsxldtrk
-Target Report Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save
Support TSXLDTRK built-in functions and code generation.
mamx-tile
-Target Report Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save
Support AMX-TILE built-in functions and code generation.
mamx-int8
-Target Report Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save
Support AMX-INT8 built-in functions and code generation.
mamx-bf16
-Target Report Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save
Support AMX-BF16 built-in functions and code generation.
mhreset
-Target Report Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save
Support HRESET built-in functions and code generation.
mkl
-Target Report Mask(ISA2_KL) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_KL) Var(ix86_isa_flags2) Save
Support KL built-in functions and code generation.
mwidekl
-Target Report Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save
Support WIDEKL built-in functions and code generation.
mavxvnni
-Target Report Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save
+Target Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and
AVXVNNI built-in functions and code generation.
mneeded
-Target Report Var(ix86_needed) Save
+Target Var(ix86_needed) Save
Emit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property.
enum processor_type ia64_tune = PROCESSOR_ITANIUM2
mbig-endian
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Generate big endian code.
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Generate little endian code.
mgnu-as
-Target Report Mask(GNU_AS)
+Target Mask(GNU_AS)
Generate code for GNU as.
mgnu-ld
-Target Report Mask(GNU_LD)
+Target Mask(GNU_LD)
Generate code for GNU ld.
mvolatile-asm-stop
-Target Report Mask(VOL_ASM_STOP)
+Target Mask(VOL_ASM_STOP)
Emit stop bits before and after volatile extended asms.
mregister-names
Use in/loc/out register names.
mno-sdata
-Target Report RejectNegative Mask(NO_SDATA)
+Target RejectNegative Mask(NO_SDATA)
msdata
-Target Report RejectNegative InverseMask(NO_SDATA)
+Target RejectNegative InverseMask(NO_SDATA)
Enable use of sdata/scommon/sbss.
mno-pic
-Target Report RejectNegative Mask(NO_PIC)
+Target RejectNegative Mask(NO_PIC)
Generate code without GP reg.
mconstant-gp
-Target Report RejectNegative Mask(CONST_GP)
+Target RejectNegative Mask(CONST_GP)
gp is constant (but save/restore gp on indirect calls).
mauto-pic
-Target Report RejectNegative Mask(AUTO_PIC)
+Target RejectNegative Mask(AUTO_PIC)
Generate self-relocatable code.
minline-float-divide-min-latency
-Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
+Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
Generate inline floating point division, optimize for latency.
minline-float-divide-max-throughput
-Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
+Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
Generate inline floating point division, optimize for throughput.
mno-inline-float-divide
-Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
+Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
minline-int-divide-min-latency
-Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
+Target RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
Generate inline integer division, optimize for latency.
minline-int-divide-max-throughput
-Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
+Target RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
Generate inline integer division, optimize for throughput.
mno-inline-int-divide
-Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
+Target RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
Do not inline integer division.
minline-sqrt-min-latency
-Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
+Target RejectNegative Var(TARGET_INLINE_SQRT, 1)
Generate inline square root, optimize for latency.
minline-sqrt-max-throughput
-Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
+Target RejectNegative Var(TARGET_INLINE_SQRT, 2)
Generate inline square root, optimize for throughput.
mno-inline-sqrt
-Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
+Target RejectNegative Var(TARGET_INLINE_SQRT, 0)
Do not inline square root.
mdwarf2-asm
-Target Report Mask(DWARF2_ASM)
+Target Mask(DWARF2_ASM)
Enable DWARF line debug info via GNU as.
mearly-stop-bits
-Target Report Mask(EARLY_STOP_BITS)
+Target Mask(EARLY_STOP_BITS)
Enable earlier placing stop bits for better scheduling.
mfixed-range=
Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2)
msched-br-data-spec
-Target Report Var(mflag_sched_br_data_spec) Init(0)
+Target Var(mflag_sched_br_data_spec) Init(0)
Use data speculation before reload.
msched-ar-data-spec
-Target Report Var(mflag_sched_ar_data_spec) Init(1)
+Target Var(mflag_sched_ar_data_spec) Init(1)
Use data speculation after reload.
msched-control-spec
-Target Report Var(mflag_sched_control_spec) Init(2)
+Target Var(mflag_sched_control_spec) Init(2)
Use control speculation.
msched-br-in-data-spec
-Target Report Var(mflag_sched_br_in_data_spec) Init(1)
+Target Var(mflag_sched_br_in_data_spec) Init(1)
Use in block data speculation before reload.
msched-ar-in-data-spec
-Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
+Target Var(mflag_sched_ar_in_data_spec) Init(1)
Use in block data speculation after reload.
msched-in-control-spec
-Target Report Var(mflag_sched_in_control_spec) Init(1)
+Target Var(mflag_sched_in_control_spec) Init(1)
Use in block control speculation.
msched-spec-ldc
-Target Report Var(mflag_sched_spec_ldc) Init(1)
+Target Var(mflag_sched_spec_ldc) Init(1)
Use simple data speculation check.
msched-spec-control-ldc
-Target Report Var(mflag_sched_spec_control_ldc) Init(0)
+Target Var(mflag_sched_spec_control_ldc) Init(0)
Use simple data speculation check for control speculation.
msched-prefer-non-data-spec-insns
Target WarnRemoved
msched-count-spec-in-critical-path
-Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
+Target Var(mflag_sched_count_spec_in_critical_path) Init(0)
Count speculative dependencies while calculating priority of instructions.
msched-stop-bits-after-every-cycle
-Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
+Target Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
Place a stop bit after every cycle when scheduling.
msched-fp-mem-deps-zero-cost
-Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
+Target Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group.
msched-max-memory-insns=
Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1.
msched-max-memory-insns-hard-limit
-Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
+Target Var(mflag_sched_mem_insns_hard_limit) Init(0)
Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached).
msel-sched-dont-check-control-spec
-Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
+Target Var(mflag_sel_sched_dont_check_control_spec) Init(0)
Don't generate checks for control speculation in selective scheduling.
; This comment is to ensure we retain the blank line above.
milp32
-Target Report RejectNegative Mask(ILP32)
+Target RejectNegative Mask(ILP32)
Generate ILP32 code.
mlp64
-Target Report RejectNegative InverseMask(ILP32)
+Target RejectNegative InverseMask(ILP32)
Generate LP64 code.
; <http://www.gnu.org/licenses/>.
mandroid
-Target Report Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0)
+Target Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0)
Generate code for the Android platform.
tno-android-cc
; <http://www.gnu.org/licenses/>.
mbionic
-Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc)
+Target RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc)
Use Bionic C library.
mglibc
-Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc)
+Target RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc)
Use GNU C library.
muclibc
-Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl)
+Target RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl)
Use uClibc C library.
mmusl
-Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic)
+Target RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic)
Use musl C library.
; <http://www.gnu.org/licenses/>.
mmultiply-enabled
-Target Report Mask(MULTIPLY_ENABLED)
+Target Mask(MULTIPLY_ENABLED)
Enable multiply instructions.
mdivide-enabled
-Target Report Mask(DIVIDE_ENABLED)
+Target Mask(DIVIDE_ENABLED)
Enable divide and modulus instructions.
mbarrel-shift-enabled
-Target Report Mask(BARREL_SHIFT_ENABLED)
+Target Mask(BARREL_SHIFT_ENABLED)
Enable barrel shift instructions.
msign-extend-enabled
-Target Report Mask(SIGN_EXTEND_ENABLED)
+Target Mask(SIGN_EXTEND_ENABLED)
Enable sign extend instructions.
muser-enabled
-Target Report Mask(USER_ENABLED)
+Target Mask(USER_ENABLED)
Enable user-defined instructions.
enum m32r_sdata m32r_sdata_selected = M32R_SDATA_DEFAULT
m32rx
-Target Report RejectNegative Mask(M32RX)
+Target RejectNegative Mask(M32RX)
Compile for the m32rx.
m32r2
-Target Report RejectNegative Mask(M32R2)
+Target RejectNegative Mask(M32R2)
Compile for the m32r2.
m32r
Compile for the m32r.
malign-loops
-Target Report Mask(ALIGN_LOOPS)
+Target Mask(ALIGN_LOOPS)
Align all loops to 32 byte boundary.
mbranch-cost=1
-Target Report RejectNegative Mask(BRANCH_COST)
+Target RejectNegative Mask(BRANCH_COST)
Prefer branches over conditional execution.
mbranch-cost=2
-Target Report RejectNegative InverseMask(BRANCH_COST)
+Target RejectNegative InverseMask(BRANCH_COST)
Give branches their default cost.
mdebug
Specify cache flush trap number.
missue-rate=1
-Target Report RejectNegative Mask(LOW_ISSUE_RATE)
+Target RejectNegative Mask(LOW_ISSUE_RATE)
Only issue one instruction per cycle.
missue-rate=2
-Target Report RejectNegative InverseMask(LOW_ISSUE_RATE)
+Target RejectNegative InverseMask(LOW_ISSUE_RATE)
Allow two instructions to be issued per cycle.
mmodel=
Generate code that uses 68881 floating-point instructions.
malign-int
-Target Report Mask(ALIGN_INT)
+Target Mask(ALIGN_INT)
Align variables on a 32-bit boundary.
march=
Specify the name of the target architecture.
mbitfield
-Target Report Mask(BITFIELD)
+Target Mask(BITFIELD)
Use the bit-field instructions.
mc68000
Generate code for a cpu32.
mdiv
-Target Report Mask(CF_HWDIV)
+Target Mask(CF_HWDIV)
Use hardware division instructions on ColdFire.
mfidoa
Generate code which uses hardware floating point instructions.
mid-shared-library
-Target Report Mask(ID_SHARED_LIBRARY)
+Target Mask(ID_SHARED_LIBRARY)
Enable ID based shared library.
mlong-jump-table-offsets
-Target Report RejectNegative Mask(LONG_JUMP_TABLE_OFFSETS)
+Target RejectNegative Mask(LONG_JUMP_TABLE_OFFSETS)
Use 32-bit offsets in jump tables rather than 16-bit offsets.
mnobitfield
Consider type 'int' to be 32 bits wide.
mpcrel
-Target Report Mask(PCREL)
+Target Mask(PCREL)
Generate pc-relative code.
mrtd
-Target Report Mask(RTD)
+Target Mask(RTD)
Use different calling convention using 'rtd'.
msep-data
-Target Report Mask(SEP_DATA)
+Target Mask(SEP_DATA)
Enable separate data segment.
mshared-library-id=
ID of shared library to build.
mshort
-Target Report Mask(SHORT)
+Target Mask(SHORT)
Consider type 'int' to be 16 bits wide.
msoft-float
Generate code with library calls for floating point.
mstrict-align
-Target Report Mask(STRICT_ALIGNMENT)
+Target Mask(STRICT_ALIGNMENT)
Do not use unaligned memory references.
mtune=
Tune for the specified target CPU or architecture.
mxgot
-Target Report Mask(XGOT)
+Target Mask(XGOT)
Support more than 8192 GOT entries on ColdFire.
mxtls
-Target Report Mask(XTLS)
+Target Mask(XTLS)
Support TLS segment larger than 64K.
; <http://www.gnu.org/licenses/>.
m210
-Target RejectNegative Report InverseMask(M340)
+Target RejectNegative InverseMask(M340)
Generate code for the M*Core M210.
m340
-Target RejectNegative Report Mask(M340)
+Target RejectNegative Mask(M340)
Generate code for the M*Core M340.
m4byte-functions
-Target Report Mask(OVERALIGN_FUNC)
+Target Mask(OVERALIGN_FUNC)
Force functions to be aligned to a 4 byte boundary.
mbig-endian
-Target RejectNegative Report InverseMask(LITTLE_END)
+Target RejectNegative InverseMask(LITTLE_END)
Generate big-endian code.
mcallgraph-data
-Target Report Mask(CG_DATA)
+Target Mask(CG_DATA)
Emit call graph information.
mdiv
-Target Report Mask(DIV)
+Target Mask(DIV)
Use the divide instruction.
mhardlit
-Target Report Mask(HARDLIT)
+Target Mask(HARDLIT)
Inline constants if it can be done in 2 insns or less.
mlittle-endian
-Target RejectNegative Report Mask(LITTLE_END)
+Target RejectNegative Mask(LITTLE_END)
Generate little-endian code.
; Not used by the compiler proper.
Assume that run-time support has been provided, so omit -lsim from the linker command line.
mrelax-immediates
-Target Report Mask(RELAX_IMM)
+Target Mask(RELAX_IMM)
Use arbitrary sized immediates in bit operations.
mslow-bytes
-Target Report Mask(SLOW_BYTES)
+Target Mask(SLOW_BYTES)
Prefer word accesses over byte accesses.
; Maximum size we are allowed to grow the stack in a single operation.
Set the maximum amount for a single stack increment operation.
mwide-bitfields
-Target Report Mask(W_FIELD)
+Target Mask(W_FIELD)
Always treat bitfields as int-sized.
Driver
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT)
+Target RejectNegative Mask(SOFT_FLOAT)
Use software emulation for floating point (default).
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
+Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
Use hardware floating point instructions.
msmall-divides
Don't optimize block moves, use memcpy.
mbig-endian
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Target RejectNegative InverseMask(LITTLE_ENDIAN)
Assume target CPU is configured as big endian.
mlittle-endian
-Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Target RejectNegative Mask(LITTLE_ENDIAN)
Assume target CPU is configured as little endian.
mxl-soft-mul
Enum(mips_abi) String(eabi) Value(ABI_EABI)
mabicalls
-Target Report Mask(ABICALLS)
+Target Mask(ABICALLS)
Generate code that can be used in SVR4-style dynamic objects.
mmad
-Target Report Var(TARGET_MAD)
+Target Var(TARGET_MAD)
Use PMC-style 'mad' instructions.
mimadd
-Target Report Mask(IMADD)
+Target Mask(IMADD)
Use integer madd/msub instructions.
march=
-mbranch-cost=COST Set the cost of branches to roughly COST instructions.
mbranch-likely
-Target Report Mask(BRANCHLIKELY)
+Target Mask(BRANCHLIKELY)
Use Branch Likely instructions, overriding the architecture default.
mflip-mips16
-Target Report Var(TARGET_FLIP_MIPS16)
+Target Var(TARGET_FLIP_MIPS16)
Switch on/off MIPS16 ASE on alternating functions for compiler testing.
mcheck-zero-division
-Target Report Mask(CHECK_ZERO_DIV)
+Target Mask(CHECK_ZERO_DIV)
Trap on integer divide by zero.
mcode-readable=
Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
mdivide-breaks
-Target Report RejectNegative Mask(DIVIDE_BREAKS)
+Target RejectNegative Mask(DIVIDE_BREAKS)
Use branch-and-break sequences to check for integer divide by zero.
mdivide-traps
-Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
+Target RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
Use trap instructions to check for integer divide by zero.
mdmx
-Target Report RejectNegative Var(TARGET_MDMX)
+Target RejectNegative Var(TARGET_MDMX)
Allow the use of MDMX instructions.
mdouble-float
-Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
+Target RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
mdsp
-Target Report Var(TARGET_DSP)
+Target Var(TARGET_DSP)
Use MIPS-DSP instructions.
mdspr2
-Target Report Var(TARGET_DSPR2)
+Target Var(TARGET_DSPR2)
Use MIPS-DSP REV 2 instructions.
mdebug
Target Var(TARGET_DEBUG_D_MODE) Undocumented
meb
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order.
mel
-Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
Use little-endian byte order.
membedded-data
-Target Report Var(TARGET_EMBEDDED_DATA)
+Target Var(TARGET_EMBEDDED_DATA)
Use ROM instead of RAM.
meva
-Target Report Var(TARGET_EVA)
+Target Var(TARGET_EVA)
Use Enhanced Virtual Addressing instructions.
mexplicit-relocs
-Target Report Mask(EXPLICIT_RELOCS)
+Target Mask(EXPLICIT_RELOCS)
Use NewABI-style %reloc() assembly operators.
mextern-sdata
-Target Report Var(TARGET_EXTERN_SDATA) Init(1)
+Target Var(TARGET_EXTERN_SDATA) Init(1)
Use -G for data that is not defined by the current object.
mfix-24k
-Target Report Var(TARGET_FIX_24K)
+Target Var(TARGET_FIX_24K)
Work around certain 24K errata.
mfix-r4000
-Target Report Mask(FIX_R4000)
+Target Mask(FIX_R4000)
Work around certain R4000 errata.
mfix-r4400
-Target Report Mask(FIX_R4400)
+Target Mask(FIX_R4400)
Work around certain R4400 errata.
mfix-r5900
-Target Report Mask(FIX_R5900)
+Target Mask(FIX_R5900)
Work around the R5900 short loop erratum.
mfix-rm7000
-Target Report Var(TARGET_FIX_RM7000)
+Target Var(TARGET_FIX_RM7000)
Work around certain RM7000 errata.
mfix-r10000
-Target Report Mask(FIX_R10000)
+Target Mask(FIX_R10000)
Work around certain R10000 errata.
mfix-sb1
-Target Report Var(TARGET_FIX_SB1)
+Target Var(TARGET_FIX_SB1)
Work around errata for early SB-1 revision 2 cores.
mfix-vr4120
-Target Report Var(TARGET_FIX_VR4120)
+Target Var(TARGET_FIX_VR4120)
Work around certain VR4120 errata.
mfix-vr4130
-Target Report Var(TARGET_FIX_VR4130)
+Target Var(TARGET_FIX_VR4130)
Work around VR4130 mflo/mfhi errata.
mfix4300
-Target Report Var(TARGET_4300_MUL_FIX)
+Target Var(TARGET_4300_MUL_FIX)
Work around an early 4300 hardware bug.
mfp-exceptions
-Target Report Var(TARGET_FP_EXCEPTIONS) Init(1)
+Target Var(TARGET_FP_EXCEPTIONS) Init(1)
FP exceptions are enabled.
mfp32
-Target Report RejectNegative InverseMask(FLOAT64)
+Target RejectNegative InverseMask(FLOAT64)
Use 32-bit floating-point registers.
mfpxx
-Target Report RejectNegative Mask(FLOATXX)
+Target RejectNegative Mask(FLOATXX)
Conform to the o32 FPXX ABI.
mfp64
-Target Report RejectNegative Mask(FLOAT64)
+Target RejectNegative Mask(FLOAT64)
Use 64-bit floating-point registers.
mflush-func=
Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY)
mgp32
-Target Report RejectNegative InverseMask(64BIT)
+Target RejectNegative InverseMask(64BIT)
Use 32-bit general registers.
mgp64
-Target Report RejectNegative Mask(64BIT)
+Target RejectNegative Mask(64BIT)
Use 64-bit general registers.
mgpopt
-Target Report Var(TARGET_GPOPT) Init(1)
+Target Var(TARGET_GPOPT) Init(1)
Use GP-relative addressing to access small data.
mplt
-Target Report Var(TARGET_PLT)
+Target Var(TARGET_PLT)
When generating -mabicalls code, allow executables to use PLTs and copy relocations.
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
+Target RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
Allow the use of hardware floating-point ABI and instructions.
minterlink-compressed
-Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
+Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
Generate code that is link-compatible with MIPS16 and microMIPS code.
minterlink-mips16
-Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
+Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
An alias for minterlink-compressed provided for backward-compatibility.
mips
-mipsN Generate code for ISA level N.
mips16
-Target Report RejectNegative Mask(MIPS16)
+Target RejectNegative Mask(MIPS16)
Generate MIPS16 code.
mips3d
-Target Report RejectNegative Var(TARGET_MIPS3D)
+Target RejectNegative Var(TARGET_MIPS3D)
Use MIPS-3D instructions.
mllsc
-Target Report Mask(LLSC)
+Target Mask(LLSC)
Use ll, sc and sync instructions.
mlocal-sdata
-Target Report Var(TARGET_LOCAL_SDATA) Init(1)
+Target Var(TARGET_LOCAL_SDATA) Init(1)
Use -G for object-local data.
mlong-calls
-Target Report Var(TARGET_LONG_CALLS)
+Target Var(TARGET_LONG_CALLS)
Use indirect calls.
mlong32
-Target Report RejectNegative InverseMask(LONG64, LONG32)
+Target RejectNegative InverseMask(LONG64, LONG32)
Use a 32-bit long type.
mlong64
-Target Report RejectNegative Mask(LONG64)
+Target RejectNegative Mask(LONG64)
Use a 64-bit long type.
mmcount-ra-address
-Target Report Var(TARGET_MCOUNT_RA_ADDRESS)
+Target Var(TARGET_MCOUNT_RA_ADDRESS)
Pass the address of the ra save location to _mcount in $12.
mmemcpy
-Target Report Mask(MEMCPY)
+Target Mask(MEMCPY)
Don't optimize block moves.
mmicromips
-Target Report Mask(MICROMIPS)
+Target Mask(MICROMIPS)
Use microMIPS instructions.
mmsa
-Target Report Mask(MSA)
+Target Mask(MSA)
Use MIPS MSA Extension instructions.
mmt
-Target Report Var(TARGET_MT)
+Target Var(TARGET_MT)
Allow the use of MT instructions.
mno-float
-Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
+Target RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
Prevent the use of all floating-point operations.
mmcu
-Target Report Var(TARGET_MCU)
+Target Var(TARGET_MCU)
Use MCU instructions.
mno-flush-func
Do not use a cache-flushing function before calling stack trampolines.
mno-mdmx
-Target Report RejectNegative Var(TARGET_MDMX, 0)
+Target RejectNegative Var(TARGET_MDMX, 0)
Do not use MDMX instructions.
mno-mips16
-Target Report RejectNegative InverseMask(MIPS16)
+Target RejectNegative InverseMask(MIPS16)
Generate normal-mode code.
mno-mips3d
-Target Report RejectNegative Var(TARGET_MIPS3D, 0)
+Target RejectNegative Var(TARGET_MIPS3D, 0)
Do not use MIPS-3D instructions.
mpaired-single
-Target Report Mask(PAIRED_SINGLE_FLOAT)
+Target Mask(PAIRED_SINGLE_FLOAT)
Use paired-single floating-point instructions.
mr10k-cache-barrier=
Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
mrelax-pic-calls
-Target Report Mask(RELAX_PIC_CALLS)
+Target Mask(RELAX_PIC_CALLS)
Try to allow the linker to turn PIC calls into direct calls.
mshared
-Target Report Var(TARGET_SHARED) Init(1)
+Target Var(TARGET_SHARED) Init(1)
When generating -mabicalls code, make the code suitable for use in shared libraries.
msingle-float
-Target Report RejectNegative Mask(SINGLE_FLOAT)
+Target RejectNegative Mask(SINGLE_FLOAT)
Restrict the use of hardware floating-point instructions to 32-bit operations.
msmartmips
-Target Report Mask(SMARTMIPS)
+Target Mask(SMARTMIPS)
Use SmartMIPS instructions.
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
+Target RejectNegative Mask(SOFT_FLOAT_ABI)
Prevent the use of all hardware floating-point instructions.
msplit-addresses
-Target Report Mask(SPLIT_ADDRESSES)
+Target Mask(SPLIT_ADDRESSES)
Optimize lui/addiu address loads.
msym32
-Target Report Var(TARGET_SYM32)
+Target Var(TARGET_SYM32)
Assume all symbols have 32-bit values.
msynci
-Target Report Mask(SYNCI)
+Target Mask(SYNCI)
Use synci instruction to invalidate i-cache.
mlra
-Target Report Var(mips_lra_flag) Init(1) Save
+Target Var(mips_lra_flag) Init(1) Save
Use LRA instead of reload.
mlxc1-sxc1
-Target Report Var(mips_lxc1_sxc1) Init(1)
+Target Var(mips_lxc1_sxc1) Init(1)
Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
mmadd4
-Target Report Var(mips_madd4) Init(1)
+Target Var(mips_madd4) Init(1)
Use 4-operand madd.s/madd.d and related instructions where applicable.
mtune=
-mtune=PROCESSOR Optimize the output for PROCESSOR.
muninit-const-in-rodata
-Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
+Target Var(TARGET_UNINIT_CONST_IN_RODATA)
Put uninitialized constants in ROM (needs -membedded-data).
mvirt
-Target Report Var(TARGET_VIRT)
+Target Var(TARGET_VIRT)
Use Virtualization (VZ) instructions.
mxpa
-Target Report Var(TARGET_XPA)
+Target Var(TARGET_XPA)
Use eXtended Physical Address (XPA) instructions.
mcrc
-Target Report Var(TARGET_CRC)
+Target Var(TARGET_CRC)
Use Cyclic Redundancy Check (CRC) instructions.
mginv
-Target Report Var(TARGET_GINV)
+Target Var(TARGET_GINV)
Use Global INValidate (GINV) instructions.
mvr4130-align
-Target Report Mask(VR4130_ALIGN)
+Target Mask(VR4130_ALIGN)
Perform VR4130-specific alignment optimizations.
mxgot
-Target Report Var(TARGET_XGOT)
+Target Var(TARGET_XGOT)
Lift restrictions on GOT size.
modd-spreg
-Target Report Mask(ODD_SPREG)
+Target Mask(ODD_SPREG)
Enable use of odd-numbered single-precision registers.
mframe-header-opt
-Target Report Var(flag_frame_header_optimization) Optimization
+Target Var(flag_frame_header_optimization) Optimization
Optimize frame header.
noasmopt
Driver
mload-store-pairs
-Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1)
+Target Var(TARGET_LOAD_STORE_PAIRS) Init(1)
Enable load/store bonding.
mcompact-branches=
-Target RejectNegative JoinedOrMissing Var(mips_cb) Report Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
+Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
Specify the compact branch usage policy.
Enum
Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)
mloongson-mmi
-Target Report Mask(LOONGSON_MMI)
+Target Mask(LOONGSON_MMI)
Use Loongson MultiMedia extensions Instructions (MMI) instructions.
mloongson-ext
-Target Report Mask(LOONGSON_EXT)
+Target Mask(LOONGSON_EXT)
Use Loongson EXTension (EXT) instructions.
mloongson-ext2
-Target Report Var(TARGET_LOONGSON_EXT2)
+Target Var(TARGET_LOONGSON_EXT2)
Use Loongson EXTension R2 (EXT2) instructions.
; FIXME: Get rid of this one.
mlibfuncs
-Target Report Mask(LIBFUNC)
+Target Mask(LIBFUNC)
For intrinsics library: pass all parameters in registers.
mabi=mmixware
-Target Report RejectNegative InverseMask(ABI_GNU)
+Target RejectNegative InverseMask(ABI_GNU)
Use register stack for parameters and return value.
mabi=gnu
-Target Report RejectNegative Mask(ABI_GNU)
+Target RejectNegative Mask(ABI_GNU)
Use call-clobbered registers for parameters and return value.
; FIXME: Provide a way to *load* the epsilon register.
mepsilon
-Target Report Mask(FCMP_EPSILON)
+Target Mask(FCMP_EPSILON)
Use epsilon-respecting floating point compare instructions.
mzero-extend
-Target Report Mask(ZERO_EXTEND)
+Target Mask(ZERO_EXTEND)
Use zero-extending memory loads, not sign-extending ones.
mknuthdiv
-Target Report Mask(KNUTH_DIVISION)
+Target Mask(KNUTH_DIVISION)
Generate divide results with reminder having the same sign as the divisor (not the dividend).
mtoplevel-symbols
-Target Report Mask(TOPLEVEL_SYMBOLS)
+Target Mask(TOPLEVEL_SYMBOLS)
Prepend global symbols with \":\" (for use with PREFIX).
mno-set-program-start
-Target Report RejectNegative
+Target RejectNegative
Do not provide a default start-address 0x100 of the program.
melf
-Target Report RejectNegative
+Target RejectNegative
Link to emit program in ELF format (rather than mmo).
mbranch-predict
-Target Report RejectNegative Mask(BRANCH_PREDICT)
+Target RejectNegative Mask(BRANCH_PREDICT)
Use P-mnemonics for branches statically predicted as taken.
mno-branch-predict
-Target Report RejectNegative InverseMask(BRANCH_PREDICT)
+Target RejectNegative InverseMask(BRANCH_PREDICT)
Don't use P-mnemonics for branches.
; We use the term "base address" since that's what Knuth uses. The base
; registers, and you'll not find out until link time whether you
; should have compiled with -mno-base-addresses.
mbase-addresses
-Target Report RejectNegative Mask(BASE_ADDRESSES)
+Target RejectNegative Mask(BASE_ADDRESSES)
Use addresses that allocate global registers.
mno-base-addresses
-Target Report RejectNegative InverseMask(BASE_ADDRESSES)
+Target RejectNegative InverseMask(BASE_ADDRESSES)
Do not use addresses that allocate global registers.
msingle-exit
-Target Report RejectNegative InverseMask(USE_RETURN_INSN)
+Target RejectNegative InverseMask(USE_RETURN_INSN)
Generate a single exit point for each function.
mno-single-exit
-Target Report RejectNegative Mask(USE_RETURN_INSN)
+Target RejectNegative Mask(USE_RETURN_INSN)
Do not generate a single exit point for each function.
mset-program-start=
-Target Report RejectNegative Joined
+Target RejectNegative Joined
Set start-address of the program.
mset-data-start=
-Target Report RejectNegative Joined
+Target RejectNegative Joined
Set start-address of data.
Target the AM33/2.0 processor.
mam34
-Target Report
+Target
Target the AM34 processor.
mtune=
Tune code for the given processor.
mmult-bug
-Target Report Mask(MULT_BUG)
+Target Mask(MULT_BUG)
Work around hardware multiply bug.
; Ignored by the compiler
Enable linker relaxations.
mreturn-pointer-on-d0
-Target Report Mask(PTR_A0D0)
+Target Mask(PTR_A0D0)
Return pointers in both a0 and d0.
mliw
-Target Report Mask(ALLOW_LIW)
+Target Mask(ALLOW_LIW)
Allow gcc to generate LIW instructions.
msetlb
-Target Report Mask(ALLOW_SETLB)
+Target Mask(ALLOW_SETLB)
Allow gcc to generate the SETLB and Lcc instructions.
; <http://www.gnu.org/licenses/>.
meb
-Target RejectNegative Report InverseMask(LITTLE_ENDIAN)
+Target RejectNegative InverseMask(LITTLE_ENDIAN)
Generate big-endian code.
mel
-Target RejectNegative Report Mask(LITTLE_ENDIAN)
+Target RejectNegative Mask(LITTLE_ENDIAN)
Generate little-endian code.
mmul.x
-Target Report Mask(HAS_MULX)
+Target Mask(HAS_MULX)
Enable MUL.X and UMUL.X instructions.
; Ignored by the compiler
Use simulator runtime.
mtiny-printf
-Target Report Mask(TINY_PRINTF)
+Target Mask(TINY_PRINTF)
Use a lightweight configuration of printf and puts to reduce code size. For single-threaded applications, not requiring reentrant I/O only. Requires Newlib Nano IO.
masm-hex
Force assembly output to always use hex constants.
mmcu=
-Target Report ToLower Joined RejectNegative Var(target_mcu)
+Target ToLower Joined RejectNegative Var(target_mcu)
Specify the MCU to build for.
mwarn-mcu
-Target Report Var(msp430_warn_mcu) Init(1)
+Target Var(msp430_warn_mcu) Init(1)
Warn if an MCU name is unrecognized or conflicts with other options (default: on).
mwarn-devices-csv
-Target Report Var(msp430_warn_devices_csv) Init(1)
+Target Var(msp430_warn_devices_csv) Init(1)
Warn if devices.csv is not found or there are problem parsing it (default: on).
mcpu=
-Target Report Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT)
+Target Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT)
Specify the ISA to build for: msp430, msp430x, msp430xv2.
Enum
Enum(msp430_cpu_types) String(430xv2) Value(MSP430_CPU_MSP430XV2)
mlarge
-Target Report Mask(LARGE) RejectNegative
+Target Mask(LARGE) RejectNegative
Select large model - 20-bit addresses/pointers.
msmall
-Target Report InverseMask(LARGE) RejectNegative
+Target InverseMask(LARGE) RejectNegative
Select small model - 16-bit addresses/pointers (default).
mrelax
-Target Report
+Target
Optimize opcode sizes at link time.
mOs
Target Undocumented Mask(OPT_SPACE)
minrt
-Target Report Mask(MINRT) RejectNegative
+Target Mask(MINRT) RejectNegative
Use a minimum runtime (no static initializers or ctors) for memory-constrained devices.
HeaderInclude
config/msp430/msp430-opts.h
mhwmult=
-Target Joined RejectNegative Report ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(MSP430_HWMULT_AUTO)
+Target Joined RejectNegative ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(MSP430_HWMULT_AUTO)
Specify the type of hardware multiply to support.
Enum
Enum(msp430_hwmult_types) String(f5series) Value(MSP430_HWMULT_F5SERIES)
mcode-region=
-Target Joined RejectNegative Report ToLower Var(msp430_code_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER)
+Target Joined RejectNegative ToLower Var(msp430_code_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER)
Specify whether functions should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower).
mdata-region=
-Target Joined RejectNegative Report ToLower Var(msp430_data_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER)
+Target Joined RejectNegative ToLower Var(msp430_data_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER)
Specify whether variables should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower).
muse-lower-region-prefix
-Target Mask(USE_LOWER_REGION_PREFIX) Report
+Target Mask(USE_LOWER_REGION_PREFIX)
Add the .lower prefix to section names when compiling with -m{code,data}-region=lower (disabled by default).
Enum
Enum(msp430_regions) String(upper) Value(MSP430_REGION_UPPER)
msilicon-errata=
-Target Joined RejectNegative Report ToLower
+Target Joined RejectNegative ToLower
Passes on a request to the assembler to enable fixes for various silicon errata.
msilicon-errata-warn=
-Target Joined RejectNegative Report ToLower
+Target Joined RejectNegative ToLower
Passes on a request to the assembler to warn about various silicon errata.
mdevices-csv-loc=
-Target Joined Var(msp430_devices_csv_loc) RejectNegative Report
+Target Joined Var(msp430_devices_csv_loc) RejectNegative
The path to devices.csv. The GCC driver can normally locate devices.csv itself
and pass this option to the compiler, so the user shouldn't need to pass this.
mmax-inline-shift=
-Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65) Report
+Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65)
For shift operations by a constant amount, which require an individual instruction to shift by one
position, set the maximum number of inline shift instructions (maximum value 64) to emit instead of using the corresponding __mspabi helper function.
The default value is 4.
; ---------------------------------------------------------------
mreduced-regs
-Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
+Target RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
Use reduced-set registers for register allocation.
mfull-regs
-Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
+Target RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
Use full-set registers for register allocation.
; ---------------------------------------------------------------
Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE)
mcmov
-Target Report Mask(CMOV)
+Target Mask(CMOV)
Generate conditional move instructions.
mhw-abs
-Target Report Mask(HW_ABS)
+Target Mask(HW_ABS)
Generate hardware abs instructions.
mext-perf
-Target Report Mask(EXT_PERF)
+Target Mask(EXT_PERF)
Generate performance extension instructions.
mext-perf2
-Target Report Mask(EXT_PERF2)
+Target Mask(EXT_PERF2)
Generate performance extension version 2 instructions.
mext-string
-Target Report Mask(EXT_STRING)
+Target Mask(EXT_STRING)
Generate string extension instructions.
mext-dsp
-Target Report Mask(EXT_DSP)
+Target Mask(EXT_DSP)
Generate DSP extension instructions.
mv3push
-Target Report Mask(V3PUSH)
+Target Mask(V3PUSH)
Generate v3 push25/pop25 instructions.
m16-bit
-Target Report Mask(16_BIT)
+Target Mask(16_BIT)
Generate 16-bit instructions.
mrelax-hint
-Target Report Mask(RELAX_HINT)
+Target Mask(RELAX_HINT)
Insert relax hint for linker to do relaxation.
mvh
-Target Report Mask(VH) Condition(!TARGET_LINUX_ABI)
+Target Mask(VH) Condition(!TARGET_LINUX_ABI)
Enable Virtual Hosting support.
misr-vector-size=
Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
mctor-dtor
-Target Report
+Target
Enable constructor/destructor feature.
mrelax
-Target Report
+Target
Guide linker to relax instructions.
mext-fpu-fma
-Target Report Mask(EXT_FPU_FMA)
+Target Mask(EXT_FPU_FMA)
Generate floating-point multiply-accumulation instructions.
mext-fpu-sp
-Target Report Mask(FPU_SINGLE)
+Target Mask(FPU_SINGLE)
Generate single-precision floating-point instructions.
mext-fpu-dp
-Target Report Mask(FPU_DOUBLE)
+Target Mask(FPU_DOUBLE)
Generate double-precision floating-point instructions.
mforce-no-ext-dsp
-Target Undocumented Report Mask(FORCE_NO_EXT_DSP)
+Target Undocumented Mask(FORCE_NO_EXT_DSP)
Force disable hardware loop, even use -mext-dsp.
msched-prolog-epilog
Always save $lp in the stack.
munaligned-access
-Target Report Var(flag_unaligned_access) Init(0)
+Target Var(flag_unaligned_access) Init(0)
Enable unaligned word and halfword accesses to packed data.
minline-asm-r15
-Target Report Var(flag_inline_asm_r15) Init(0)
+Target Var(flag_inline_asm_r15) Init(0)
Allow use r15 for inline ASM.
; toolchains.
msmallc
-Target Report RejectNegative
+Target RejectNegative
Link with a limited version of the C library.
msys-lib=
Name of the startfile.
mhal
-Target Report RejectNegative
+Target RejectNegative
Link with HAL BSP.
int saved_custom_code_index[256]
mhw-div
-Target Report Mask(HAS_DIV)
+Target Mask(HAS_DIV)
Enable DIV, DIVU.
mhw-mul
-Target Report Mask(HAS_MUL)
+Target Mask(HAS_MUL)
Enable MUL instructions.
mhw-mulx
-Target Report Mask(HAS_MULX)
+Target Mask(HAS_MULX)
Enable MULX instructions, assume fast shifter.
mfast-sw-div
-Target Report Mask(FAST_SW_DIV)
+Target Mask(FAST_SW_DIV)
Use table based fast divide (default at -O3).
mbypass-cache
-Target Report Mask(BYPASS_CACHE)
+Target Mask(BYPASS_CACHE)
All memory accesses use I/O load/store instructions.
mno-cache-volatile
-Target Report RejectNegative Mask(BYPASS_CACHE_VOLATILE)
+Target RejectNegative Mask(BYPASS_CACHE_VOLATILE)
Volatile memory accesses use I/O load/store instructions.
mcache-volatile
-Target Report RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE)
+Target RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE)
Volatile memory accesses do not use I/O load/store instructions.
mgpopt=
Enum(nios2_gpopt_type) String(all) Value(gpopt_all)
mgpopt
-Target Report RejectNegative Var(nios2_gpopt_option, gpopt_local)
+Target RejectNegative Var(nios2_gpopt_option, gpopt_local)
Equivalent to -mgpopt=local.
mno-gpopt
-Target Report RejectNegative Var(nios2_gpopt_option, gpopt_none)
+Target RejectNegative Var(nios2_gpopt_option, gpopt_none)
Equivalent to -mgpopt=none.
meb
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order.
mel
-Target Report RejectNegative InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Use little-endian byte order.
mcustom-fpu-cfg=
Floating point custom instruction configuration name.
mno-custom-ftruncds
-Target Report RejectNegative Var(nios2_custom_ftruncds, -1)
+Target RejectNegative Var(nios2_custom_ftruncds, -1)
Do not use the ftruncds custom instruction.
mcustom-ftruncds=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1)
Integer id (N) of ftruncds custom instruction.
mno-custom-fextsd
-Target Report RejectNegative Var(nios2_custom_fextsd, -1)
+Target RejectNegative Var(nios2_custom_fextsd, -1)
Do not use the fextsd custom instruction.
mcustom-fextsd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1)
Integer id (N) of fextsd custom instruction.
mno-custom-fixdu
-Target Report RejectNegative Var(nios2_custom_fixdu, -1)
+Target RejectNegative Var(nios2_custom_fixdu, -1)
Do not use the fixdu custom instruction.
mcustom-fixdu=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1)
Integer id (N) of fixdu custom instruction.
mno-custom-fixdi
-Target Report RejectNegative Var(nios2_custom_fixdi, -1)
+Target RejectNegative Var(nios2_custom_fixdi, -1)
Do not use the fixdi custom instruction.
mcustom-fixdi=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1)
Integer id (N) of fixdi custom instruction.
mno-custom-fixsu
-Target Report RejectNegative Var(nios2_custom_fixsu, -1)
+Target RejectNegative Var(nios2_custom_fixsu, -1)
Do not use the fixsu custom instruction.
mcustom-fixsu=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1)
Integer id (N) of fixsu custom instruction.
mno-custom-fixsi
-Target Report RejectNegative Var(nios2_custom_fixsi, -1)
+Target RejectNegative Var(nios2_custom_fixsi, -1)
Do not use the fixsi custom instruction.
mcustom-fixsi=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1)
Integer id (N) of fixsi custom instruction.
mno-custom-floatud
-Target Report RejectNegative Var(nios2_custom_floatud, -1)
+Target RejectNegative Var(nios2_custom_floatud, -1)
Do not use the floatud custom instruction.
mcustom-floatud=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1)
Integer id (N) of floatud custom instruction.
mno-custom-floatid
-Target Report RejectNegative Var(nios2_custom_floatid, -1)
+Target RejectNegative Var(nios2_custom_floatid, -1)
Do not use the floatid custom instruction.
mcustom-floatid=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1)
Integer id (N) of floatid custom instruction.
mno-custom-floatus
-Target Report RejectNegative Var(nios2_custom_floatus, -1)
+Target RejectNegative Var(nios2_custom_floatus, -1)
Do not use the floatus custom instruction.
mcustom-floatus=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1)
Integer id (N) of floatus custom instruction.
mno-custom-floatis
-Target Report RejectNegative Var(nios2_custom_floatis, -1)
+Target RejectNegative Var(nios2_custom_floatis, -1)
Do not use the floatis custom instruction.
mcustom-floatis=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1)
Integer id (N) of floatis custom instruction.
mno-custom-fcmpned
-Target Report RejectNegative Var(nios2_custom_fcmpned, -1)
+Target RejectNegative Var(nios2_custom_fcmpned, -1)
Do not use the fcmpned custom instruction.
mcustom-fcmpned=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1)
Integer id (N) of fcmpned custom instruction.
mno-custom-fcmpeqd
-Target Report RejectNegative Var(nios2_custom_fcmpeqd, -1)
+Target RejectNegative Var(nios2_custom_fcmpeqd, -1)
Do not use the fcmpeqd custom instruction.
mcustom-fcmpeqd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1)
Integer id (N) of fcmpeqd custom instruction.
mno-custom-fcmpged
-Target Report RejectNegative Var(nios2_custom_fcmpged, -1)
+Target RejectNegative Var(nios2_custom_fcmpged, -1)
Do not use the fcmpged custom instruction.
mcustom-fcmpged=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1)
Integer id (N) of fcmpged custom instruction.
mno-custom-fcmpgtd
-Target Report RejectNegative Var(nios2_custom_fcmpgtd, -1)
+Target RejectNegative Var(nios2_custom_fcmpgtd, -1)
Do not use the fcmpgtd custom instruction.
mcustom-fcmpgtd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1)
Integer id (N) of fcmpgtd custom instruction.
mno-custom-fcmpled
-Target Report RejectNegative Var(nios2_custom_fcmpled, -1)
+Target RejectNegative Var(nios2_custom_fcmpled, -1)
Do not use the fcmpled custom instruction.
mcustom-fcmpled=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1)
Integer id (N) of fcmpled custom instruction.
mno-custom-fcmpltd
-Target Report RejectNegative Var(nios2_custom_fcmpltd, -1)
+Target RejectNegative Var(nios2_custom_fcmpltd, -1)
Do not use the fcmpltd custom instruction.
mcustom-fcmpltd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1)
Integer id (N) of fcmpltd custom instruction.
mno-custom-flogd
-Target Report RejectNegative Var(nios2_custom_flogd, -1)
+Target RejectNegative Var(nios2_custom_flogd, -1)
Do not use the flogd custom instruction.
mcustom-flogd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1)
Integer id (N) of flogd custom instruction.
mno-custom-fexpd
-Target Report RejectNegative Var(nios2_custom_fexpd, -1)
+Target RejectNegative Var(nios2_custom_fexpd, -1)
Do not use the fexpd custom instruction.
mcustom-fexpd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1)
Integer id (N) of fexpd custom instruction.
mno-custom-fatand
-Target Report RejectNegative Var(nios2_custom_fatand, -1)
+Target RejectNegative Var(nios2_custom_fatand, -1)
Do not use the fatand custom instruction.
mcustom-fatand=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1)
Integer id (N) of fatand custom instruction.
mno-custom-ftand
-Target Report RejectNegative Var(nios2_custom_ftand, -1)
+Target RejectNegative Var(nios2_custom_ftand, -1)
Do not use the ftand custom instruction.
mcustom-ftand=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1)
Integer id (N) of ftand custom instruction.
mno-custom-fsind
-Target Report RejectNegative Var(nios2_custom_fsind, -1)
+Target RejectNegative Var(nios2_custom_fsind, -1)
Do not use the fsind custom instruction.
mcustom-fsind=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1)
Integer id (N) of fsind custom instruction.
mno-custom-fcosd
-Target Report RejectNegative Var(nios2_custom_fcosd, -1)
+Target RejectNegative Var(nios2_custom_fcosd, -1)
Do not use the fcosd custom instruction.
mcustom-fcosd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1)
Integer id (N) of fcosd custom instruction.
mno-custom-fsqrtd
-Target Report RejectNegative Var(nios2_custom_fsqrtd, -1)
+Target RejectNegative Var(nios2_custom_fsqrtd, -1)
Do not use the fsqrtd custom instruction.
mcustom-fsqrtd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1)
Integer id (N) of fsqrtd custom instruction.
mno-custom-fabsd
-Target Report RejectNegative Var(nios2_custom_fabsd, -1)
+Target RejectNegative Var(nios2_custom_fabsd, -1)
Do not use the fabsd custom instruction.
mcustom-fabsd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1)
Integer id (N) of fabsd custom instruction.
mno-custom-fnegd
-Target Report RejectNegative Var(nios2_custom_fnegd, -1)
+Target RejectNegative Var(nios2_custom_fnegd, -1)
Do not use the fnegd custom instruction.
mcustom-fnegd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1)
Integer id (N) of fnegd custom instruction.
mno-custom-fmaxd
-Target Report RejectNegative Var(nios2_custom_fmaxd, -1)
+Target RejectNegative Var(nios2_custom_fmaxd, -1)
Do not use the fmaxd custom instruction.
mcustom-fmaxd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1)
Integer id (N) of fmaxd custom instruction.
mno-custom-fmind
-Target Report RejectNegative Var(nios2_custom_fmind, -1)
+Target RejectNegative Var(nios2_custom_fmind, -1)
Do not use the fmind custom instruction.
mcustom-fmind=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1)
Integer id (N) of fmind custom instruction.
mno-custom-fdivd
-Target Report RejectNegative Var(nios2_custom_fdivd, -1)
+Target RejectNegative Var(nios2_custom_fdivd, -1)
Do not use the fdivd custom instruction.
mcustom-fdivd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1)
Integer id (N) of fdivd custom instruction.
mno-custom-fmuld
-Target Report RejectNegative Var(nios2_custom_fmuld, -1)
+Target RejectNegative Var(nios2_custom_fmuld, -1)
Do not use the fmuld custom instruction.
mcustom-fmuld=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1)
Integer id (N) of fmuld custom instruction.
mno-custom-fsubd
-Target Report RejectNegative Var(nios2_custom_fsubd, -1)
+Target RejectNegative Var(nios2_custom_fsubd, -1)
Do not use the fsubd custom instruction.
mcustom-fsubd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1)
Integer id (N) of fsubd custom instruction.
mno-custom-faddd
-Target Report RejectNegative Var(nios2_custom_faddd, -1)
+Target RejectNegative Var(nios2_custom_faddd, -1)
Do not use the faddd custom instruction.
mcustom-faddd=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1)
Integer id (N) of faddd custom instruction.
mno-custom-fcmpnes
-Target Report RejectNegative Var(nios2_custom_fcmpnes, -1)
+Target RejectNegative Var(nios2_custom_fcmpnes, -1)
Do not use the fcmpnes custom instruction.
mcustom-fcmpnes=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1)
Integer id (N) of fcmpnes custom instruction.
mno-custom-fcmpeqs
-Target Report RejectNegative Var(nios2_custom_fcmpeqs, -1)
+Target RejectNegative Var(nios2_custom_fcmpeqs, -1)
Do not use the fcmpeqs custom instruction.
mcustom-fcmpeqs=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1)
Integer id (N) of fcmpeqs custom instruction.
mno-custom-fcmpges
-Target Report RejectNegative Var(nios2_custom_fcmpges, -1)
+Target RejectNegative Var(nios2_custom_fcmpges, -1)
Do not use the fcmpges custom instruction.
mcustom-fcmpges=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1)
Integer id (N) of fcmpges custom instruction.
mno-custom-fcmpgts
-Target Report RejectNegative Var(nios2_custom_fcmpgts, -1)
+Target RejectNegative Var(nios2_custom_fcmpgts, -1)
Do not use the fcmpgts custom instruction.
mcustom-fcmpgts=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1)
Integer id (N) of fcmpgts custom instruction.
mno-custom-fcmples
-Target Report RejectNegative Var(nios2_custom_fcmples, -1)
+Target RejectNegative Var(nios2_custom_fcmples, -1)
Do not use the fcmples custom instruction.
mcustom-fcmples=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1)
Integer id (N) of fcmples custom instruction.
mno-custom-fcmplts
-Target Report RejectNegative Var(nios2_custom_fcmplts, -1)
+Target RejectNegative Var(nios2_custom_fcmplts, -1)
Do not use the fcmplts custom instruction.
mcustom-fcmplts=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1)
Integer id (N) of fcmplts custom instruction.
mno-custom-flogs
-Target Report RejectNegative Var(nios2_custom_flogs, -1)
+Target RejectNegative Var(nios2_custom_flogs, -1)
Do not use the flogs custom instruction.
mcustom-flogs=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1)
Integer id (N) of flogs custom instruction.
mno-custom-fexps
-Target Report RejectNegative Var(nios2_custom_fexps, -1)
+Target RejectNegative Var(nios2_custom_fexps, -1)
Do not use the fexps custom instruction.
mcustom-fexps=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1)
Integer id (N) of fexps custom instruction.
mno-custom-fatans
-Target Report RejectNegative Var(nios2_custom_fatans, -1)
+Target RejectNegative Var(nios2_custom_fatans, -1)
Do not use the fatans custom instruction.
mcustom-fatans=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1)
Integer id (N) of fatans custom instruction.
mno-custom-ftans
-Target Report RejectNegative Var(nios2_custom_ftans, -1)
+Target RejectNegative Var(nios2_custom_ftans, -1)
Do not use the ftans custom instruction.
mcustom-ftans=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1)
Integer id (N) of ftans custom instruction.
mno-custom-fsins
-Target Report RejectNegative Var(nios2_custom_fsins, -1)
+Target RejectNegative Var(nios2_custom_fsins, -1)
Do not use the fsins custom instruction.
mcustom-fsins=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1)
Integer id (N) of fsins custom instruction.
mno-custom-fcoss
-Target Report RejectNegative Var(nios2_custom_fcoss, -1)
+Target RejectNegative Var(nios2_custom_fcoss, -1)
Do not use the fcoss custom instruction.
mcustom-fcoss=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1)
Integer id (N) of fcoss custom instruction.
mno-custom-fsqrts
-Target Report RejectNegative Var(nios2_custom_fsqrts, -1)
+Target RejectNegative Var(nios2_custom_fsqrts, -1)
Do not use the fsqrts custom instruction.
mcustom-fsqrts=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1)
Integer id (N) of fsqrts custom instruction.
mno-custom-fabss
-Target Report RejectNegative Var(nios2_custom_fabss, -1)
+Target RejectNegative Var(nios2_custom_fabss, -1)
Do not use the fabss custom instr.
mcustom-fabss=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1)
Integer id (N) of fabss custom instruction.
mno-custom-fnegs
-Target Report RejectNegative Var(nios2_custom_fnegs, -1)
+Target RejectNegative Var(nios2_custom_fnegs, -1)
Do not use the fnegs custom instruction.
mcustom-fnegs=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1)
Integer id (N) of fnegs custom instruction.
mno-custom-fmaxs
-Target Report RejectNegative Var(nios2_custom_fmaxs, -1)
+Target RejectNegative Var(nios2_custom_fmaxs, -1)
Do not use the fmaxs custom instruction.
mcustom-fmaxs=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1)
Integer id (N) of fmaxs custom instruction.
mno-custom-fmins
-Target Report RejectNegative Var(nios2_custom_fmins, -1)
+Target RejectNegative Var(nios2_custom_fmins, -1)
Do not use the fmins custom instruction.
mcustom-fmins=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1)
Integer id (N) of fmins custom instruction.
mno-custom-fdivs
-Target Report RejectNegative Var(nios2_custom_fdivs, -1)
+Target RejectNegative Var(nios2_custom_fdivs, -1)
Do not use the fdivs custom instruction.
mcustom-fdivs=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1)
Integer id (N) of fdivs custom instruction.
mno-custom-fmuls
-Target Report RejectNegative Var(nios2_custom_fmuls, -1)
+Target RejectNegative Var(nios2_custom_fmuls, -1)
Do not use the fmuls custom instruction.
mcustom-fmuls=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1)
Integer id (N) of fmuls custom instruction.
mno-custom-fsubs
-Target Report RejectNegative Var(nios2_custom_fsubs, -1)
+Target RejectNegative Var(nios2_custom_fsubs, -1)
Do not use the fsubs custom instruction.
mcustom-fsubs=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1)
Integer id (N) of fsubs custom instruction.
mno-custom-fadds
-Target Report RejectNegative Var(nios2_custom_fadds, -1)
+Target RejectNegative Var(nios2_custom_fadds, -1)
Do not use the fadds custom instruction.
mcustom-fadds=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1)
Integer id (N) of fadds custom instruction.
mno-custom-frdy
-Target Report RejectNegative Var(nios2_custom_frdy, -1)
+Target RejectNegative Var(nios2_custom_frdy, -1)
Do not use the frdy custom instruction.
mcustom-frdy=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1)
Integer id (N) of frdy custom instruction.
mno-custom-frdxhi
-Target Report RejectNegative Var(nios2_custom_frdxhi, -1)
+Target RejectNegative Var(nios2_custom_frdxhi, -1)
Do not use the frdxhi custom instruction.
mcustom-frdxhi=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1)
Integer id (N) of frdxhi custom instruction.
mno-custom-frdxlo
-Target Report RejectNegative Var(nios2_custom_frdxlo, -1)
+Target RejectNegative Var(nios2_custom_frdxlo, -1)
Do not use the frdxlo custom instruction.
mcustom-frdxlo=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1)
Integer id (N) of frdxlo custom instruction.
mno-custom-fwry
-Target Report RejectNegative Var(nios2_custom_fwry, -1)
+Target RejectNegative Var(nios2_custom_fwry, -1)
Do not use the fwry custom instruction.
mcustom-fwry=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1)
Integer id (N) of fwry custom instruction.
mno-custom-fwrx
-Target Report RejectNegative Var(nios2_custom_fwrx, -1)
+Target RejectNegative Var(nios2_custom_fwrx, -1)
Do not use the fwrx custom instruction.
mcustom-fwrx=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1)
Integer id (N) of fwrx custom instruction.
mno-custom-round
-Target Report RejectNegative Var(nios2_custom_round, -1)
+Target RejectNegative Var(nios2_custom_round, -1)
Do not use the round custom instruction.
mcustom-round=
-Target Report RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1)
+Target RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1)
Integer id (N) of round custom instruction.
march=
Enum(nios2_arch_type) String(r2) Value(ARCH_R2)
mbmx
-Target Report Mask(HAS_BMX)
+Target Mask(HAS_BMX)
Enable generation of R2 BMX instructions.
mcdx
-Target Report Mask(HAS_CDX)
+Target Mask(HAS_CDX)
Enable generation of R2 CDX instructions.
mgprel-sec=
; It's not clear whether this was ever build/tested/used, so this is no longer
; exposed to the user.
;m32
-;Target Report RejectNegative InverseMask(ABI64)
+;Target RejectNegative InverseMask(ABI64)
;Generate code for a 32-bit ABI.
m64
-Target Report RejectNegative Mask(ABI64)
+Target RejectNegative Mask(ABI64)
Generate code for a 64-bit ABI.
mmainkernel
-Target Report RejectNegative
+Target RejectNegative
Link in code for a __main kernel.
moptimize
-Target Report Var(nvptx_optimize) Init(-1)
+Target Var(nvptx_optimize) Init(-1)
Optimize partition neutering.
msoft-stack
-Target Report Mask(SOFT_STACK)
+Target Mask(SOFT_STACK)
Use custom stacks instead of local memory for automatic storage.
msoft-stack-reserve-local=
-Target Report Joined RejectNegative UInteger Var(nvptx_softstack_size) Init(128)
+Target Joined RejectNegative UInteger Var(nvptx_softstack_size) Init(128)
Specify size of .local memory used for stack when the exact amount is not known.
muniform-simt
-Target Report Mask(UNIFORM_SIMT)
+Target Mask(UNIFORM_SIMT)
Generate code that can keep local state uniform across all lanes.
mgomp
-Target Report Mask(GOMP)
+Target Mask(GOMP)
Generate code for OpenMP offloading: enables -msoft-stack and -muniform-simt.
Enum
Does nothing. Preserved for backward compatibility.
mcaller-copies
-Target Report Mask(CALLER_COPIES)
+Target Mask(CALLER_COPIES)
Caller copies function arguments passed by hidden reference.
mcoherent-ldcw
-Target Report Var(TARGET_COHERENT_LDCW) Init(1)
+Target Var(TARGET_COHERENT_LDCW) Init(1)
Use ldcw/ldcd coherent cache-control hint.
mdisable-fpregs
-Target Report Mask(DISABLE_FPREGS)
+Target Mask(DISABLE_FPREGS)
Disable FP regs.
mdisable-indexing
-Target Report Mask(DISABLE_INDEXING)
+Target Mask(DISABLE_INDEXING)
Disable indexed addressing.
mfast-indirect-calls
-Target Report Mask(FAST_INDIRECT_CALLS)
+Target Mask(FAST_INDIRECT_CALLS)
Generate fast indirect calls.
mfixed-range=
Specify range of registers to make fixed.
mgas
-Target Report Mask(GAS)
+Target Mask(GAS)
Assume code will be assembled by GAS.
mjump-in-delay
Enable linker optimizations.
mlong-calls
-Target Report Mask(LONG_CALLS)
+Target Mask(LONG_CALLS)
Always generate long calls.
mlong-load-store
-Target Report Mask(LONG_LOAD_STORE)
+Target Mask(LONG_LOAD_STORE)
Emit long load/store sequences.
mnosnake
Generate PA1.0 code.
mno-space-regs
-Target RejectNegative Report Mask(NO_SPACE_REGS)
+Target RejectNegative Mask(NO_SPACE_REGS)
Disable space regs.
mordered
-Target Report Var(TARGET_ORDERED) Init(0)
+Target Var(TARGET_ORDERED) Init(0)
Assume memory references are ordered and barriers are not needed.
mpa-risc-1-0
Generate PA2.0 code (requires binutils 2.10 or later).
mportable-runtime
-Target Report Mask(PORTABLE_RUNTIME)
+Target Mask(PORTABLE_RUNTIME)
Use portable calling conventions.
mschedule=
Enum(pa_schedule) String(7300) Value(PROCESSOR_7300)
msoft-float
-Target Report Mask(SOFT_FLOAT)
+Target Mask(SOFT_FLOAT)
Use software floating point.
msnake
Generate PA1.1 code.
mspace-regs
-Target RejectNegative Report InverseMask(NO_SPACE_REGS)
+Target RejectNegative InverseMask(NO_SPACE_REGS)
Do not disable space regs.
Generate code for an 11/10.
m40
-Target Report Mask(40)
+Target Mask(40)
Generate code for an 11/40.
m45
-Target Report Mask(45)
+Target Mask(45)
Generate code for an 11/45.
mac0
-Target Report Mask(AC0)
+Target Mask(AC0)
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
mdec-asm
-Target RejectNegative Report Mask(DEC_ASM) Negative(mgnu-asm)
+Target RejectNegative Mask(DEC_ASM) Negative(mgnu-asm)
Use the DEC assembler syntax.
mgnu-asm
-Target RejectNegative Report Mask(GNU_ASM) Negative(munix-asm)
+Target RejectNegative Mask(GNU_ASM) Negative(munix-asm)
Use the GNU assembler syntax.
mfpu
-Target RejectNegative Report Mask(FPU)
+Target RejectNegative Mask(FPU)
Use hardware floating point.
mint16
-Target Report InverseMask(INT32, INT16)
+Target InverseMask(INT32, INT16)
Use 16 bit int.
mint32
-Target Report Mask(INT32)
+Target Mask(INT32)
Use 32 bit int.
msoft-float
-Target RejectNegative Report InverseMask(FPU, SOFT_FLOAT)
+Target RejectNegative InverseMask(FPU, SOFT_FLOAT)
Do not use hardware floating point.
msplit
-Target Report Mask(SPLIT)
+Target Mask(SPLIT)
Target has split I&D.
munix-asm
-Target RejectNegative Report Mask(UNIX_ASM) Negative(mdec-asm)
+Target RejectNegative Mask(UNIX_ASM) Negative(mdec-asm)
Use UNIX assembler syntax.
mlra
-Target Report Mask(LRA)
+Target Mask(LRA)
Use LRA register allocator.
config/pru/pru-opts.h
minrt
-Target Report Mask(MINRT) RejectNegative
+Target Mask(MINRT) RejectNegative
Use a minimum runtime (no static initializers or ctors) for memory-constrained
devices.
-mmcu=MCU Select the target System-On-Chip variant that embeds this PRU.
mno-relax
-Target Report RejectNegative
+Target RejectNegative
Make GCC pass the --no-relax command-line option to the linker instead of
the --relax option.
Allow (or do not allow) gcc to use the LOOP instruction.
mabi=
-Target RejectNegative Report Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save
+Target RejectNegative Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save
Select target ABI variant.
Enum
-mbranch-cost=N Set the cost of branches to roughly N instructions.
mplt
-Target Report Var(TARGET_PLT) Init(1)
+Target Var(TARGET_PLT) Init(1)
When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
mabi=
-Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32)
+Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32)
Specify integer and floating-point calling convention.
mpreferred-stack-boundary=
Enum(abi_type) String(lp64d) Value(ABI_LP64D)
mfdiv
-Target Report Mask(FDIV)
+Target Mask(FDIV)
Use hardware floating-point divide and square root instructions.
mdiv
-Target Report Mask(DIV)
+Target Mask(DIV)
Use hardware instructions for integer division.
march=
-Target Report RejectNegative Joined
+Target RejectNegative Joined
-march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be
lower-case.
-msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets).
msave-restore
-Target Report Mask(SAVE_RESTORE)
+Target Mask(SAVE_RESTORE)
Use smaller but slower prologue and epilogue code.
mshorten-memrefs
32-bit integer load/stores.
mcmodel=
-Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
+Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
Specify the code model.
mstrict-align
-Target Report Mask(STRICT_ALIGN) Save
+Target Mask(STRICT_ALIGN) Save
Do not generate unaligned memory accesses.
Enum
Enum(code_model) String(medany) Value(CM_MEDANY)
mexplicit-relocs
-Target Report Mask(EXPLICIT_RELOCS)
+Target Mask(EXPLICIT_RELOCS)
Use %reloc() operators, rather than assembly macros, to load addresses.
mrelax
Mask(RVE)
mriscv-attribute
-Target Report Var(riscv_emit_attribute_p) Init(-1)
+Target Var(riscv_emit_attribute_p) Init(-1)
Emit RISC-V ELF attribute.
malign-data=
Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)
misa-spec=
-Target Report RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
+Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
Set the version of RISC-V ISA spec.
config/rl78/rl78-opts.h
msim
-Target Report
+Target
Use the simulator runtime.
mmul=
-Target RejectNegative Joined Var(rl78_mul_type) Report Tolower Enum(rl78_mul_types) Init(MUL_UNINIT)
+Target RejectNegative Joined Var(rl78_mul_type) Tolower Enum(rl78_mul_types) Init(MUL_UNINIT)
Selects the type of hardware multiplication and division to use (none/g13/g14).
Enum
Enum(rl78_mul_types) String(rl78) Value(MUL_G14)
mallregs
-Target Mask(ALLREGS) Report Optimization
+Target Mask(ALLREGS) Optimization
Use all registers, reserving none for interrupt handlers.
mrelax
-Target Report Optimization
+Target Optimization
Enable assembler and linker relaxation. Enabled by default at -Os.
mcpu=
-Target RejectNegative Joined Var(rl78_cpu_type) Report ToLower Enum(rl78_cpu_types) Init(CPU_UNINIT)
+Target RejectNegative Joined Var(rl78_cpu_type) ToLower Enum(rl78_cpu_types) Init(CPU_UNINIT)
Selects the type of RL78 core being targeted (g10/g13/g14). The default is the G14. If set, also selects the hardware multiply support to be used.
Enum
Enum(rl78_cpu_types) String(rl78) Value(CPU_G14)
mg10
-Target RejectNegative Report Alias(mcpu=, g10)
+Target RejectNegative Alias(mcpu=, g10)
Alias for -mcpu=g10.
mg13
-Target RejectNegative Report Alias(mcpu=, g13)
+Target RejectNegative Alias(mcpu=, g13)
Alias for -mcpu=g13.
mg14
-Target RejectNegative Report Alias(mcpu=, g14)
+Target RejectNegative Alias(mcpu=, g14)
Alias for -mcpu=g14.
mrl78
-Target RejectNegative Report Alias(mcpu=, g14)
+Target RejectNegative Alias(mcpu=, g14)
Alias for -mcpu=g14.
mes0
; <http://www.gnu.org/licenses/>.
maix64
-Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
+Target RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
Compile for 64-bit pointers.
maix32
-Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
+Target RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
Compile for 32-bit pointers.
mcmodel=
Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE)
mpe
-Target Report RejectNegative Var(internal_nothing_1) Save
+Target RejectNegative Var(internal_nothing_1) Save
Support message passing with the Parallel Environment.
posix
; <http://www.gnu.org/licenses/>.
mprofile-kernel
-Target Report Var(profile_kernel) Save
+Target Var(profile_kernel) Save
Call mcount for profiling before a function prologue.
mcmodel=
Target RejectNegative Undocumented Ignore
mpowerpc64
-Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
+Target Mask(POWERPC64) Var(rs6000_isa_flags)
Use PowerPC-64 instruction set.
mpowerpc-gpopt
-Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
+Target Mask(PPC_GPOPT) Var(rs6000_isa_flags)
Use PowerPC General Purpose group optional instructions.
mpowerpc-gfxopt
-Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
+Target Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
Use PowerPC Graphics group optional instructions.
mmfcrf
-Target Report Mask(MFCRF) Var(rs6000_isa_flags)
+Target Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction.
mpopcntb
-Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
+Target Mask(POPCNTB) Var(rs6000_isa_flags)
Use PowerPC V2.02 popcntb instruction.
mfprnd
-Target Report Mask(FPRND) Var(rs6000_isa_flags)
+Target Mask(FPRND) Var(rs6000_isa_flags)
Use PowerPC V2.02 floating point rounding instructions.
mcmpb
-Target Report Mask(CMPB) Var(rs6000_isa_flags)
+Target Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction.
;; This option existed in the past, but now is always off.
Target RejectNegative Undocumented WarnRemoved
maltivec
-Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
+Target Mask(ALTIVEC) Var(rs6000_isa_flags)
Use AltiVec instructions.
mfold-gimple
-Target Report Var(rs6000_fold_gimple) Init(1)
+Target Var(rs6000_fold_gimple) Init(1)
Enable early gimple folding of builtins.
mhard-dfp
-Target Report Mask(DFP) Var(rs6000_isa_flags)
+Target Mask(DFP) Var(rs6000_isa_flags)
Use decimal floating point instructions.
mmulhw
-Target Report Mask(MULHW) Var(rs6000_isa_flags)
+Target Mask(MULHW) Var(rs6000_isa_flags)
Use 4xx half-word multiply instructions.
mdlmzb
-Target Report Mask(DLMZB) Var(rs6000_isa_flags)
+Target Mask(DLMZB) Var(rs6000_isa_flags)
Use 4xx string-search dlmzb instruction.
mmultiple
-Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
+Target Mask(MULTIPLE) Var(rs6000_isa_flags)
Generate load/store multiple instructions.
;; This option existed in the past, but now is always off.
Target RejectNegative Undocumented WarnRemoved
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
+Target RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
Do not use hardware floating point.
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
+Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point.
mpopcntd
-Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
+Target Mask(POPCNTD) Var(rs6000_isa_flags)
Use PowerPC V2.06 popcntd instruction.
mfriz
-Target Report Var(TARGET_FRIZ) Init(-1) Save
+Target Var(TARGET_FRIZ) Init(-1) Save
Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
mveclibabi=
Vector library ABI to use.
mvsx
-Target Report Mask(VSX) Var(rs6000_isa_flags)
+Target Mask(VSX) Var(rs6000_isa_flags)
Use vector/scalar (VSX) instructions.
mvsx-align-128
-Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
+Target Undocumented Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64
mallow-movmisalign
; Allow the movmisalign in DF/DI vectors
mefficient-unaligned-vsx
-Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
+Target Undocumented Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
; Consider unaligned VSX vector and fp accesses to be efficient
msched-groups
-Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
+Target Undocumented Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set rs6000_sched_groups
malways-hint
-Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
+Target Undocumented Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set rs6000_always_hint
malign-branch-targets
-Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
+Target Undocumented Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set rs6000_align_branch_targets
mno-update
-Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
+Target RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
Do not generate load/store with update instructions.
mupdate
-Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
+Target RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
Generate load/store with update instructions.
msingle-pic-base
-Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
+Target Var(TARGET_SINGLE_PIC_BASE) Init(0)
Do not load the PIC register in function prologues.
mavoid-indexed-addresses
-Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
+Target Var(TARGET_AVOID_XFORM) Init(-1) Save
Avoid generation of indexed load/store instructions when possible.
msched-epilog
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
msched-prolog
-Target Report Var(TARGET_SCHED_PROLOG) Save
+Target Var(TARGET_SCHED_PROLOG) Save
Schedule the start and end of the procedure.
maix-struct-return
-Target Report RejectNegative Var(aix_struct_return) Save
+Target RejectNegative Var(aix_struct_return) Save
Return all structures in memory (AIX default).
msvr4-struct-return
-Target Report RejectNegative Var(aix_struct_return,0) Save
+Target RejectNegative Var(aix_struct_return,0) Save
Return small structures in registers (SVR4 default).
mxl-compat
-Target Report Var(TARGET_XL_COMPAT) Save
+Target Var(TARGET_XL_COMPAT) Save
Conform more closely to IBM XLC semantics.
mrecip
-Target Report
+Target
Generate software reciprocal divide and square root for better throughput.
mrecip=
-Target Report RejectNegative Joined Var(rs6000_recip_name)
+Target RejectNegative Joined Var(rs6000_recip_name)
Generate software reciprocal divide and square root for better throughput.
mrecip-precision
-Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
+Target Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
Assume that the reciprocal estimate instructions provide more accuracy.
mno-fp-in-toc
-Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
+Target RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
Do not place floating point constants in TOC.
mfp-in-toc
-Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
+Target RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
Place floating point constants in TOC.
mno-sum-in-toc
; This is at the cost of having 2 extra loads and one extra store per
; function, and one less allocable register.
mminimal-toc
-Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
+Target Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
Use only one TOC entry per procedure.
mfull-toc
-Target Report
+Target
Put everything in the regular TOC.
mvrsave
-Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
+Target Var(TARGET_ALTIVEC_VRSAVE) Save
Generate VRSAVE instructions when generating AltiVec code.
mvrsave=no
Deprecated option. Use -mvrsave instead.
mblock-move-inline-limit=
-Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
+Target Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
Max number of bytes to move inline.
mblock-ops-unaligned-vsx
-Target Report Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags)
+Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags)
Generate unaligned VSX load/store for inline expansion of memcpy/memmove.
mblock-ops-vector-pair
Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove.
mblock-compare-inline-limit=
-Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
+Target Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
Max number of bytes to compare without loops.
mblock-compare-inline-loop-limit=
-Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
+Target Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
Max number of bytes to compare with loops.
mstring-compare-inline-limit=
-Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
+Target Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
Max number of bytes to compare.
misel
-Target Report Mask(ISEL) Var(rs6000_isa_flags)
+Target Mask(ISEL) Var(rs6000_isa_flags)
Generate isel instructions.
mdebug=
Enum(rs6000_traceback_type) String(no) Value(traceback_none)
mlongcall
-Target Report Var(rs6000_default_long_calls) Save
+Target Var(rs6000_default_long_calls) Save
Avoid all range limits on call instructions.
; This option existed in the past, but now is always on.
Specify scheduling priority for dispatch slot restricted insns.
mpointers-to-nested-functions
-Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
+Target Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use r11 to hold the static link in calls to functions via pointers.
msave-toc-indirect
-Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
+Target Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Save the TOC in the prologue for indirect calls rather than inline.
; This option existed in the past, but now is always the same as -mvsx.
Target RejectNegative Undocumented Ignore
mpower8-fusion
-Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
+Target Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8.
mpower8-fusion-sign
Allow sign extension in fusion operations.
mpower8-vector
-Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
+Target Mask(P8_VECTOR) Var(rs6000_isa_flags)
Use vector and scalar instructions added in ISA 2.07.
mcrypto
-Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
+Target Mask(CRYPTO) Var(rs6000_isa_flags)
Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
mdirect-move
Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved
mhtm
-Target Report Mask(HTM) Var(rs6000_isa_flags)
+Target Mask(HTM) Var(rs6000_isa_flags)
Use ISA 2.07 transactional memory (HTM) instructions.
mquad-memory
-Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
+Target Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
Generate the quad word memory instructions (lq/stq).
mquad-memory-atomic
-Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
+Target Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
Generate the quad word memory atomic instructions (lqarx/stqcx).
mcompat-align-parm
-Target Report Var(rs6000_compat_align_parm) Init(0) Save
+Target Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.
moptimize-swaps
; Use conservative small loop unrolling.
mpower9-misc
-Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
+Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags)
Use certain scalar instructions added in ISA 3.0.
mpower9-vector
-Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
+Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use vector instructions added in ISA 3.0.
mpower9-minmax
Fuse medium/large code model toc references with the memory instruction.
mmodulo
-Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
+Target Undocumented Mask(MODULO) Var(rs6000_isa_flags)
Generate the integer modulo instructions.
mfloat128
-Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
+Target Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
Enable IEEE 128-bit floating point via the __float128 keyword.
mfloat128-hardware
-Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
+Target Mask(FLOAT128_HW) Var(rs6000_isa_flags)
Enable using IEEE 128-bit floating point instructions.
mfloat128-convert
Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
mprefixed
-Target Report Mask(PREFIXED) Var(rs6000_isa_flags)
+Target Mask(PREFIXED) Var(rs6000_isa_flags)
Generate (do not generate) prefixed memory instructions.
mpcrel
-Target Report Mask(PCREL) Var(rs6000_isa_flags)
+Target Mask(PCREL) Var(rs6000_isa_flags)
Generate (do not generate) pc-relative memory addressing.
mmma
-Target Report Mask(MMA) Var(rs6000_isa_flags)
+Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
mrelative-jumptables
-msdata=[none,data,sysv,eabi] Select method for sdata handling.
mreadonly-in-sdata
-Target Report Var(rs6000_readonly_in_sdata) Init(1) Save
+Target Var(rs6000_readonly_in_sdata) Init(1) Save
Allow readonly data in sdata.
mtls-size=
Enum(rs6000_tls_size) String(64) Value(64)
mbit-align
-Target Report Var(TARGET_NO_BITFIELD_TYPE) Save
+Target Var(TARGET_NO_BITFIELD_TYPE) Save
Align to the base type of the bit-field.
mstrict-align
-Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags)
+Target Mask(STRICT_ALIGN) Var(rs6000_isa_flags)
Align to the base type of the bit-field.
Don't assume that unaligned accesses are handled by the system.
mrelocatable
-Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags)
+Target Mask(RELOCATABLE) Var(rs6000_isa_flags)
Produce code relocatable at runtime.
mrelocatable-lib
Produce code relocatable at runtime.
mlittle-endian
-Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
+Target RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce little endian code.
mlittle
-Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
+Target RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce little endian code.
mbig-endian
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
+Target RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce big endian code.
mbig
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
+Target RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce big endian code.
;; FIXME: This does nothing. What should be done?
No description yet.
meabi
-Target Report Mask(EABI) Var(rs6000_isa_flags)
+Target Mask(EABI) Var(rs6000_isa_flags)
Use EABI.
mbit-word
-Target Report Var(TARGET_NO_BITFIELD_WORD) Save
+Target Var(TARGET_NO_BITFIELD_WORD) Save
Allow bit-fields to cross word boundaries.
mregnames
No description yet.
m64
-Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
+Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
Generate 64-bit code.
m32
-Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
+Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
Generate 32-bit code.
mnewlib
No description yet.
msecure-plt
-Target Report RejectNegative Var(secure_plt, 1) Save
+Target RejectNegative Var(secure_plt, 1) Save
Generate code to use a non-exec PLT and GOT.
mbss-plt
-Target Report RejectNegative Var(secure_plt, 0) Save
+Target RejectNegative Var(secure_plt, 0) Save
Generate code for old exec BSS PLT.
mpltseq
-Target Report Var(rs6000_pltseq) Init(1) Save
+Target Var(rs6000_pltseq) Init(1) Save
Use inline plt sequences to implement long calls and -fno-plt.
mgnu-attribute
-Target Report Var(rs6000_gnu_attr) Init(1) Save
+Target Var(rs6000_gnu_attr) Init(1) Save
Emit .gnu_attribute tags.
;---------------------------------------------------
mas100-syntax
-Target Mask(AS100_SYNTAX) Report
+Target Mask(AS100_SYNTAX)
Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax.
;---------------------------------------------------
; The default is -fpu -m32bit-doubles.
m64bit-doubles
-Target RejectNegative Mask(64BIT_DOUBLES) Report
+Target RejectNegative Mask(64BIT_DOUBLES)
Store doubles in 64 bits.
m32bit-doubles
-Target RejectNegative InverseMask(64BIT_DOUBLES) Report
+Target RejectNegative InverseMask(64BIT_DOUBLES)
Stores doubles in 32 bits. This is the default.
nofpu
Disable the use of RX FPU instructions.
mnofpu
-Target RejectNegative Mask(NO_USE_FPU) Report Undocumented
+Target RejectNegative Mask(NO_USE_FPU) Undocumented
fpu
-Target RejectNegative InverseMask(NO_USE_FPU) Report
+Target RejectNegative InverseMask(NO_USE_FPU)
Enable the use of RX FPU instructions. This is the default.
;---------------------------------------------------
mcpu=
-Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600)
+Target RejectNegative Joined Var(rx_cpu_type) ToLower Enum(rx_cpu_types) Init(RX600)
Specify the target RX cpu type.
Enum
;---------------------------------------------------
mbig-endian-data
-Target RejectNegative Mask(BIG_ENDIAN_DATA) Report
+Target RejectNegative Mask(BIG_ENDIAN_DATA)
Data is stored in big-endian format.
mlittle-endian-data
-Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Report
+Target RejectNegative InverseMask(BIG_ENDIAN_DATA)
Data is stored in little-endian format. (Default).
;---------------------------------------------------
;---------------------------------------------------
mwarn-multiple-fast-interrupts
-Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
+Target Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
Warn when multiple, different, fast interrupt handlers are in the compilation unit.
;---------------------------------------------------
mgcc-abi
-Target RejectNegative Report Mask(GCC_ABI)
+Target RejectNegative Mask(GCC_ABI)
Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits.
mrx-abi
-Target RejectNegative Report InverseMask(GCC_ABI)
+Target RejectNegative InverseMask(GCC_ABI)
Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default.
;---------------------------------------------------
mlra
-Target Report Mask(ENABLE_LRA)
+Target Mask(ENABLE_LRA)
Enable the use of the LRA register allocator.
;---------------------------------------------------
mallow-string-insns
-Target Report Var(rx_allow_string_insns) Init(1)
+Target Var(rx_allow_string_insns) Init(1)
Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default.
;---------------------------------------------------
mjsr
-Target Report Mask(JSR)
+Target Mask(JSR)
Always use JSR, never BSR, for calls.
long s390_cost_pointer
m31
-Target Report RejectNegative Negative(m64) InverseMask(64BIT)
+Target RejectNegative Negative(m64) InverseMask(64BIT)
31 bit ABI.
m64
-Target Report RejectNegative Negative(m31) Mask(64BIT)
+Target RejectNegative Negative(m31) Mask(64BIT)
64 bit ABI.
march=
Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
mbackchain
-Target Report Mask(BACKCHAIN) Save
+Target Mask(BACKCHAIN) Save
Maintain backchain pointer.
mdebug
-Target Report Mask(DEBUG_ARG) Save
+Target Mask(DEBUG_ARG) Save
Additional debug prints.
mesa
-Target Report RejectNegative Negative(mzarch) InverseMask(ZARCH)
+Target RejectNegative Negative(mzarch) InverseMask(ZARCH)
ESA/390 architecture.
mhard-dfp
-Target Report Mask(HARD_DFP) Save
+Target Mask(HARD_DFP) Save
Enable decimal floating point hardware support.
mhard-float
-Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Save
+Target RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Save
Enable hardware floating point.
mhotpatch=
-Target RejectNegative Report Joined Var(s390_deferred_options) Defer
+Target RejectNegative Joined Var(s390_deferred_options) Defer
Takes two non-negative integer numbers separated by a comma.
Prepend the function label with the number of two-byte Nop
instructions indicated by the first. Append Nop instructions
size. Using 0 for both values disables hotpatching.
mlong-double-128
-Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128)
+Target RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128)
Use 128-bit long double.
mlong-double-64
-Target Report RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128)
+Target RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128)
Use 64-bit long double.
mhtm
-Target Report Mask(OPT_HTM) Save
+Target Mask(OPT_HTM) Save
Use hardware transactional execution instructions.
mvx
-Target Report Mask(OPT_VX) Save
+Target Mask(OPT_VX) Save
Use hardware vector facility instructions and enable the vector ABI.
mpacked-stack
-Target Report Mask(PACKED_STACK) Save
+Target Mask(PACKED_STACK) Save
Use packed stack layout.
msmall-exec
-Target Report Mask(SMALL_EXEC) Save
+Target Mask(SMALL_EXEC) Save
Use bras for executable < 64k.
msoft-float
-Target Report RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) Save
+Target RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) Save
Disable hardware floating point.
mstack-guard=
Schedule code for given CPU.
mmvcle
-Target Report Mask(MVCLE) Save
+Target Mask(MVCLE) Save
Use the mvcle instruction for block moves.
mzvector
-Target Report Mask(ZVECTOR) Save
+Target Mask(ZVECTOR) Save
Enable the z vector language extension providing the context-sensitive
vector macro and enable the Altivec-style builtins in vecintrin.h.
Warn if a single function's framesize exceeds the given framesize.
mzarch
-Target Report RejectNegative Negative(mesa) Mask(ZARCH)
+Target RejectNegative Negative(mesa) Mask(ZARCH)
z/Architecture.
mbranch-cost=
-Target Report Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) Save
+Target Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) Save
Set the branch costs for conditional branch instructions. Reasonable
values are small, non-negative integers. The default branch cost is
1.
mlra
-Target Report Var(s390_lra_flag) Init(1) Save
+Target Var(s390_lra_flag) Init(1) Save
Use LRA instead of reload.
mpic-data-is-text-relative
-Target Report Var(s390_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
+Target Var(s390_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
Assume data segments are relative to text segment.
mindirect-branch=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep)
Wrap all indirect branches into execute in order to disable branch
prediction.
mindirect-branch-jump=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep)
Wrap indirect table jumps and computed gotos into execute in order to
disable branch prediction. Using thunk or thunk-extern with this
option requires the thunks to be considered signal handlers to order to
exceptions) is required please use thunk-inline instead.
mindirect-branch-call=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep)
Wrap all indirect calls into execute in order to disable branch prediction.
mfunction-return=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep)
Wrap all indirect return branches into execute in order to disable branch
prediction.
mfunction-return-mem=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep)
Wrap indirect return branches into execute in order to disable branch
prediction. This affects only branches where the return address is
going to be restored from memory.
mfunction-return-reg=
-Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep)
+Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep)
Wrap indirect return branches into execute in order to disable branch
prediction. This affects only branches where the return address
doesn't need to be restored from memory.
Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
mindirect-branch-table
-Target Report Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE)
+Target Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE)
Generate sections .s390_indirect_jump, .s390_indirect_call,
.s390_return_reg, and .s390_return_mem to contain the indirect branch
locations which have been patched as part of using one of the
from the entry to the patched location.
mfentry
-Target Report Var(flag_fentry)
+Target Var(flag_fentry)
Emit profiling counter call at function entry before prologue. The compiled
code will require a 64-bit CPU and glibc 2.29 or newer to run.
mrecord-mcount
-Target Report Var(flag_record_mcount)
+Target Var(flag_record_mcount)
Generate __mcount_loc section with all _mcount and __fentry__ calls.
mnop-mcount
-Target Report Var(flag_nop_mcount)
+Target Var(flag_nop_mcount)
Generate mcount/__fentry__ calls as nops. To activate they need to be
patched in.
mvx-long-double-fma
-Target Report Undocumented Var(flag_vx_long_double_fma)
+Target Undocumented Var(flag_vx_long_double_fma)
Emit fused multiply-add instructions for long doubles in vector registers
(wfmaxb, wfmsxb, wfnmaxb, wfnmsxb). Reassociation pass does not handle
fused multiply-adds, therefore code generated by the middle-end is prone to
; <http://www.gnu.org/licenses/>.
mtpf-trace
-Target Report Mask(TPF_PROFILING)
+Target Mask(TPF_PROFILING)
Enable TPF-OS tracing code.
mtpf-trace-hook-prologue-check=
-Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_prologue_check) Init(TPF_TRACE_PROLOGUE_CHECK)
+Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_prologue_check) Init(TPF_TRACE_PROLOGUE_CHECK)
Set the trace check address for prologue tpf hook
mtpf-trace-hook-prologue-target=
-Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_prologue_target) Init(TPF_TRACE_PROLOGUE_TARGET)
+Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_prologue_target) Init(TPF_TRACE_PROLOGUE_TARGET)
Set the trace jump address for prologue tpf hook
mtpf-trace-hook-epilogue-check=
-Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_epilogue_check) Init(TPF_TRACE_EPILOGUE_CHECK)
+Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_epilogue_check) Init(TPF_TRACE_EPILOGUE_CHECK)
Set the trace check address for epilogue tpf hook
mtpf-trace-hook-epilogue-target=
-Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_epilogue_target) Init(TPF_TRACE_EPILOGUE_TARGET)
+Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_epilogue_target) Init(TPF_TRACE_EPILOGUE_TARGET)
Set the trace jump address for epilogue tpf hook
mtpf-trace-skip
-Target Report Var(s390_tpf_trace_skip) Init(0)
+Target Var(s390_tpf_trace_skip) Init(0)
Set the prologue and epilogue hook addresses to TPF_TRACE_PROLOGUE_SKIP_TARGET and TPF_TRACE_EPILOGUE_SKIP_TARGET. Equivalent to using -mtpf-trace-hook-prologue-target=TPF_TRACE_PROLOGUE_SKIP_TARGET and -mtpf-trace-hook-epilogue-target=TPF_TRACE_EPILOGUE_SKIP_TARGET
mmain
-Target Report
+Target
Specify main object for TPF-OS.
Generate SH4al-dsp code.
maccumulate-outgoing-args
-Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1)
+Target Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1)
Reserve space for outgoing arguments in the function prologue.
mb
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Target RejectNegative InverseMask(LITTLE_ENDIAN)
Generate code in big endian mode.
mbigtable
-Target Report RejectNegative Mask(BIGTABLE)
+Target RejectNegative Mask(BIGTABLE)
Generate 32-bit offsets in switch tables.
mbitops
-Target Report RejectNegative Mask(BITOPS)
+Target RejectNegative Mask(BITOPS)
Generate bit instructions.
mbranch-cost=
Cost to assume for a branch insn.
mzdcbranch
-Target Report Var(TARGET_ZDCBRANCH)
+Target Var(TARGET_ZDCBRANCH)
Assume that zero displacement conditional branches are fast.
mcbranch-force-delay-slot
-Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0)
+Target RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0)
Force the usage of delay slots for conditional branches.
mdalign
-Target Report RejectNegative Mask(ALIGN_DOUBLE)
+Target RejectNegative Mask(ALIGN_DOUBLE)
Align doubles at 64-bit boundaries.
mdiv=
Specify name for 32 bit signed division function.
mfdpic
-Target Report Var(TARGET_FDPIC) Init(0)
+Target Var(TARGET_FDPIC) Init(0)
Generate ELF FDPIC code.
mfmovd
Specify range of registers to make fixed.
mhitachi
-Target Report RejectNegative Mask(HITACHI)
+Target RejectNegative Mask(HITACHI)
Follow Renesas (formerly Hitachi) / SuperH calling conventions.
mieee
Increase the IEEE compliance for floating-point comparisons.
minline-ic_invalidate
-Target Report Var(TARGET_INLINE_IC_INVALIDATE)
+Target Var(TARGET_INLINE_IC_INVALIDATE)
Inline code to invalidate instruction cache entries after setting up nested function trampolines.
misize
-Target Report RejectNegative Mask(DUMPISIZE)
+Target RejectNegative Mask(DUMPISIZE)
Annotate assembler instructions with estimated addresses.
ml
-Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Target RejectNegative Mask(LITTLE_ENDIAN)
Generate code in little endian mode.
mnomacsave
-Target Report RejectNegative Mask(NOMACSAVE)
+Target RejectNegative Mask(NOMACSAVE)
Mark MAC register as call-clobbered.
;; ??? This option is not useful, but is retained in case there are people
;; who are still relying on it. It may be deleted in the future.
mpadstruct
-Target Report RejectNegative Mask(PADSTRUCT)
+Target RejectNegative Mask(PADSTRUCT)
Make structs a multiple of 4 bytes (warning: ABI altered).
mprefergot
-Target Report RejectNegative Mask(PREFERGOT)
+Target RejectNegative Mask(PREFERGOT)
Emit function-calls using global offset table when generating PIC.
mrelax
-Target Report RejectNegative Mask(RELAX)
+Target RejectNegative Mask(RELAX)
Shorten address references during linking.
mrenesas
Follow Renesas (formerly Hitachi) / SuperH calling conventions.
matomic-model=
-Target Report RejectNegative Joined Var(sh_atomic_model_str)
+Target RejectNegative Joined Var(sh_atomic_model_str)
Specify the model for atomic operations.
mtas
-Target Report RejectNegative Var(TARGET_ENABLE_TAS)
+Target RejectNegative Var(TARGET_ENABLE_TAS)
Use tas.b instruction for __atomic_test_and_set.
multcost=
Enable the use of the fsrra instruction.
mlra
-Target Report Var(sh_lra_flag) Init(0) Save
+Target Var(sh_lra_flag) Init(0) Save
Use LRA instead of reload (transitional).
Driver Joined
mclear-hwcap
-Target Report
+Target
Clear hardware capabilities when linking.
mimpure-text
-Target Report
+Target
Pass -z text to linker.
pthread
; <http://www.gnu.org/licenses/>.
mlong-double-128
-Target Report RejectNegative Mask(LONG_DOUBLE_128)
+Target RejectNegative Mask(LONG_DOUBLE_128)
Use 128-bit long double.
mlong-double-64
-Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
+Target RejectNegative InverseMask(LONG_DOUBLE_128)
Use 64-bit long double.
unsigned int sparc_debug
mfpu
-Target Report Mask(FPU)
+Target Mask(FPU)
Use hardware FP.
mhard-float
Do not use hardware FP.
mflat
-Target Report Mask(FLAT)
+Target Mask(FLAT)
Use flat register window model.
munaligned-doubles
-Target Report Mask(UNALIGNED_DOUBLES)
+Target Mask(UNALIGNED_DOUBLES)
Assume possible double misalignment.
mapp-regs
-Target Report Mask(APP_REGS)
+Target Mask(APP_REGS)
Use ABI reserved registers.
mhard-quad-float
-Target Report RejectNegative Mask(HARD_QUAD)
+Target RejectNegative Mask(HARD_QUAD)
Use hardware quad FP instructions.
msoft-quad-float
-Target Report RejectNegative InverseMask(HARD_QUAD)
+Target RejectNegative InverseMask(HARD_QUAD)
Do not use hardware quad fp instructions.
mlra
-Target Report Mask(LRA)
+Target Mask(LRA)
Enable Local Register Allocation.
mv8plus
-Target Report Mask(V8PLUS)
+Target Mask(V8PLUS)
Compile for V8+ ABI.
mvis
-Target Report Mask(VIS)
+Target Mask(VIS)
Use UltraSPARC Visual Instruction Set version 1.0 extensions.
mvis2
-Target Report Mask(VIS2)
+Target Mask(VIS2)
Use UltraSPARC Visual Instruction Set version 2.0 extensions.
mvis3
-Target Report Mask(VIS3)
+Target Mask(VIS3)
Use UltraSPARC Visual Instruction Set version 3.0 extensions.
mvis4
-Target Report Mask(VIS4)
+Target Mask(VIS4)
Use UltraSPARC Visual Instruction Set version 4.0 extensions.
mvis4b
-Target Report Mask(VIS4B)
+Target Mask(VIS4B)
Use additional VIS instructions introduced in OSA2017.
mcbcond
-Target Report Mask(CBCOND)
+Target Mask(CBCOND)
Use UltraSPARC Compare-and-Branch extensions.
mfmaf
-Target Report Mask(FMAF)
+Target Mask(FMAF)
Use UltraSPARC Fused Multiply-Add extensions.
mfsmuld
-Target Report Mask(FSMULD)
+Target Mask(FSMULD)
Use Floating-point Multiply Single to Double (FsMULd) instruction.
mpopc
-Target Report Mask(POPC)
+Target Mask(POPC)
Use UltraSPARC Population-Count instruction.
msubxc
-Target Report Mask(SUBXC)
+Target Mask(SUBXC)
Use UltraSPARC Subtract-Extended-with-Carry instruction.
mptr64
-Target Report RejectNegative Mask(PTR64)
+Target RejectNegative Mask(PTR64)
Pointers are 64-bit.
mptr32
-Target Report RejectNegative InverseMask(PTR64)
+Target RejectNegative InverseMask(PTR64)
Pointers are 32-bit.
m64
-Target Report RejectNegative Mask(64BIT)
+Target RejectNegative Mask(64BIT)
Use 64-bit ABI.
m32
-Target Report RejectNegative InverseMask(64BIT)
+Target RejectNegative InverseMask(64BIT)
Use 32-bit ABI.
mstack-bias
-Target Report Mask(STACK_BIAS)
+Target Mask(STACK_BIAS)
Use stack bias.
mfaster-structs
-Target Report Mask(FASTER_STRUCTS)
+Target Mask(FASTER_STRUCTS)
Use structs on stronger alignment for double-word copies.
mrelax
Optimize tail call instructions in assembler and linker.
muser-mode
-Target Report InverseMask(SV_MODE)
+Target InverseMask(SV_MODE)
Do not generate code that can only run in supervisor mode (default).
mcpu=
Enable debug output.
mstd-struct-return
-Target Report Var(sparc_std_struct_return)
+Target Var(sparc_std_struct_return)
Enable strict 32-bit psABI struct return checking.
mfix-at697f
-Target Report RejectNegative Var(sparc_fix_at697f)
+Target RejectNegative Var(sparc_fix_at697f)
Enable workaround for single erratum of AT697F processor
(corresponding to erratum #13 of AT697E processor).
mfix-ut699
-Target Report RejectNegative Var(sparc_fix_ut699)
+Target RejectNegative Var(sparc_fix_ut699)
Enable workarounds for the errata of the UT699 processor.
mfix-ut700
-Target Report RejectNegative Var(sparc_fix_ut700)
+Target RejectNegative Var(sparc_fix_ut700)
Enable workarounds for the errata of the UT699E/UT700 processor.
mfix-gr712rc
-Target Report RejectNegative Var(sparc_fix_gr712rc)
+Target RejectNegative Var(sparc_fix_gr712rc)
Enable workarounds for the errata of the GR712RC processor.
;; Enable workaround for back-to-back store errata
Enum(tilegx_cpu) String(tilegx) Value(0)
m32
-Target Report RejectNegative Negative(m64) Mask(32BIT)
+Target RejectNegative Negative(m64) Mask(32BIT)
Compile with 32 bit longs and pointers.
m64
-Target Report RejectNegative Negative(m32) InverseMask(32BIT, 64BIT)
+Target RejectNegative Negative(m32) InverseMask(32BIT, 64BIT)
Compile with 64 bit longs and pointers.
mbig-endian
-Target Report RejectNegative Mask(BIG_ENDIAN)
+Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order.
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_ENDIAN)
+Target RejectNegative InverseMask(BIG_ENDIAN)
Use little-endian byte order.
mcmodel=
; <http://www.gnu.org/licenses/>.
m32
-Target Report RejectNegative
+Target RejectNegative
Compile with 32 bit longs and pointers, which is the only supported
behavior and thus the flag is ignored.
int small_memory_max[(int)SMALL_MEMORY_max] = { 0, 0, 0 }
mapp-regs
-Target Report Mask(APP_REGS)
+Target Mask(APP_REGS)
Use registers r2 and r5.
mbig-switch
-Target Report Mask(BIG_SWITCH)
+Target Mask(BIG_SWITCH)
Use 4 byte entries in switch tables.
mdebug
-Target Report Mask(DEBUG)
+Target Mask(DEBUG)
Enable backend debugging.
mdisable-callt
-Target Report Mask(DISABLE_CALLT)
+Target Mask(DISABLE_CALLT)
Do not use the callt instruction (default).
mep
-Target Report Mask(EP)
+Target Mask(EP)
Reuse r30 on a per function basis.
mghs
Target RejectNegative InverseMask(GCC_ABI) MaskExists
mlong-calls
-Target Report Mask(LONG_CALLS)
+Target Mask(LONG_CALLS)
Prohibit PC relative function calls.
mprolog-function
-Target Report Mask(PROLOG_FUNCTION)
+Target Mask(PROLOG_FUNCTION)
Use stubs for function prologues.
msda=
Target RejectNegative Joined Undocumented Alias(msda=)
msmall-sld
-Target Report Mask(SMALL_SLD)
+Target Mask(SMALL_SLD)
Enable the use of the short load instructions.
mspace
Target RejectNegative Joined Undocumented Alias(mtda=)
mno-strict-align
-Target Report Mask(NO_STRICT_ALIGN)
+Target Mask(NO_STRICT_ALIGN)
Do not enforce strict alignment.
mjump-tables-in-data-section
-Target Report Mask(JUMP_TABLES_IN_DATA_SECTION)
+Target Mask(JUMP_TABLES_IN_DATA_SECTION)
Put jump tables for switch statements into the .data section rather than the .code section.
mUS-bit-set
-Target Report Mask(US_BIT_SET)
+Target Mask(US_BIT_SET)
mv850
-Target Report RejectNegative Mask(V850)
+Target RejectNegative Mask(V850)
Compile for the v850 processor.
mv850e
-Target Report RejectNegative Mask(V850E)
+Target RejectNegative Mask(V850E)
Compile for the v850e processor.
mv850e1
Compile for the v850es variant of the v850e1.
mv850e2
-Target Report RejectNegative Mask(V850E2)
+Target RejectNegative Mask(V850E2)
Compile for the v850e2 processor.
mv850e2v3
-Target Report RejectNegative Mask(V850E2V3)
+Target RejectNegative Mask(V850E2V3)
Compile for the v850e2v3 processor.
mv850e3v5
-Target Report RejectNegative Mask(V850E3V5)
+Target RejectNegative Mask(V850E3V5)
Compile for the v850e3v5 processor.
mv850e2v4
Target RejectNegative Mask(V850E3V5) MaskExists
mloop
-Target Report Mask(LOOP)
+Target Mask(LOOP)
Enable v850e3v5 loop instructions.
mzda=
Target RejectNegative Joined Undocumented Alias(mzda=)
mrelax
-Target Report Mask(RELAX)
+Target Mask(RELAX)
Enable relaxing in the assembler.
mlong-jumps
-Target Report Mask(BIG_SWITCH) MaskExists
+Target Mask(BIG_SWITCH) MaskExists
Prohibit PC relative jumps.
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT)
+Target RejectNegative Mask(SOFT_FLOAT)
Inhibit the use of hardware floating point instructions.
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT) MaskExists
+Target RejectNegative InverseMask(SOFT_FLOAT) MaskExists
Allow the use of hardware floating point instructions for V850E2V3 and up.
mrh850-abi
-Target RejectNegative Report InverseMask(GCC_ABI) MaskExists
+Target RejectNegative InverseMask(GCC_ABI) MaskExists
Enable support for the RH850 ABI. This is the default.
mgcc-abi
-Target RejectNegative Report Mask(GCC_ABI)
+Target RejectNegative Mask(GCC_ABI)
Enable support for the old GCC ABI.
m8byte-align
-Target Report Mask(8BYTE_ALIGN)
+Target Mask(8BYTE_ALIGN)
Support alignments of up to 64-bits.
Link with libc.a and libsim.a.
mfpu
-Target Report Mask(FPU)
+Target Mask(FPU)
Use hardware FP (default).
mhard-float
Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6)
msv-mode
-Target RejectNegative Report Mask(SV_MODE)
+Target RejectNegative Mask(SV_MODE)
Generate code for the supervisor mode (default).
muser-mode
-Target RejectNegative Report InverseMask(SV_MODE)
+Target RejectNegative InverseMask(SV_MODE)
Generate code for the user mode.
menable-trampolines
Target RejectNegative
mmalloc64
-Target Report Var(flag_vms_malloc64) Init(1)
+Target Var(flag_vms_malloc64) Init(1)
Malloc data into P2 space.
mdebug-main=
Set name of main routine for the debugger.
mvms-return-codes
-Target Report Var(flag_vms_return_codes)
+Target Var(flag_vms_return_codes)
Use VMS exit codes instead of posix ones.
mpointer-size=
-Target Joined Report RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE)
+Target Joined RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE)
-mpointer-size=[no,32,short,64,long] Set the default pointer size.
Enum
Driver Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL)
mrtp
-Target Report RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL)
+Target RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL)
Assume the VxWorks RTP environment.
; VxWorks AE has two modes: kernel mode and vThreads mode. In
; <http://www.gnu.org/licenses/>.
mconst16
-Target Report Mask(CONST16)
+Target Mask(CONST16)
Use CONST16 instruction to load constants.
mforce-no-pic
-Target Report Mask(FORCE_NO_PIC)
+Target Mask(FORCE_NO_PIC)
Disable position-independent code (PIC) for use in OS kernel code.
mlongcalls
Intersperse literal pools with code in the text section.
mauto-litpools
-Target Report Mask(AUTO_LITPOOLS)
+Target Mask(AUTO_LITPOOLS)
Relax literals in assembler and place them automatically in the text section.
mserialize-volatile
-Target Report Mask(SERIALIZE_VOLATILE)
+Target Mask(SERIALIZE_VOLATILE)
-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions.
TargetVariable
int xtensa_windowed_abi = -1
mabi=call0
-Target Report RejectNegative Var(xtensa_windowed_abi, 0)
+Target RejectNegative Var(xtensa_windowed_abi, 0)
Use call0 ABI.
mabi=windowed
-Target Report RejectNegative Var(xtensa_windowed_abi, 1)
+Target RejectNegative Var(xtensa_windowed_abi, 1)
Use windowed registers ABI.
Enum(lto_linker_output) String(exec) Value(LTO_LINKER_OUTPUT_EXEC)
flinker-output=
-LTO Report Driver Joined RejectNegative Enum(lto_linker_output) Var(flag_lto_linker_output) Init(LTO_LINKER_OUTPUT_UNKNOWN)
+LTO Driver Joined RejectNegative Enum(lto_linker_output) Var(flag_lto_linker_output) Init(LTO_LINKER_OUTPUT_UNKNOWN)
Set linker output type (used internally during LTO optimization).
fltrans
-LTO Report Var(flag_ltrans)
+LTO Var(flag_ltrans)
Run the link-time optimizer in local transformation (LTRANS) mode.
fltrans-output-list=
Specify a file to which a list of files output by LTRANS is written.
fwpa
-LTO Driver Report
+LTO Driver
Run the link-time optimizer in whole program analysis (WPA) mode.
fwpa=
projects / gcc.git / commitdiff