Now we can actually test our changes.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
-I$(top_srcdir)/src/intel \
$(DEFINES) \
$(VISIBILITY_CFLAGS) \
- $(INTEL_CFLAGS)
+ $(LIBDRM_CFLAGS) \
+ $(VALGRIND_CFLAGS)
AM_CXXFLAGS = $(AM_CFLAGS)
$(top_builddir)/src/intel/compiler/libintel_compiler.la \
$(top_builddir)/src/intel/blorp/libblorp.la \
$(I965_PERGEN_LIBS) \
- $(INTEL_LIBS)
+ $(LIBDRM_LIBS)
BUILT_SOURCES = $(i965_oa_GENERATED_FILES)
CLEANFILES = $(BUILT_SOURCES)
brw_binding_tables.c \
brw_blorp.c \
brw_blorp.h \
+ brw_bufmgr.h \
brw_cc.c \
brw_clear.c \
brw_clip.c \
intel_buffer_objects.h \
intel_buffers.c \
intel_buffers.h \
+ intel_bufmgr.c \
+ intel_bufmgr_gem.c \
+ intel_bufmgr_priv.h \
+ intel_chipset.h \
intel_copy_image.c \
intel_extensions.c \
intel_fbo.c \
intel_tex_validate.c \
intel_tiled_memcpy.c \
intel_tiled_memcpy.h \
- intel_upload.c
+ intel_upload.c \
+ libdrm_lists.h \
+ libdrm_macros.h \
+ uthash.h \
+ xf86atomic.h
i965_gen6_FILES = \
genX_blorp_exec.c
*/
/**
- * @file intel_bufmgr.h
+ * @file brw_bufmgr.h
*
* Public definitions of Intel-specific bufmgr functions.
*/
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
/* Emit CC viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
(brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4)),
brw->batch.bo, brw->cc.vp_offset,
(brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
/* emit clip viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
(brw->clip.state_offset +
offsetof(struct brw_clip_unit_state, clip6)),
brw->batch.bo, brw->clip.vp_offset,
prepare_indirect_gpgpu_walker(struct brw_context *brw)
{
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
- drm_intel_bo *bo = brw->compute.num_work_groups_bo;
+ drm_bacon_bo *bo = brw->compute.num_work_groups_bo;
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
I915_GEM_DOMAIN_VERTEX, 0,
brw->no_batch_wrap = false;
- if (drm_intel_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
+ if (drm_bacon_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
if (!fail_next) {
intel_batchbuffer_reset_to_saved(brw);
intel_batchbuffer_flush(brw);
struct brw_context *brw = brw_context(ctx);
static const GLuint indirect_group_counts[3] = { 0, 0, 0 };
struct gl_buffer_object *indirect_buffer = ctx->DispatchIndirectBuffer;
- drm_intel_bo *bo =
+ drm_bacon_bo *bo =
intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
indirect, 3 * sizeof(GLuint));
}
static bool
-intel_disable_rb_aux_buffer(struct brw_context *brw, const drm_intel_bo *bo)
+intel_disable_rb_aux_buffer(struct brw_context *brw, const drm_bacon_bo *bo)
{
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
bool found = false;
intel_glFlush(ctx);
if (brw->batch.last_bo)
- drm_intel_bo_wait_rendering(brw->batch.last_bo);
+ drm_bacon_bo_wait_rendering(brw->batch.last_bo);
}
static void
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
- drm_intel_bufmgr_gem_enable_reuse(brw->bufmgr);
+ drm_bacon_bufmgr_gem_enable_reuse(brw->bufmgr);
break;
}
* This is required for transform feedback buffer offsets, query objects,
* and also allows us to reduce how much state we have to emit.
*/
- brw->hw_ctx = drm_intel_gem_context_create(brw->bufmgr);
+ brw->hw_ctx = drm_bacon_gem_context_create(brw->bufmgr);
if (!brw->hw_ctx) {
fprintf(stderr, "Failed to create hardware context.\n");
brw_destroy_state(brw);
brw_draw_destroy(brw);
- drm_intel_bo_unreference(brw->curbe.curbe_bo);
+ drm_bacon_bo_unreference(brw->curbe.curbe_bo);
if (brw->vs.base.scratch_bo)
- drm_intel_bo_unreference(brw->vs.base.scratch_bo);
+ drm_bacon_bo_unreference(brw->vs.base.scratch_bo);
if (brw->tcs.base.scratch_bo)
- drm_intel_bo_unreference(brw->tcs.base.scratch_bo);
+ drm_bacon_bo_unreference(brw->tcs.base.scratch_bo);
if (brw->tes.base.scratch_bo)
- drm_intel_bo_unreference(brw->tes.base.scratch_bo);
+ drm_bacon_bo_unreference(brw->tes.base.scratch_bo);
if (brw->gs.base.scratch_bo)
- drm_intel_bo_unreference(brw->gs.base.scratch_bo);
+ drm_bacon_bo_unreference(brw->gs.base.scratch_bo);
if (brw->wm.base.scratch_bo)
- drm_intel_bo_unreference(brw->wm.base.scratch_bo);
+ drm_bacon_bo_unreference(brw->wm.base.scratch_bo);
- drm_intel_gem_context_destroy(brw->hw_ctx);
+ drm_bacon_gem_context_destroy(brw->hw_ctx);
if (ctx->swrast_context) {
_swsetup_DestroyContext(&brw->ctx);
brw_fini_pipe_control(brw);
intel_batchbuffer_free(&brw->batch);
- drm_intel_bo_unreference(brw->throttle_batch[1]);
- drm_intel_bo_unreference(brw->throttle_batch[0]);
+ drm_bacon_bo_unreference(brw->throttle_batch[1]);
+ drm_bacon_bo_unreference(brw->throttle_batch[0]);
brw->throttle_batch[1] = NULL;
brw->throttle_batch[0] = NULL;
* DRI2BufferDepthStencil are handled as special cases.
*
* \param buffer_name is a human readable name, such as "dri2 front buffer",
- * that is passed to drm_intel_bo_gem_create_from_name().
+ * that is passed to drm_bacon_bo_gem_create_from_name().
*
* \see intel_update_renderbuffers()
*/
const char *buffer_name)
{
struct gl_framebuffer *fb = drawable->driverPrivate;
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
if (!rb)
return;
if (last_mt) {
/* The bo already has a name because the miptree was created by a
* previous call to intel_process_dri2_buffer(). If a bo already has a
- * name, then drm_intel_bo_flink() is a low-cost getter. It does not
+ * name, then drm_bacon_bo_flink() is a low-cost getter. It does not
* create a new name.
*/
- drm_intel_bo_flink(last_mt->bo, &old_name);
+ drm_bacon_bo_flink(last_mt->bo, &old_name);
}
if (old_name == buffer->name)
buffer->cpp, buffer->pitch);
}
- bo = drm_intel_bo_gem_create_from_name(brw->bufmgr, buffer_name,
+ bo = drm_bacon_bo_gem_create_from_name(brw->bufmgr, buffer_name,
buffer->name);
if (!bo) {
fprintf(stderr,
assert(rb->mt);
- drm_intel_bo_unreference(bo);
+ drm_bacon_bo_unreference(bo);
}
/**
#include "isl/isl.h"
#include "blorp/blorp.h"
-#include <intel_bufmgr.h>
+#include <brw_bufmgr.h>
#include "common/gen_debug.h"
#include "intel_screen.h"
struct brw_context *brw;
struct brw_cache_item **items;
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
GLuint size, n_items;
uint32_t next_offset;
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
uint32_t offset;
uint32_t size;
/** Byte stride between elements in the uploaded array */
struct gl_query_object Base;
/** Last query BO associated with this query. */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
/** Last index in bo with query data for this object. */
int last_index;
struct intel_batchbuffer {
/** Current batchbuffer being queued up. */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
/** Last BO submitted to the hardware. Used for glFinish(). */
- drm_intel_bo *last_bo;
+ drm_bacon_bo *last_bo;
#ifdef DEBUG
uint16_t emit, total;
struct gl_transform_feedback_object base;
/** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
- drm_intel_bo *offset_bo;
+ drm_bacon_bo *offset_bo;
/** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
bool zero_offsets;
* @{
*/
uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
- drm_intel_bo *prim_count_bo;
+ drm_bacon_bo *prim_count_bo;
unsigned prim_count_buffer_index; /**< in number of uint64_t units */
/** @} */
* unless you're taking additional measures to synchronize thread execution
* across slot size changes.
*/
- drm_intel_bo *scratch_bo;
+ drm_bacon_bo *scratch_bo;
/**
* Scratch slot size allocated for each thread in the buffer object given
} vtbl;
- drm_intel_bufmgr *bufmgr;
+ drm_bacon_bufmgr *bufmgr;
- drm_intel_context *hw_ctx;
+ drm_bacon_context *hw_ctx;
/** BO for post-sync nonzero writes for gen6 workaround. */
- drm_intel_bo *workaround_bo;
+ drm_bacon_bo *workaround_bo;
uint8_t pipe_controls_since_last_cs_stall;
/**
- * Set of drm_intel_bo * that have been rendered to within this batchbuffer
+ * Set of drm_bacon_bo * that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
* isn't coherent with it (i.e. the sampler).
*/
bool no_batch_wrap;
struct {
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
uint32_t next_offset;
} upload;
bool front_buffer_dirty;
/** Framerate throttling: @{ */
- drm_intel_bo *throttle_batch[2];
+ drm_bacon_bo *throttle_batch[2];
/* Limit the number of outstanding SwapBuffers by waiting for an earlier
* frame of rendering to complete. This gives a very precise cap to the
* Buffer and offset used for GL_ARB_shader_draw_parameters
* (for now, only gl_BaseVertex).
*/
- drm_intel_bo *draw_params_bo;
+ drm_bacon_bo *draw_params_bo;
uint32_t draw_params_offset;
/**
* draw parameters.
*/
int gl_drawid;
- drm_intel_bo *draw_id_bo;
+ drm_bacon_bo *draw_id_bo;
uint32_t draw_id_offset;
} draw;
* an indirect call, and num_work_groups_offset is valid. Otherwise,
* num_work_groups is set based on glDispatchCompute.
*/
- drm_intel_bo *num_work_groups_bo;
+ drm_bacon_bo *num_work_groups_bo;
GLintptr num_work_groups_offset;
const GLuint *num_work_groups;
} compute;
const struct _mesa_index_buffer *ib;
/* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
uint32_t size;
GLuint type;
* Pointer to the (intel_upload.c-generated) BO containing the uniforms
* for upload to the CURBE.
*/
- drm_intel_bo *curbe_bo;
+ drm_bacon_bo *curbe_bo;
/** Offset within curbe_bo of space for current curbe entry */
GLuint curbe_offset;
} curbe;
* Buffer object used in place of multisampled null render targets on
* Gen6. See brw_emit_null_surface_state().
*/
- drm_intel_bo *multisampled_null_render_target_bo;
+ drm_bacon_bo *multisampled_null_render_target_bo;
uint32_t fast_clear_op;
float offset_clamp;
} l3;
struct {
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
const char **names;
int *ids;
enum shader_time_shader_type *types;
/** gen6_queryobj.c */
void gen6_init_queryobj_functions(struct dd_function_table *functions);
-void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
-void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
+void brw_write_timestamp(struct brw_context *brw, drm_bacon_bo *bo, int idx);
+void brw_write_depth_count(struct brw_context *brw, drm_bacon_bo *bo, int idx);
/** hsw_queryobj.c */
void hsw_overflow_result_to_gpr0(struct brw_context *brw,
/** intel_batchbuffer.c */
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_store_register_mem32(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
+ drm_bacon_bo *bo, uint32_t reg, uint32_t offset);
void brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
+ drm_bacon_bo *bo, uint32_t reg, uint32_t offset);
void brw_load_register_imm32(struct brw_context *brw,
uint32_t reg, uint32_t imm);
void brw_load_register_imm64(struct brw_context *brw,
uint32_t dest);
void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
uint32_t dest);
-void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+void brw_store_data_imm32(struct brw_context *brw, drm_bacon_bo *bo,
uint32_t offset, uint32_t imm);
-void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+void brw_store_data_imm64(struct brw_context *brw, drm_bacon_bo *bo,
uint32_t offset, uint64_t imm);
/*======================================================================
void brwInitFragProgFuncs( struct dd_function_table *functions );
void brw_get_scratch_bo(struct brw_context *brw,
- drm_intel_bo **scratch_bo, int size);
+ drm_bacon_bo **scratch_bo, int size);
void brw_alloc_stage_scratch(struct brw_context *brw,
struct brw_stage_state *stage_state,
unsigned per_thread_size,
/* brw_wm_surface_state.c */
void brw_init_surface_formats(struct brw_context *brw);
void brw_create_constant_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset);
void brw_create_buffer_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset);
void brw_init_performance_queries(struct brw_context *brw);
/* intel_buffer_objects.c */
-int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
+int brw_bo_map(struct brw_context *brw, drm_bacon_bo *bo, int write_enable,
const char *bo_name);
-int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
+int brw_bo_map_gtt(struct brw_context *brw, drm_bacon_bo *bo,
const char *bo_name);
/* intel_extensions.c */
return prog_offset;
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
state_offset,
brw->cache.bo,
prog_offset,
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- drm_intel_bo *bo, uint32_t offset,
+ drm_bacon_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
if (unlikely(brw->perf_debug)) {
start_busy = (brw->batch.last_bo &&
- drm_intel_bo_busy(brw->batch.last_bo));
+ drm_bacon_bo_busy(brw->batch.last_bo));
start_time = get_time();
}
}
cp->compiled_once = true;
- if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
+ if (start_busy && !drm_bacon_bo_busy(brw->batch.last_bo)) {
perf_debug("CS compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
ADVANCE_BATCH();
} else if (prim->is_indirect) {
struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer;
- drm_intel_bo *bo = intel_bufferobj_buffer(brw,
+ drm_bacon_bo *bo = intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
prim->indirect_offset, 5 * sizeof(GLuint));
GLuint i;
for (i = 0; i < brw->vb.nr_buffers; i++) {
- drm_intel_bo_unreference(brw->vb.buffers[i].bo);
+ drm_bacon_bo_unreference(brw->vb.buffers[i].bo);
brw->vb.buffers[i].bo = NULL;
}
brw->vb.nr_buffers = 0;
brw->draw.params.gl_basevertex = new_basevertex;
brw->draw.params.gl_baseinstance = new_baseinstance;
- drm_intel_bo_unreference(brw->draw.draw_params_bo);
+ drm_bacon_bo_unreference(brw->draw.draw_params_bo);
if (prims[i].is_indirect) {
/* Point draw_params_bo at the indirect buffer. */
brw->draw.draw_params_bo =
intel_buffer_object(ctx->DrawIndirectBuffer)->buffer;
- drm_intel_bo_reference(brw->draw.draw_params_bo);
+ drm_bacon_bo_reference(brw->draw.draw_params_bo);
brw->draw.draw_params_offset =
prims[i].indirect_offset + (prims[i].indexed ? 12 : 8);
} else {
* the loop.
*/
brw->draw.gl_drawid = prims[i].draw_id;
- drm_intel_bo_unreference(brw->draw.draw_id_bo);
+ drm_bacon_bo_unreference(brw->draw.draw_id_bo);
brw->draw.draw_id_bo = NULL;
if (i > 0 && vs_prog_data->uses_drawid)
brw->ctx.NewDriverState |= BRW_NEW_VERTICES;
brw->no_batch_wrap = false;
- if (drm_intel_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
+ if (drm_bacon_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
if (!fail_next) {
intel_batchbuffer_reset_to_saved(brw);
intel_batchbuffer_flush(brw);
unsigned i;
for (i = 0; i < brw->vb.nr_buffers; i++) {
- drm_intel_bo_unreference(brw->vb.buffers[i].bo);
+ drm_bacon_bo_unreference(brw->vb.buffers[i].bo);
brw->vb.buffers[i].bo = NULL;
}
brw->vb.nr_buffers = 0;
}
brw->vb.nr_enabled = 0;
- drm_intel_bo_unreference(brw->ib.bo);
+ drm_bacon_bo_unreference(brw->ib.bo);
brw->ib.bo = NULL;
}
#define BRW_DRAW_H
#include "main/mtypes.h" /* for struct gl_context... */
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
struct brw_context;
uint32_t *
brw_emit_vertex_buffer_state(struct brw_context *brw,
unsigned buffer_nr,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
unsigned start_offset,
unsigned end_offset,
unsigned stride,
const uint32_t range = buffer_range_end[i] - buffer_range_start[i];
buffer->bo = intel_bufferobj_buffer(brw, enabled_buffer[i], start, range);
- drm_intel_bo_reference(buffer->bo);
+ drm_bacon_bo_reference(buffer->bo);
}
/* If we need to upload all the arrays, then we can trim those arrays to
uint32_t *
brw_emit_vertex_buffer_state(struct brw_context *brw,
unsigned buffer_nr,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
unsigned start_offset,
unsigned end_offset,
unsigned stride,
struct gl_context *ctx = &brw->ctx;
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
GLuint ib_size;
- drm_intel_bo *old_bo = brw->ib.bo;
+ drm_bacon_bo *old_bo = brw->ib.bo;
struct gl_buffer_object *bufferobj;
GLuint offset;
GLuint ib_type_size;
ctx->Driver.UnmapBuffer(ctx, bufferobj, MAP_INTERNAL);
} else {
- drm_intel_bo *bo =
+ drm_bacon_bo *bo =
intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
offset, ib_size);
if (bo != brw->ib.bo) {
- drm_intel_bo_unreference(brw->ib.bo);
+ drm_bacon_bo_unreference(brw->ib.bo);
brw->ib.bo = bo;
brw->ib.size = bufferobj->Size;
- drm_intel_bo_reference(bo);
+ drm_bacon_bo_reference(bo);
}
}
}
st_index = brw_get_shader_time_index(brw, &gp->program, ST_GS, true);
if (unlikely(brw->perf_debug)) {
- start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo);
+ start_busy = brw->batch.last_bo && drm_bacon_bo_busy(brw->batch.last_bo);
start_time = get_time();
}
if (gp->compiled_once) {
brw_gs_debug_recompile(brw, &gp->program, key);
}
- if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
+ if (start_busy && !drm_bacon_bo_busy(brw->batch.last_bo)) {
perf_debug("GS compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
#include "intel_mipmap_tree.h"
static GLenum
-intel_buffer_purgeable(drm_intel_bo *buffer)
+intel_buffer_purgeable(drm_bacon_bo *buffer)
{
int retained = 0;
if (buffer != NULL)
- retained = drm_intel_bo_madvise(buffer, I915_MADV_DONTNEED);
+ retained = drm_bacon_bo_madvise(buffer, I915_MADV_DONTNEED);
return retained ? GL_VOLATILE_APPLE : GL_RELEASED_APPLE;
}
}
static int
-intel_bo_unpurgeable(drm_intel_bo *buffer)
+intel_bo_unpurgeable(drm_bacon_bo *buffer)
{
int retained;
retained = 0;
if (buffer != NULL)
- retained = drm_intel_bo_madvise(buffer, I915_MADV_WILLNEED);
+ retained = drm_bacon_bo_madvise(buffer, I915_MADV_WILLNEED);
return retained;
}
return GL_UNDEFINED_APPLE;
if (option == GL_UNDEFINED_APPLE || !intel_bo_unpurgeable(intel->buffer)) {
- drm_intel_bo_unreference(intel->buffer);
+ drm_bacon_bo_unreference(intel->buffer);
intel->buffer = NULL;
return GL_UNDEFINED_APPLE;
}
/**
* BO containing OA counter snapshots at query Begin/End time.
*/
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
/**
* The MI_REPORT_PERF_COUNT command lets us specify a unique
* BO containing starting and ending snapshots for the
* statistics counters.
*/
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
} pipeline_stats;
};
};
*/
static void
emit_mi_report_perf_count(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t offset_in_bytes,
uint32_t report_id)
{
if (!read_oa_samples(brw))
goto error;
- drm_intel_bo_map(obj->oa.bo, false);
+ drm_bacon_bo_map(obj->oa.bo, false);
query_buffer = obj->oa.bo->virtual;
start = last = query_buffer;
DBG("Marking %d accumulated - results gathered\n", o->Id);
- drm_intel_bo_unmap(obj->oa.bo);
+ drm_bacon_bo_unmap(obj->oa.bo);
obj->oa.results_accumulated = true;
drop_from_unaccumulated_query_list(brw, obj);
dec_n_oa_users(brw);
error:
- drm_intel_bo_unmap(obj->oa.bo);
+ drm_bacon_bo_unmap(obj->oa.bo);
discard_all_queries(brw);
}
uint32_t ctx_id;
int period_exponent;
- if (drm_intel_gem_context_get_id(brw->hw_ctx, &ctx_id) != 0)
+ if (drm_bacon_gem_context_get_id(brw->hw_ctx, &ctx_id) != 0)
return false;
/* The timestamp for HSW+ increments every 80ns
}
if (obj->oa.bo) {
- drm_intel_bo_unreference(obj->oa.bo);
+ drm_bacon_bo_unreference(obj->oa.bo);
obj->oa.bo = NULL;
}
obj->oa.bo =
- drm_intel_bo_alloc(brw->bufmgr, "perf. query OA MI_RPC bo",
+ drm_bacon_bo_alloc(brw->bufmgr, "perf. query OA MI_RPC bo",
MI_RPC_BO_SIZE, 64);
#ifdef DEBUG
/* Pre-filling the BO helps debug whether writes landed. */
- drm_intel_bo_map(obj->oa.bo, true);
+ drm_bacon_bo_map(obj->oa.bo, true);
memset((char *) obj->oa.bo->virtual, 0x80, MI_RPC_BO_SIZE);
- drm_intel_bo_unmap(obj->oa.bo);
+ drm_bacon_bo_unmap(obj->oa.bo);
#endif
obj->oa.begin_report_id = brw->perfquery.next_query_start_report_id;
case PIPELINE_STATS:
if (obj->pipeline_stats.bo) {
- drm_intel_bo_unreference(obj->pipeline_stats.bo);
+ drm_bacon_bo_unreference(obj->pipeline_stats.bo);
obj->pipeline_stats.bo = NULL;
}
obj->pipeline_stats.bo =
- drm_intel_bo_alloc(brw->bufmgr, "perf. query pipeline stats bo",
+ drm_bacon_bo_alloc(brw->bufmgr, "perf. query pipeline stats bo",
STATS_BO_SIZE, 64);
/* Take starting snapshots. */
{
struct brw_context *brw = brw_context(ctx);
struct brw_perf_query_object *obj = brw_perf_query(o);
- drm_intel_bo *bo = NULL;
+ drm_bacon_bo *bo = NULL;
assert(!o->Ready);
/* If the current batch references our results bo then we need to
* flush first...
*/
- if (drm_intel_bo_references(brw->batch.bo, bo))
+ if (drm_bacon_bo_references(brw->batch.bo, bo))
intel_batchbuffer_flush(brw);
if (unlikely(brw->perf_debug)) {
- if (drm_intel_bo_busy(bo))
+ if (drm_bacon_bo_busy(bo))
perf_debug("Stalling GPU waiting for a performance query object.\n");
}
- drm_intel_bo_wait_rendering(bo);
+ drm_bacon_bo_wait_rendering(bo);
}
static bool
case OA_COUNTERS:
return (obj->oa.results_accumulated ||
(obj->oa.bo &&
- !drm_intel_bo_references(brw->batch.bo, obj->oa.bo) &&
- !drm_intel_bo_busy(obj->oa.bo)));
+ !drm_bacon_bo_references(brw->batch.bo, obj->oa.bo) &&
+ !drm_bacon_bo_busy(obj->oa.bo)));
case PIPELINE_STATS:
return (obj->pipeline_stats.bo &&
- !drm_intel_bo_references(brw->batch.bo, obj->pipeline_stats.bo) &&
- !drm_intel_bo_busy(obj->pipeline_stats.bo));
+ !drm_bacon_bo_references(brw->batch.bo, obj->pipeline_stats.bo) &&
+ !drm_bacon_bo_busy(obj->pipeline_stats.bo));
}
unreachable("missing ready check for unknown query kind");
int n_counters = obj->query->n_counters;
uint8_t *p = data;
- drm_intel_bo_map(obj->pipeline_stats.bo, false);
+ drm_bacon_bo_map(obj->pipeline_stats.bo, false);
uint64_t *start = obj->pipeline_stats.bo->virtual;
uint64_t *end = start + (STATS_BO_END_OFFSET_BYTES / sizeof(uint64_t));
p += 8;
}
- drm_intel_bo_unmap(obj->pipeline_stats.bo);
+ drm_bacon_bo_unmap(obj->pipeline_stats.bo);
return p - data;
}
dec_n_oa_users(brw);
}
- drm_intel_bo_unreference(obj->oa.bo);
+ drm_bacon_bo_unreference(obj->oa.bo);
obj->oa.bo = NULL;
}
case PIPELINE_STATS:
if (obj->pipeline_stats.bo) {
- drm_intel_bo_unreference(obj->pipeline_stats.bo);
+ drm_bacon_bo_unreference(obj->pipeline_stats.bo);
obj->pipeline_stats.bo = NULL;
}
break;
*/
void
brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- drm_intel_bo *bo, uint32_t offset,
+ drm_bacon_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper)
{
if (brw->gen >= 8) {
* the gen6 workaround because it involves actually writing to
* the buffer, and the kernel doesn't let us write to the batch.
*/
- brw->workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
+ brw->workaround_bo = drm_bacon_bo_alloc(brw->bufmgr,
"pipe_control workaround",
4096, 4096);
if (brw->workaround_bo == NULL)
void
brw_fini_pipe_control(struct brw_context *brw)
{
- drm_intel_bo_unreference(brw->workaround_bo);
+ drm_bacon_bo_unreference(brw->workaround_bo);
}
void
brw_get_scratch_bo(struct brw_context *brw,
- drm_intel_bo **scratch_bo, int size)
+ drm_bacon_bo **scratch_bo, int size)
{
- drm_intel_bo *old_bo = *scratch_bo;
+ drm_bacon_bo *old_bo = *scratch_bo;
if (old_bo && old_bo->size < size) {
- drm_intel_bo_unreference(old_bo);
+ drm_bacon_bo_unreference(old_bo);
old_bo = NULL;
}
if (!old_bo) {
- *scratch_bo = drm_intel_bo_alloc(brw->bufmgr, "scratch bo", size, 4096);
+ *scratch_bo = drm_bacon_bo_alloc(brw->bufmgr, "scratch bo", size, 4096);
}
}
stage_state->per_thread_scratch = per_thread_size;
if (stage_state->scratch_bo)
- drm_intel_bo_unreference(stage_state->scratch_bo);
+ drm_bacon_bo_unreference(stage_state->scratch_bo);
stage_state->scratch_bo =
- drm_intel_bo_alloc(brw->bufmgr, "shader scratch space",
+ drm_bacon_bo_alloc(brw->bufmgr, "shader scratch space",
per_thread_size * thread_count, 4096);
}
}
{
const int max_entries = 2048;
brw->shader_time.bo =
- drm_intel_bo_alloc(brw->bufmgr, "shader time",
+ drm_bacon_bo_alloc(brw->bufmgr, "shader time",
max_entries * BRW_SHADER_TIME_STRIDE * 3, 4096);
brw->shader_time.names = rzalloc_array(brw, const char *, max_entries);
brw->shader_time.ids = rzalloc_array(brw, int, max_entries);
* delaying reading the reports, but it doesn't look like it's a big
* overhead compared to the cost of tracking the time in the first place.
*/
- drm_intel_bo_map(brw->shader_time.bo, true);
+ drm_bacon_bo_map(brw->shader_time.bo, true);
void *bo_map = brw->shader_time.bo->virtual;
for (int i = 0; i < brw->shader_time.num_entries; i++) {
/* Zero the BO out to clear it out for our next collection.
*/
memset(bo_map, 0, brw->shader_time.bo->size);
- drm_intel_bo_unmap(brw->shader_time.bo);
+ drm_bacon_bo_unmap(brw->shader_time.bo);
}
void
void
brw_destroy_shader_time(struct brw_context *brw)
{
- drm_intel_bo_unreference(brw->shader_time.bo);
+ drm_bacon_bo_unreference(brw->shader_time.bo);
brw->shader_time.bo = NULL;
}
brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
{
struct brw_context *brw = cache->brw;
- drm_intel_bo *new_bo;
+ drm_bacon_bo *new_bo;
- new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
+ new_bo = drm_bacon_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
if (brw->has_llc)
- drm_intel_gem_bo_map_unsynchronized(new_bo);
+ drm_bacon_gem_bo_map_unsynchronized(new_bo);
/* Copy any existing data that needs to be saved. */
if (cache->next_offset != 0) {
if (brw->has_llc) {
memcpy(new_bo->virtual, cache->bo->virtual, cache->next_offset);
} else {
- drm_intel_bo_map(cache->bo, false);
- drm_intel_bo_subdata(new_bo, 0, cache->next_offset,
+ drm_bacon_bo_map(cache->bo, false);
+ drm_bacon_bo_subdata(new_bo, 0, cache->next_offset,
cache->bo->virtual);
- drm_intel_bo_unmap(cache->bo);
+ drm_bacon_bo_unmap(cache->bo);
}
}
if (brw->has_llc)
- drm_intel_bo_unmap(cache->bo);
- drm_intel_bo_unreference(cache->bo);
+ drm_bacon_bo_unmap(cache->bo);
+ drm_bacon_bo_unreference(cache->bo);
cache->bo = new_bo;
cache->bo_used_by_gpu = false;
continue;
if (!brw->has_llc)
- drm_intel_bo_map(cache->bo, false);
+ drm_bacon_bo_map(cache->bo, false);
ret = memcmp(cache->bo->virtual + item->offset, data, item->size);
if (!brw->has_llc)
- drm_intel_bo_unmap(cache->bo);
+ drm_bacon_bo_unmap(cache->bo);
if (ret)
continue;
if (brw->has_llc) {
memcpy((char *)cache->bo->virtual + item->offset, data, data_size);
} else {
- drm_intel_bo_subdata(cache->bo, item->offset, data_size, data);
+ drm_bacon_bo_subdata(cache->bo, item->offset, data_size, data);
}
}
cache->items =
calloc(cache->size, sizeof(struct brw_cache_item *));
- cache->bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", 4096, 64);
+ cache->bo = drm_bacon_bo_alloc(brw->bufmgr, "program cache", 4096, 64);
if (brw->has_llc)
- drm_intel_gem_bo_map_unsynchronized(cache->bo);
+ drm_bacon_gem_bo_map_unsynchronized(cache->bo);
}
static void
DBG("%s\n", __func__);
if (brw->has_llc)
- drm_intel_bo_unmap(cache->bo);
- drm_intel_bo_unreference(cache->bo);
+ drm_bacon_bo_unmap(cache->bo);
+ drm_bacon_bo_unreference(cache->bo);
cache->bo = NULL;
brw_clear_cache(brw, cache);
free(cache->items);
struct brw_cache_item *item;
if (!brw->has_llc)
- drm_intel_bo_map(cache->bo, false);
+ drm_bacon_bo_map(cache->bo, false);
for (unsigned i = 0; i < cache->size; i++) {
for (item = cache->items[i]; item; item = item->next) {
}
if (!brw->has_llc)
- drm_intel_bo_unmap(cache->bo);
+ drm_bacon_bo_unmap(cache->bo);
}
* Emit PIPE_CONTROLs to write the current GPU timestamp into a buffer.
*/
void
-brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
+brw_write_timestamp(struct brw_context *brw, drm_bacon_bo *query_bo, int idx)
{
if (brw->gen == 6) {
/* Emit Sandybridge workaround flush: */
* Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
*/
void
-brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
+brw_write_depth_count(struct brw_context *brw, drm_bacon_bo *query_bo, int idx)
{
uint32_t flags = PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_DEPTH_STALL;
* still contributing to it, flush it now so the results will be present
* when mapped.
*/
- if (drm_intel_bo_references(brw->batch.bo, query->bo))
+ if (drm_bacon_bo_references(brw->batch.bo, query->bo))
intel_batchbuffer_flush(brw);
if (unlikely(brw->perf_debug)) {
- if (drm_intel_bo_busy(query->bo)) {
+ if (drm_bacon_bo_busy(query->bo)) {
perf_debug("Stalling on the GPU waiting for a query object.\n");
}
}
- drm_intel_bo_map(query->bo, false);
+ drm_bacon_bo_map(query->bo, false);
results = query->bo->virtual;
switch (query->Base.Target) {
case GL_TIME_ELAPSED_EXT:
default:
unreachable("Unrecognized query target in brw_queryobj_get_results()");
}
- drm_intel_bo_unmap(query->bo);
+ drm_bacon_bo_unmap(query->bo);
/* Now that we've processed the data stored in the query's buffer object,
* we can release it.
*/
- drm_intel_bo_unreference(query->bo);
+ drm_bacon_bo_unreference(query->bo);
query->bo = NULL;
}
{
struct brw_query_object *query = (struct brw_query_object *)q;
- drm_intel_bo_unreference(query->bo);
+ drm_bacon_bo_unreference(query->bo);
free(query);
}
* obtain the time elapsed. Notably, this includes time elapsed while
* the system was doing other work, such as running other applications.
*/
- drm_intel_bo_unreference(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "timer query", 4096, 4096);
+ drm_bacon_bo_unreference(query->bo);
+ query->bo = drm_bacon_bo_alloc(brw->bufmgr, "timer query", 4096, 4096);
brw_write_timestamp(brw, query->bo, 0);
break;
* Since we're starting a new query, we need to be sure to throw away
* any previous occlusion query results.
*/
- drm_intel_bo_unreference(query->bo);
+ drm_bacon_bo_unreference(query->bo);
query->bo = NULL;
query->last_index = -1;
* not ready yet on the first time it is queried. This ensures that
* the async query will return true in finite time.
*/
- if (query->bo && drm_intel_bo_references(brw->batch.bo, query->bo))
+ if (query->bo && drm_bacon_bo_references(brw->batch.bo, query->bo))
intel_batchbuffer_flush(brw);
- if (query->bo == NULL || !drm_intel_bo_busy(query->bo)) {
+ if (query->bo == NULL || !drm_bacon_bo_busy(query->bo)) {
brw_queryobj_get_results(ctx, query);
query->Base.Ready = true;
}
brw_queryobj_get_results(ctx, query);
}
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "query", 4096, 1);
+ query->bo = drm_bacon_bo_alloc(brw->bufmgr, "query", 4096, 1);
query->last_index = 0;
}
}
assert(q->Target == GL_TIMESTAMP);
- drm_intel_bo_unreference(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "timestamp query", 4096, 4096);
+ drm_bacon_bo_unreference(query->bo);
+ query->bo = drm_bacon_bo_alloc(brw->bufmgr, "timestamp query", 4096, 4096);
brw_write_timestamp(brw, query->bo, 0);
query->flushed = false;
switch (brw->screen->hw_has_timestamp) {
case 3: /* New kernel, always full 36bit accuracy */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP | 1, &result);
+ drm_bacon_reg_read(brw->bufmgr, TIMESTAMP | 1, &result);
break;
case 2: /* 64bit kernel, result is left-shifted by 32bits, losing 4bits */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result);
+ drm_bacon_reg_read(brw->bufmgr, TIMESTAMP, &result);
result = result >> 32;
break;
case 1: /* 32bit kernel, result is 36bit wide but may be inaccurate! */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result);
+ drm_bacon_reg_read(brw->bufmgr, TIMESTAMP, &result);
break;
}
if (brw->reset_count != 0)
return GL_NO_ERROR;
- err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
+ err = drm_bacon_get_reset_stats(brw->hw_ctx, &reset_count, &active,
&pending);
if (err)
return GL_NO_ERROR;
uint32_t pending;
int err;
- err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
+ err = drm_bacon_get_reset_stats(brw->hw_ctx, &reset_count, &active,
&pending);
if (err)
return;
ss[2] = border_color_offset;
if (brw->gen < 6) {
ss[2] += brw->batch.bo->offset64; /* reloc */
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
I915_GEM_DOMAIN_SAMPLER, 0);
{
struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
- drm_intel_bo *bo = brw->batch.bo;
+ drm_bacon_bo *bo = brw->batch.bo;
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
*/
/* Emit SF viewport relocation */
- drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
+ drm_bacon_bo_emit_reloc(bo, (brw->sf.state_offset +
offsetof(struct brw_sf_unit_state, sf5)),
brw->batch.bo, (brw->sf.vp_offset |
sf->sf5.front_winding |
void brw_emit_buffer_surface_state(struct brw_context *brw,
uint32_t *out_offset,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
unsigned buffer_offset,
unsigned surface_format,
unsigned buffer_size,
} type;
union {
- drm_intel_bo *batch_bo;
+ drm_bacon_bo *batch_bo;
/* This struct owns the fd. */
int sync_fd;
switch (fence->type) {
case BRW_FENCE_TYPE_BO_WAIT:
if (fence->batch_bo)
- drm_intel_bo_unreference(fence->batch_bo);
+ drm_bacon_bo_unreference(fence->batch_bo);
break;
case BRW_FENCE_TYPE_SYNC_FD:
if (fence->sync_fd != -1)
assert(!fence->signalled);
fence->batch_bo = brw->batch.bo;
- drm_intel_bo_reference(fence->batch_bo);
+ drm_bacon_bo_reference(fence->batch_bo);
if (intel_batchbuffer_flush(brw) < 0) {
- drm_intel_bo_unreference(fence->batch_bo);
+ drm_bacon_bo_unreference(fence->batch_bo);
fence->batch_bo = NULL;
return false;
}
return false;
}
- if (drm_intel_bo_busy(fence->batch_bo))
+ if (drm_bacon_bo_busy(fence->batch_bo))
return false;
- drm_intel_bo_unreference(fence->batch_bo);
+ drm_bacon_bo_unreference(fence->batch_bo);
fence->batch_bo = NULL;
fence->signalled = true;
if (timeout > INT64_MAX)
timeout = INT64_MAX;
- if (drm_intel_gem_bo_wait(fence->batch_bo, timeout) != 0)
+ if (drm_bacon_gem_bo_wait(fence->batch_bo, timeout) != 0)
return false;
fence->signalled = true;
- drm_intel_bo_unreference(fence->batch_bo);
+ drm_bacon_bo_unreference(fence->batch_bo);
fence->batch_bo = NULL;
return true;
st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
if (unlikely(brw->perf_debug)) {
- start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo);
+ start_busy = brw->batch.last_bo && drm_bacon_bo_busy(brw->batch.last_bo);
start_time = get_time();
}
tcp->compiled_once = true;
}
- if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
+ if (start_busy && !drm_bacon_bo_busy(brw->batch.last_bo)) {
perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
st_index = brw_get_shader_time_index(brw, &tep->program, ST_TES, true);
if (unlikely(brw->perf_debug)) {
- start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo);
+ start_busy = brw->batch.last_bo && drm_bacon_bo_busy(brw->batch.last_bo);
start_time = get_time();
}
if (tep->compiled_once) {
brw_tes_debug_recompile(brw, &tep->program, key);
}
- if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
+ if (start_busy && !drm_bacon_bo_busy(brw->batch.last_bo)) {
perf_debug("TES compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
if (unlikely(brw->perf_debug)) {
start_busy = (brw->batch.last_bo &&
- drm_intel_bo_busy(brw->batch.last_bo));
+ drm_bacon_bo_busy(brw->batch.last_bo));
start_time = get_time();
}
if (vp->compiled_once) {
brw_vs_debug_recompile(brw, &vp->program, key);
}
- if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
+ if (start_busy && !drm_bacon_bo_busy(brw->batch.last_bo)) {
perf_debug("VS compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
vs->vs5.sampler_state_pointer =
(brw->batch.bo->offset64 + stage_state->sampler_offset) >> 5;
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
stage_state->state_offset +
offsetof(struct brw_vs_unit_state, vs5),
brw->batch.bo,
/* Emit scratch space relocation */
if (prog_data->total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
stage_state->state_offset +
offsetof(struct brw_vs_unit_state, thread2),
stage_state->scratch_bo,
/* BRW_NEW_*_PROG_DATA | _NEW_PROGRAM_CONSTANTS */
uint32_t size = prog_data->nr_pull_params * 4;
- drm_intel_bo *const_bo = NULL;
+ drm_bacon_bo *const_bo = NULL;
uint32_t const_offset;
gl_constant_value *constants = intel_upload_space(brw, size, 64,
&const_bo, &const_offset);
brw_create_constant_surface(brw, const_bo, const_offset, size,
&stage_state->surf_offset[surf_index]);
- drm_intel_bo_unreference(const_bo);
+ drm_bacon_bo_unreference(const_bo);
brw->ctx.NewDriverState |= brw_new_constbuf;
}
if (unlikely(brw->perf_debug)) {
start_busy = (brw->batch.last_bo &&
- drm_intel_bo_busy(brw->batch.last_bo));
+ drm_bacon_bo_busy(brw->batch.last_bo));
start_time = get_time();
}
brw_wm_debug_recompile(brw, &fp->program, key);
fp->compiled_once = true;
- if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
+ if (start_busy && !drm_bacon_bo_busy(brw->batch.last_bo)) {
perf_debug("FS compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
/* Emit scratch space relocation */
if (prog_data->base.total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, thread2),
brw->wm.base.scratch_bo,
/* Emit sampler state relocation */
if (brw->wm.base.sampler_count != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, wm4),
brw->batch.bo, (brw->wm.base.sampler_offset |
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
- drm_intel_bo *aux_bo;
+ drm_bacon_bo *aux_bo;
struct isl_surf *aux_surf = NULL, aux_surf_s;
uint64_t aux_offset = 0;
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
.mocs = mocs, .clear_color = clear_color,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
*surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset,
read_domains, write_domains);
*/
assert((aux_offset & 0xfff) == 0);
uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
*surf_offset + brw->isl_dev.ss.aux_addr_offset,
aux_bo, *aux_addr - aux_bo->offset64,
read_domains, write_domains);
void
brw_emit_buffer_surface_state(struct brw_context *brw,
uint32_t *out_offset,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
unsigned buffer_offset,
unsigned surface_format,
unsigned buffer_size,
.mocs = tex_mocs[brw->gen]);
if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
*out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
struct intel_buffer_object *intel_obj =
intel_buffer_object(tObj->BufferObject);
uint32_t size = tObj->BufferSize;
- drm_intel_bo *bo = NULL;
+ drm_bacon_bo *bo = NULL;
mesa_format format = tObj->_BufferObjectFormat;
uint32_t brw_format = brw_isl_format_for_mesa_format(format);
int texel_size = _mesa_get_format_bytes(format);
*/
void
brw_create_constant_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset)
*/
void
brw_create_buffer_surface(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t offset,
uint32_t size,
uint32_t *out_offset)
{
struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
uint32_t offset_bytes = 4 * offset_dwords;
- drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
+ drm_bacon_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
offset_bytes,
buffer_obj->Size - offset_bytes);
uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset);
surf[5] = 0;
/* Emit relocation to surface contents. */
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
bo, offset_bytes,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
* - Surface Format must be R8G8B8A8_UNORM.
*/
unsigned surface_type = BRW_SURFACE_NULL;
- drm_intel_bo *bo = NULL;
+ drm_bacon_bo *bo = NULL;
unsigned pitch_minus_1 = 0;
uint32_t multisampling_state = 0;
uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset);
surf[5] = 0;
if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ drm_bacon_bo_emit_reloc(brw->batch.bo,
offset + 4,
mt->bo,
surf[1] - mt->bo->offset64,
GLsizeiptr size = binding->BufferObject->Size - binding->Offset;
if (!binding->AutomaticSize)
size = MIN2(size, binding->Size);
- drm_intel_bo *bo =
+ drm_bacon_bo *bo =
intel_bufferobj_buffer(brw, intel_bo,
binding->Offset,
size);
GLsizeiptr size = binding->BufferObject->Size - binding->Offset;
if (!binding->AutomaticSize)
size = MIN2(size, binding->Size);
- drm_intel_bo *bo =
+ drm_bacon_bo *bo =
intel_bufferobj_buffer(brw, intel_bo,
binding->Offset,
size);
&ctx->AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding];
struct intel_buffer_object *intel_bo =
intel_buffer_object(binding->BufferObject);
- drm_intel_bo *bo = intel_bufferobj_buffer(
+ drm_bacon_bo *bo = intel_bufferobj_buffer(
brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
const unsigned surf_idx =
cs_prog_data->binding_table.work_groups_start;
uint32_t *surf_offset = &brw->cs.base.surf_offset[surf_idx];
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
uint32_t bo_offset;
if (brw->compute.num_work_groups_bo == NULL) {
static void
write_primitives_generated(struct brw_context *brw,
- drm_intel_bo *query_bo, int stream, int idx)
+ drm_bacon_bo *query_bo, int stream, int idx)
{
brw_emit_mi_flush(brw);
static void
write_xfb_primitives_written(struct brw_context *brw,
- drm_intel_bo *bo, int stream, int idx)
+ drm_bacon_bo *bo, int stream, int idx)
{
brw_emit_mi_flush(brw);
static void
write_xfb_overflow_streams(struct gl_context *ctx,
- drm_intel_bo *bo, int stream, int count,
+ drm_bacon_bo *bo, int stream, int count,
int idx)
{
struct brw_context *brw = brw_context(ctx);
}
static void
-emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo,
+emit_pipeline_stat(struct brw_context *brw, drm_bacon_bo *bo,
int stream, int target, int idx)
{
/* One source of confusion is the tessellation shader statistics. The
default:
unreachable("Unrecognized query target in brw_queryobj_get_results()");
}
- drm_intel_bo_unmap(query->bo);
+ drm_bacon_bo_unmap(query->bo);
/* Now that we've processed the data stored in the query's buffer object,
* we can release it.
*/
- drm_intel_bo_unreference(query->bo);
+ drm_bacon_bo_unreference(query->bo);
query->bo = NULL;
query->Base.Ready = true;
struct brw_query_object *query = (struct brw_query_object *)q;
/* Since we're starting a new query, we need to throw away old results. */
- drm_intel_bo_unreference(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "query results", 4096, 4096);
+ drm_bacon_bo_unreference(query->bo);
+ query->bo = drm_bacon_bo_alloc(brw->bufmgr, "query results", 4096, 4096);
/* For ARB_query_buffer_object: The result is not available */
set_query_availability(brw, query, false);
* (for example, due to being full). Record that it's been flushed.
*/
query->flushed = query->flushed ||
- !drm_intel_bo_references(brw->batch.bo, query->bo);
+ !drm_bacon_bo_references(brw->batch.bo, query->bo);
if (!query->flushed)
intel_batchbuffer_flush(brw);
*/
flush_batch_if_needed(brw, query);
- if (!drm_intel_bo_busy(query->bo)) {
+ if (!drm_bacon_bo_busy(query->bo)) {
gen6_queryobj_get_results(ctx, query);
}
}
_mesa_init_transform_feedback_object(&brw_obj->base, name);
brw_obj->offset_bo =
- drm_intel_bo_alloc(brw->bufmgr, "transform feedback offsets", 16, 64);
+ drm_bacon_bo_alloc(brw->bufmgr, "transform feedback offsets", 16, 64);
brw_obj->prim_count_bo =
- drm_intel_bo_alloc(brw->bufmgr, "xfb primitive counts", 4096, 64);
+ drm_bacon_bo_alloc(brw->bufmgr, "xfb primitive counts", 4096, 64);
return &brw_obj->base;
}
_mesa_reference_buffer_object(ctx, &obj->Buffers[i], NULL);
}
- drm_intel_bo_unreference(brw_obj->offset_bo);
- drm_intel_bo_unreference(brw_obj->prim_count_bo);
+ drm_bacon_bo_unreference(brw_obj->offset_bo);
+ drm_bacon_bo_unreference(brw_obj->prim_count_bo);
free(brw_obj);
}
/* If the current batch is still contributing to the number of primitives
* generated, flush it now so the results will be present when mapped.
*/
- if (drm_intel_bo_references(brw->batch.bo, obj->prim_count_bo))
+ if (drm_bacon_bo_references(brw->batch.bo, obj->prim_count_bo))
intel_batchbuffer_flush(brw);
- if (unlikely(brw->perf_debug && drm_intel_bo_busy(obj->prim_count_bo)))
+ if (unlikely(brw->perf_debug && drm_bacon_bo_busy(obj->prim_count_bo)))
perf_debug("Stalling for # of transform feedback primitives written.\n");
- drm_intel_bo_map(obj->prim_count_bo, false);
+ drm_bacon_bo_map(obj->prim_count_bo, false);
uint64_t *prim_counts = obj->prim_count_bo->virtual;
assert(obj->prim_count_buffer_index % (2 * streams) == 0);
prim_counts += 2 * streams; /* move to the next pair */
}
- drm_intel_bo_unmap(obj->prim_count_bo);
+ drm_bacon_bo_unmap(obj->prim_count_bo);
/* We've already gathered up the old data; we can safely overwrite it now. */
obj->prim_count_buffer_index = 0;
for (i = 0; i < 4; i++) {
struct intel_buffer_object *bufferobj =
intel_buffer_object(xfb_obj->Buffers[i]);
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
uint32_t start, end;
uint32_t stride;
uint32_t start = xfb_obj->Offset[i];
assert(start % 4 == 0);
uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
- drm_intel_bo *bo =
+ drm_bacon_bo *bo =
intel_bufferobj_buffer(brw, bufferobj, start, end - start);
assert(end <= bo->size);
{
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
- drm_intel_bo *bo = address.buffer;
+ drm_bacon_bo *bo = address.buffer;
- drm_intel_bo_emit_reloc(brw->batch.bo, ss_offset,
+ drm_bacon_bo_emit_reloc(brw->batch.bo, ss_offset,
bo, address.offset + delta,
address.read_domains, address.write_domain);
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
intel_batchbuffer_save_state(brw);
- drm_intel_bo *saved_bo = brw->batch.bo;
+ drm_bacon_bo *saved_bo = brw->batch.bo;
uint32_t saved_used = USED_BATCH(brw->batch);
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
* map all the BOs into the GPU at batch exec time later. If so, flush the
* batch and try again with nothing else in the batch.
*/
- if (drm_intel_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
+ if (drm_bacon_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
if (!check_aperture_failed_once) {
check_aperture_failed_once = true;
intel_batchbuffer_reset_to_saved(brw);
* Store immediate data into the user buffer using the requested size.
*/
static void
-store_query_result_imm(struct brw_context *brw, drm_intel_bo *bo,
+store_query_result_imm(struct brw_context *brw, drm_bacon_bo *bo,
uint32_t offset, GLenum ptype, uint64_t imm)
{
switch (ptype) {
}
static void
-set_predicate(struct brw_context *brw, drm_intel_bo *query_bo)
+set_predicate(struct brw_context *brw, drm_bacon_bo *query_bo)
{
brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull);
* query has not finished yet.
*/
static void
-store_query_result_reg(struct brw_context *brw, drm_intel_bo *bo,
+store_query_result_reg(struct brw_context *brw, drm_bacon_bo *bo,
uint32_t offset, GLenum ptype, uint32_t reg,
const bool pipelined)
{
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include "intel_buffers.h"
#include "intel_fbo.h"
#include "brw_context.h"
static void
intel_batchbuffer_reset(struct intel_batchbuffer *batch,
- drm_intel_bufmgr *bufmgr,
+ drm_bacon_bufmgr *bufmgr,
bool has_llc);
static bool
void
intel_batchbuffer_init(struct intel_batchbuffer *batch,
- drm_intel_bufmgr *bufmgr,
+ drm_bacon_bufmgr *bufmgr,
bool has_llc)
{
intel_batchbuffer_reset(batch, bufmgr, has_llc);
static void
intel_batchbuffer_reset(struct intel_batchbuffer *batch,
- drm_intel_bufmgr *bufmgr,
+ drm_bacon_bufmgr *bufmgr,
bool has_llc)
{
if (batch->last_bo != NULL) {
- drm_intel_bo_unreference(batch->last_bo);
+ drm_bacon_bo_unreference(batch->last_bo);
batch->last_bo = NULL;
}
batch->last_bo = batch->bo;
- batch->bo = drm_intel_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
+ batch->bo = drm_bacon_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
if (has_llc) {
- drm_intel_bo_map(batch->bo, true);
+ drm_bacon_bo_map(batch->bo, true);
batch->map = batch->bo->virtual;
}
batch->map_next = batch->map;
{
brw->batch.saved.map_next = brw->batch.map_next;
brw->batch.saved.reloc_count =
- drm_intel_gem_bo_get_reloc_count(brw->batch.bo);
+ drm_bacon_gem_bo_get_reloc_count(brw->batch.bo);
}
void
intel_batchbuffer_reset_to_saved(struct brw_context *brw)
{
- drm_intel_gem_bo_clear_relocs(brw->batch.bo, brw->batch.saved.reloc_count);
+ drm_bacon_gem_bo_clear_relocs(brw->batch.bo, brw->batch.saved.reloc_count);
brw->batch.map_next = brw->batch.saved.map_next;
if (USED_BATCH(brw->batch) == 0)
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
free(batch->cpu_map);
- drm_intel_bo_unreference(batch->last_bo);
- drm_intel_bo_unreference(batch->bo);
+ drm_bacon_bo_unreference(batch->last_bo);
+ drm_bacon_bo_unreference(batch->bo);
if (batch->state_batch_sizes)
_mesa_hash_table_destroy(batch->state_batch_sizes, NULL);
}
if (batch->ring != RENDER_RING)
return;
- int ret = drm_intel_bo_map(batch->bo, false);
+ int ret = drm_bacon_bo_map(batch->bo, false);
if (ret != 0) {
fprintf(stderr,
"WARNING: failed to map batchbuffer (%s), "
}
if (ret == 0) {
- drm_intel_bo_unmap(batch->bo);
+ drm_bacon_bo_unmap(batch->bo);
}
}
#else
brw_new_batch(struct brw_context *brw)
{
/* Create a new batchbuffer and reset the associated state: */
- drm_intel_gem_bo_clear_relocs(brw->batch.bo, 0);
+ drm_bacon_gem_bo_clear_relocs(brw->batch.bo, 0);
intel_batchbuffer_reset_and_clear_render_cache(brw);
/* If the kernel supports hardware contexts, then most hardware state is
if (brw->need_swap_throttle && brw->throttle_batch[0]) {
if (brw->throttle_batch[1]) {
if (!brw->disable_throttling)
- drm_intel_bo_wait_rendering(brw->throttle_batch[1]);
- drm_intel_bo_unreference(brw->throttle_batch[1]);
+ drm_bacon_bo_wait_rendering(brw->throttle_batch[1]);
+ drm_bacon_bo_unreference(brw->throttle_batch[1]);
}
brw->throttle_batch[1] = brw->throttle_batch[0];
brw->throttle_batch[0] = NULL;
int ret = 0;
if (brw->has_llc) {
- drm_intel_bo_unmap(batch->bo);
+ drm_bacon_bo_unmap(batch->bo);
} else {
- ret = drm_intel_bo_subdata(batch->bo, 0, 4 * USED_BATCH(*batch), batch->map);
+ ret = drm_bacon_bo_subdata(batch->bo, 0, 4 * USED_BATCH(*batch), batch->map);
if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
- ret = drm_intel_bo_subdata(batch->bo,
+ ret = drm_bacon_bo_subdata(batch->bo,
batch->state_batch_offset,
batch->bo->size - batch->state_batch_offset,
(char *)batch->map + batch->state_batch_offset);
if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) {
assert(in_fence_fd == -1);
assert(out_fence_fd == NULL);
- ret = drm_intel_bo_mrb_exec(batch->bo, 4 * USED_BATCH(*batch),
+ ret = drm_bacon_bo_mrb_exec(batch->bo, 4 * USED_BATCH(*batch),
NULL, 0, 0, flags);
} else {
- ret = drm_intel_gem_bo_fence_exec(batch->bo, brw->hw_ctx,
+ ret = drm_bacon_gem_bo_fence_exec(batch->bo, brw->hw_ctx,
4 * USED_BATCH(*batch),
in_fence_fd, out_fence_fd,
flags);
if (brw->throttle_batch[0] == NULL) {
brw->throttle_batch[0] = brw->batch.bo;
- drm_intel_bo_reference(brw->throttle_batch[0]);
+ drm_bacon_bo_reference(brw->throttle_batch[0]);
}
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
fprintf(stderr, "waiting for idle\n");
- drm_intel_bo_wait_rendering(brw->batch.bo);
+ drm_bacon_bo_wait_rendering(brw->batch.bo);
}
/* Start a new batch buffer. */
*/
uint64_t
intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
- drm_intel_bo *buffer, uint32_t offset,
+ drm_bacon_bo *buffer, uint32_t offset,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
int ret;
- ret = drm_intel_bo_emit_reloc(batch->bo, offset,
+ ret = drm_bacon_bo_emit_reloc(batch->bo, offset,
buffer, delta,
read_domains, write_domain);
assert(ret == 0);
static void
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset,
int size)
void
brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
*/
void
brw_store_register_mem32(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+ drm_bacon_bo *bo, uint32_t reg, uint32_t offset)
{
assert(brw->gen >= 6);
*/
void
brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+ drm_bacon_bo *bo, uint32_t reg, uint32_t offset)
{
assert(brw->gen >= 6);
* Write 32-bits of immediate data to a GPU memory buffer.
*/
void
-brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+brw_store_data_imm32(struct brw_context *brw, drm_bacon_bo *bo,
uint32_t offset, uint32_t imm)
{
assert(brw->gen >= 6);
* Write 64-bits of immediate data to a GPU memory buffer.
*/
void
-brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+brw_store_data_imm64(struct brw_context *brw, drm_bacon_bo *bo,
uint32_t offset, uint64_t imm)
{
assert(brw->gen >= 6);
#include "main/mtypes.h"
#include "brw_context.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#ifdef __cplusplus
extern "C" {
struct intel_batchbuffer;
void intel_batchbuffer_init(struct intel_batchbuffer *batch,
- drm_intel_bufmgr *bufmgr,
+ drm_bacon_bufmgr *bufmgr,
bool has_llc);
void intel_batchbuffer_free(struct intel_batchbuffer *batch);
void intel_batchbuffer_save_state(struct brw_context *brw);
enum brw_gpu_ring ring);
uint64_t intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
- drm_intel_bo *buffer,
+ drm_bacon_bo *buffer,
uint32_t offset,
uint32_t read_domains,
uint32_t write_domain,
intelEmitCopyBlit(struct brw_context *brw,
GLuint cpp,
int32_t src_pitch,
- drm_intel_bo *src_buffer,
+ drm_bacon_bo *src_buffer,
GLuint src_offset,
uint32_t src_tiling,
int32_t dst_pitch,
- drm_intel_bo *dst_buffer,
+ drm_bacon_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
GLshort src_x, GLshort src_y,
GLuint CMD, BR13, pass = 0;
int dst_y2 = dst_y + h;
int dst_x2 = dst_x + w;
- drm_intel_bo *aper_array[3];
+ drm_bacon_bo *aper_array[3];
bool dst_y_tiled = dst_tiling == I915_TILING_Y;
bool src_y_tiled = src_tiling == I915_TILING_Y;
uint32_t src_tile_w, src_tile_h;
aper_array[1] = dst_buffer;
aper_array[2] = src_buffer;
- if (drm_intel_bufmgr_check_aperture_space(aper_array, 3) != 0) {
+ if (drm_bacon_bufmgr_check_aperture_space(aper_array, 3) != 0) {
intel_batchbuffer_flush(brw);
pass++;
} else
GLubyte *src_bits, GLuint src_size,
GLuint fg_color,
GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
+ drm_bacon_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
GLshort x, GLshort y,
*/
void
intel_emit_linear_blit(struct brw_context *brw,
- drm_intel_bo *dst_bo,
+ drm_bacon_bo *dst_bo,
unsigned int dst_offset,
- drm_intel_bo *src_bo,
+ drm_bacon_bo *src_bo,
unsigned int src_offset,
unsigned int size)
{
{
uint32_t BR13, CMD;
int pitch, cpp;
- drm_intel_bo *aper_array[2];
+ drm_bacon_bo *aper_array[2];
pitch = mt->pitch;
cpp = mt->cpp;
aper_array[0] = brw->batch.bo;
aper_array[1] = mt->bo;
- if (drm_intel_bufmgr_check_aperture_space(aper_array,
+ if (drm_bacon_bufmgr_check_aperture_space(aper_array,
ARRAY_SIZE(aper_array)) != 0) {
intel_batchbuffer_flush(brw);
}
intelEmitCopyBlit(struct brw_context *brw,
GLuint cpp,
int32_t src_pitch,
- drm_intel_bo *src_buffer,
+ drm_bacon_bo *src_buffer,
GLuint src_offset,
uint32_t src_tiling,
int32_t dst_pitch,
- drm_intel_bo *dst_buffer,
+ drm_bacon_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
GLshort srcx, GLshort srcy,
GLubyte *src_bits, GLuint src_size,
GLuint fg_color,
GLshort dst_pitch,
- drm_intel_bo *dst_buffer,
+ drm_bacon_bo *dst_buffer,
GLuint dst_offset,
uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLenum logic_op);
void intel_emit_linear_blit(struct brw_context *brw,
- drm_intel_bo *dst_bo,
+ drm_bacon_bo *dst_bo,
unsigned int dst_offset,
- drm_intel_bo *src_bo,
+ drm_bacon_bo *src_bo,
unsigned int src_offset,
unsigned int size);
/**
* Map a buffer object; issue performance warnings if mapping causes stalls.
*
- * This matches the drm_intel_bo_map API, but takes an additional human-readable
+ * This matches the drm_bacon_bo_map API, but takes an additional human-readable
* name for the buffer object to use in the performance debug message.
*/
int
brw_bo_map(struct brw_context *brw,
- drm_intel_bo *bo, int write_enable,
+ drm_bacon_bo *bo, int write_enable,
const char *bo_name)
{
- if (likely(!brw->perf_debug) || !drm_intel_bo_busy(bo))
- return drm_intel_bo_map(bo, write_enable);
+ if (likely(!brw->perf_debug) || !drm_bacon_bo_busy(bo))
+ return drm_bacon_bo_map(bo, write_enable);
double start_time = get_time();
- int ret = drm_intel_bo_map(bo, write_enable);
+ int ret = drm_bacon_bo_map(bo, write_enable);
perf_debug("CPU mapping a busy %s BO stalled and took %.03f ms.\n",
bo_name, (get_time() - start_time) * 1000);
}
int
-brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo, const char *bo_name)
+brw_bo_map_gtt(struct brw_context *brw, drm_bacon_bo *bo, const char *bo_name)
{
- if (likely(!brw->perf_debug) || !drm_intel_bo_busy(bo))
- return drm_intel_gem_bo_map_gtt(bo);
+ if (likely(!brw->perf_debug) || !drm_bacon_bo_busy(bo))
+ return drm_bacon_gem_bo_map_gtt(bo);
double start_time = get_time();
- int ret = drm_intel_gem_bo_map_gtt(bo);
+ int ret = drm_bacon_gem_bo_map_gtt(bo);
perf_debug("GTT mapping a busy %s BO stalled and took %.03f ms.\n",
bo_name, (get_time() - start_time) * 1000);
intel_obj->gpu_active_end = 0;
}
-/** Allocates a new drm_intel_bo to store the data for the buffer object. */
+/** Allocates a new drm_bacon_bo to store the data for the buffer object. */
static void
alloc_buffer_object(struct brw_context *brw,
struct intel_buffer_object *intel_obj)
{
- intel_obj->buffer = drm_intel_bo_alloc(brw->bufmgr, "bufferobj",
+ intel_obj->buffer = drm_bacon_bo_alloc(brw->bufmgr, "bufferobj",
intel_obj->Base.Size, 64);
/* the buffer might be bound as a uniform buffer, need to update it
static void
release_buffer(struct intel_buffer_object *intel_obj)
{
- drm_intel_bo_unreference(intel_obj->buffer);
+ drm_bacon_bo_unreference(intel_obj->buffer);
intel_obj->buffer = NULL;
}
*/
_mesa_buffer_unmap_all_mappings(ctx, obj);
- drm_intel_bo_unreference(intel_obj->buffer);
+ drm_bacon_bo_unreference(intel_obj->buffer);
_mesa_delete_buffer_object(ctx, obj);
}
return false;
if (data != NULL)
- drm_intel_bo_subdata(intel_obj->buffer, 0, size, data);
+ drm_bacon_bo_subdata(intel_obj->buffer, 0, size, data);
}
return true;
if (offset + size <= intel_obj->gpu_active_start ||
intel_obj->gpu_active_end <= offset) {
if (brw->has_llc) {
- drm_intel_gem_bo_map_unsynchronized(intel_obj->buffer);
+ drm_bacon_gem_bo_map_unsynchronized(intel_obj->buffer);
memcpy(intel_obj->buffer->virtual + offset, data, size);
- drm_intel_bo_unmap(intel_obj->buffer);
+ drm_bacon_bo_unmap(intel_obj->buffer);
if (intel_obj->gpu_active_end > intel_obj->gpu_active_start)
intel_obj->prefer_stall_to_blit = true;
}
busy =
- drm_intel_bo_busy(intel_obj->buffer) ||
- drm_intel_bo_references(brw->batch.bo, intel_obj->buffer);
+ drm_bacon_bo_busy(intel_obj->buffer) ||
+ drm_bacon_bo_references(brw->batch.bo, intel_obj->buffer);
if (busy) {
if (size == intel_obj->Base.Size) {
/* Replace the current busy bo so the subdata doesn't stall. */
- drm_intel_bo_unreference(intel_obj->buffer);
+ drm_bacon_bo_unreference(intel_obj->buffer);
alloc_buffer_object(brw, intel_obj);
} else if (!intel_obj->prefer_stall_to_blit) {
perf_debug("Using a blit copy to avoid stalling on "
(long)offset, (long)offset + size, (long)(size/1024),
intel_obj->gpu_active_start,
intel_obj->gpu_active_end);
- drm_intel_bo *temp_bo =
- drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64);
+ drm_bacon_bo *temp_bo =
+ drm_bacon_bo_alloc(brw->bufmgr, "subdata temp", size, 64);
- drm_intel_bo_subdata(temp_bo, 0, size, data);
+ drm_bacon_bo_subdata(temp_bo, 0, size, data);
intel_emit_linear_blit(brw,
intel_obj->buffer, offset,
temp_bo, 0,
size);
- drm_intel_bo_unreference(temp_bo);
+ drm_bacon_bo_unreference(temp_bo);
return;
} else {
perf_debug("Stalling on glBufferSubData(%ld, %ld) (%ldkb) to a busy "
}
}
- drm_intel_bo_subdata(intel_obj->buffer, offset, size, data);
+ drm_bacon_bo_subdata(intel_obj->buffer, offset, size, data);
mark_buffer_inactive(intel_obj);
}
struct brw_context *brw = brw_context(ctx);
assert(intel_obj);
- if (drm_intel_bo_references(brw->batch.bo, intel_obj->buffer)) {
+ if (drm_bacon_bo_references(brw->batch.bo, intel_obj->buffer)) {
intel_batchbuffer_flush(brw);
}
- drm_intel_bo_get_subdata(intel_obj->buffer, offset, size, data);
+ drm_bacon_bo_get_subdata(intel_obj->buffer, offset, size, data);
mark_buffer_inactive(intel_obj);
}
* achieve the required synchronization.
*/
if (!(access & GL_MAP_UNSYNCHRONIZED_BIT)) {
- if (drm_intel_bo_references(brw->batch.bo, intel_obj->buffer)) {
+ if (drm_bacon_bo_references(brw->batch.bo, intel_obj->buffer)) {
if (access & GL_MAP_INVALIDATE_BUFFER_BIT) {
- drm_intel_bo_unreference(intel_obj->buffer);
+ drm_bacon_bo_unreference(intel_obj->buffer);
alloc_buffer_object(brw, intel_obj);
} else {
perf_debug("Stalling on the GPU for mapping a busy buffer "
"object\n");
intel_batchbuffer_flush(brw);
}
- } else if (drm_intel_bo_busy(intel_obj->buffer) &&
+ } else if (drm_bacon_bo_busy(intel_obj->buffer) &&
(access & GL_MAP_INVALIDATE_BUFFER_BIT)) {
- drm_intel_bo_unreference(intel_obj->buffer);
+ drm_bacon_bo_unreference(intel_obj->buffer);
alloc_buffer_object(brw, intel_obj);
}
}
*/
if (!(access & (GL_MAP_UNSYNCHRONIZED_BIT | GL_MAP_PERSISTENT_BIT)) &&
(access & GL_MAP_INVALIDATE_RANGE_BIT) &&
- drm_intel_bo_busy(intel_obj->buffer)) {
+ drm_bacon_bo_busy(intel_obj->buffer)) {
/* Ensure that the base alignment of the allocation meets the alignment
* guarantees the driver has advertised to the application.
*/
const unsigned alignment = ctx->Const.MinMapBufferAlignment;
intel_obj->map_extra[index] = (uintptr_t) offset % alignment;
- intel_obj->range_map_bo[index] = drm_intel_bo_alloc(brw->bufmgr,
+ intel_obj->range_map_bo[index] = drm_bacon_bo_alloc(brw->bufmgr,
"BO blit temp",
length +
intel_obj->map_extra[index],
brw_bo_map(brw, intel_obj->range_map_bo[index],
(access & GL_MAP_WRITE_BIT) != 0, "range-map");
} else {
- drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
+ drm_bacon_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
}
obj->Mappings[index].Pointer =
intel_obj->range_map_bo[index]->virtual + intel_obj->map_extra[index];
if (access & GL_MAP_UNSYNCHRONIZED_BIT) {
if (!brw->has_llc && brw->perf_debug &&
- drm_intel_bo_busy(intel_obj->buffer)) {
+ drm_bacon_bo_busy(intel_obj->buffer)) {
perf_debug("MapBufferRange with GL_MAP_UNSYNCHRONIZED_BIT stalling (it's actually synchronized on non-LLC platforms)\n");
}
- drm_intel_gem_bo_map_unsynchronized(intel_obj->buffer);
+ drm_bacon_gem_bo_map_unsynchronized(intel_obj->buffer);
} else if (!brw->has_llc && (!(access & GL_MAP_READ_BIT) ||
(access & GL_MAP_PERSISTENT_BIT))) {
- drm_intel_gem_bo_map_gtt(intel_obj->buffer);
+ drm_bacon_gem_bo_map_gtt(intel_obj->buffer);
mark_buffer_inactive(intel_obj);
} else {
brw_bo_map(brw, intel_obj->buffer, (access & GL_MAP_WRITE_BIT) != 0,
assert(intel_obj);
assert(obj->Mappings[index].Pointer);
if (intel_obj->range_map_bo[index] != NULL) {
- drm_intel_bo_unmap(intel_obj->range_map_bo[index]);
+ drm_bacon_bo_unmap(intel_obj->range_map_bo[index]);
if (!(obj->Mappings[index].AccessFlags & GL_MAP_FLUSH_EXPLICIT_BIT)) {
intel_emit_linear_blit(brw,
*/
brw_emit_mi_flush(brw);
- drm_intel_bo_unreference(intel_obj->range_map_bo[index]);
+ drm_bacon_bo_unreference(intel_obj->range_map_bo[index]);
intel_obj->range_map_bo[index] = NULL;
} else if (intel_obj->buffer != NULL) {
- drm_intel_bo_unmap(intel_obj->buffer);
+ drm_bacon_bo_unmap(intel_obj->buffer);
}
obj->Mappings[index].Pointer = NULL;
obj->Mappings[index].Offset = 0;
* Anywhere that uses buffer objects in the pipeline should be using this to
* mark the range of the buffer that is being accessed by the pipeline.
*/
-drm_intel_bo *
+drm_bacon_bo *
intel_bufferobj_buffer(struct brw_context *brw,
struct intel_buffer_object *intel_obj,
uint32_t offset, uint32_t size)
struct brw_context *brw = brw_context(ctx);
struct intel_buffer_object *intel_src = intel_buffer_object(src);
struct intel_buffer_object *intel_dst = intel_buffer_object(dst);
- drm_intel_bo *src_bo, *dst_bo;
+ drm_bacon_bo *src_bo, *dst_bo;
if (size == 0)
return;
struct intel_buffer_object
{
struct gl_buffer_object Base;
- drm_intel_bo *buffer; /* the low-level buffer manager's buffer handle */
+ drm_bacon_bo *buffer; /* the low-level buffer manager's buffer handle */
- drm_intel_bo *range_map_bo[MAP_COUNT];
+ drm_bacon_bo *range_map_bo[MAP_COUNT];
/**
* Alignment offset from the range_map_bo temporary mapping to the returned
/* Get the bm buffer associated with a GL bufferobject:
*/
-drm_intel_bo *intel_bufferobj_buffer(struct brw_context *brw,
+drm_bacon_bo *intel_bufferobj_buffer(struct brw_context *brw,
struct intel_buffer_object *obj,
uint32_t offset,
uint32_t size);
const void *data,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ drm_bacon_bo **out_bo,
uint32_t *out_offset);
void *intel_upload_space(struct brw_context *brw,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ drm_bacon_bo **out_bo,
uint32_t *out_offset);
void intel_upload_finish(struct brw_context *brw);
#include <drm.h>
#include <i915_drm.h>
#include "libdrm_macros.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include "intel_bufmgr_priv.h"
#include "xf86drm.h"
#endif
#include "libdrm_macros.h"
#include "libdrm_lists.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include "intel_bufmgr_priv.h"
#include "intel_chipset.h"
#include "string.h"
}
void
-brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo)
+brw_render_cache_set_add_bo(struct brw_context *brw, drm_bacon_bo *bo)
{
_mesa_set_add(brw->render_cache, bo);
}
* different caches within a batchbuffer, it's all our responsibility.
*/
void
-brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo)
+brw_render_cache_set_check_flush(struct brw_context *brw, drm_bacon_bo *bo)
{
if (!_mesa_set_search(brw->render_cache, bo))
return;
struct intel_renderbuffer *irb);
void brw_render_cache_set_clear(struct brw_context *brw);
-void brw_render_cache_set_add_bo(struct brw_context *brw, drm_intel_bo *bo);
-void brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo);
+void brw_render_cache_set_add_bo(struct brw_context *brw, drm_bacon_bo *bo);
+void brw_render_cache_set_check_flush(struct brw_context *brw, drm_bacon_bo *bo);
unsigned
intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples);
#include <xf86drm.h>
#include "main/mtypes.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include <GL/internal/dri_interface.h>
#ifdef __cplusplus
struct __DRIimageRec {
struct intel_screen *screen;
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
uint32_t pitch; /**< in bytes */
GLenum internal_format;
uint32_t dri_format;
if (format == MESA_FORMAT_S_UINT8) {
/* Align to size of W tile, 64x64. */
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_bacon_bo_alloc_tiled(brw->bufmgr, "miptree",
ALIGN(mt->total_width, 64),
ALIGN(mt->total_height, 64),
mt->cpp, &mt->tiling, &pitch,
alloc_flags);
} else {
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_bacon_bo_alloc_tiled(brw->bufmgr, "miptree",
mt->total_width, mt->total_height,
mt->cpp, &mt->tiling, &pitch,
alloc_flags);
mt->total_width, mt->total_height);
mt->tiling = I915_TILING_X;
- drm_intel_bo_unreference(mt->bo);
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ drm_bacon_bo_unreference(mt->bo);
+ mt->bo = drm_bacon_bo_alloc_tiled(brw->bufmgr, "miptree",
mt->total_width, mt->total_height, mt->cpp,
&mt->tiling, &pitch, alloc_flags);
mt->pitch = pitch;
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
uint32_t tiling, swizzle;
GLenum target;
- drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
+ drm_bacon_bo_get_tiling(bo, &tiling, &swizzle);
/* Nothing will be able to use this miptree with the BO if the offset isn't
* aligned.
if (!mt)
return NULL;
- drm_intel_bo_reference(bo);
+ drm_bacon_bo_reference(bo);
mt->bo = bo;
mt->pitch = pitch;
mt->offset = offset;
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t width, uint32_t height,
uint32_t pitch)
{
if (hiz_buf->mt)
intel_miptree_release(&hiz_buf->mt);
else
- drm_intel_bo_unreference(hiz_buf->aux_base.bo);
+ drm_bacon_bo_unreference(hiz_buf->aux_base.bo);
free(hiz_buf);
}
DBG("%s deleting %p\n", __func__, *mt);
- drm_intel_bo_unreference((*mt)->bo);
+ drm_bacon_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->r8stencil_mt);
intel_miptree_hiz_buffer_free((*mt)->hiz_buf);
if ((*mt)->mcs_buf) {
- drm_intel_bo_unreference((*mt)->mcs_buf->bo);
+ drm_bacon_bo_unreference((*mt)->mcs_buf->bo);
free((*mt)->mcs_buf);
}
intel_resolve_map_clear(&(*mt)->hiz_map);
const int ret = brw_bo_map_gtt(brw, mt->mcs_buf->bo, "miptree");
if (unlikely(ret)) {
fprintf(stderr, "Failed to map mcs buffer into GTT\n");
- drm_intel_bo_unreference(mt->mcs_buf->bo);
+ drm_bacon_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
return;
}
void *data = mt->mcs_buf->bo->virtual;
memset(data, init_value, mt->mcs_buf->size);
- drm_intel_bo_unmap(mt->mcs_buf->bo);
+ drm_bacon_bo_unmap(mt->mcs_buf->bo);
}
static struct intel_miptree_aux_buffer *
* structure should go away. We use miptree create simply as a means to make
* sure all the constraints for the buffer are satisfied.
*/
- drm_intel_bo_reference(temp_mt->bo);
+ drm_bacon_bo_reference(temp_mt->bo);
intel_miptree_release(&temp_mt);
return buf;
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
*/
- buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "ccs-miptree",
+ buf->bo = drm_bacon_bo_alloc_tiled(brw->bufmgr, "ccs-miptree",
buf->pitch, buf->size / buf->pitch,
1, &tiling, &pitch, alloc_flags);
if (buf->bo) {
unsigned long pitch;
uint32_t tiling = I915_TILING_Y;
- buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ buf->aux_base.bo = drm_bacon_bo_alloc_tiled(brw->bufmgr, "hiz",
hz_width, hz_height, 1,
&tiling, &pitch,
BO_ALLOC_FOR_RENDER);
free(buf);
return NULL;
} else if (tiling != I915_TILING_Y) {
- drm_intel_bo_unreference(buf->aux_base.bo);
+ drm_bacon_bo_unreference(buf->aux_base.bo);
free(buf);
return NULL;
}
unsigned long pitch;
uint32_t tiling = I915_TILING_Y;
- buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ buf->aux_base.bo = drm_bacon_bo_alloc_tiled(brw->bufmgr, "hiz",
hz_width, hz_height, 1,
&tiling, &pitch,
BO_ALLOC_FOR_RENDER);
free(buf);
return NULL;
} else if (tiling != I915_TILING_Y) {
- drm_intel_bo_unreference(buf->aux_base.bo);
+ drm_bacon_bo_unreference(buf->aux_base.bo);
free(buf);
return NULL;
}
if (mt->mcs_buf) {
intel_miptree_all_slices_resolve_color(brw, mt, 0);
mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
- drm_intel_bo_unreference(mt->mcs_buf->bo);
+ drm_bacon_bo_unreference(mt->mcs_buf->bo);
free(mt->mcs_buf);
mt->mcs_buf = NULL;
*/
intel_miptree_all_slices_resolve_color(brw, mt, 0);
- drm_intel_bo *bo = mt->bo;
+ drm_bacon_bo *bo = mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo))
+ if (drm_bacon_bo_references(brw->batch.bo, bo))
intel_batchbuffer_flush(brw);
/* brw_bo_map() uses a WB mmaping of the buffer's backing storage. It
static void
intel_miptree_unmap_raw(struct intel_mipmap_tree *mt)
{
- drm_intel_bo_unmap(mt->bo);
+ drm_bacon_bo_unmap(mt->bo);
}
static void
* The hardware has a fixed layout of a texture depending on parameters such
* as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
* mipmap levels. The individual level/layer slices are each 2D rectangles of
- * pixels at some x/y offset from the start of the drm_intel_bo.
+ * pixels at some x/y offset from the start of the drm_bacon_bo.
*
* Original OpenGL allowed texture miplevels to be specified in arbitrary
* order, and a texture may change size over time. Thus, each
#include "main/mtypes.h"
#include "isl/isl.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include "intel_resolve_map.h"
#include <GL/internal/dri_interface.h>
* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
* @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
*/
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
/**
* Offset into bo where the surface starts.
* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
* @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
*/
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
/**
* Pitch in bytes.
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- drm_intel_bo *bo,
+ drm_bacon_bo *bo,
uint32_t width, uint32_t height,
uint32_t pitch);
struct brw_context *brw = brw_context(ctx);
struct intel_buffer_object *src = intel_buffer_object(unpack->BufferObj);
GLuint src_offset;
- drm_intel_bo *src_buffer;
+ drm_bacon_bo *src_buffer;
DBG("%s\n", __func__);
int dst_pitch;
/* The miptree's buffer. */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
int error = 0;
bo = irb->mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo)) {
+ if (drm_bacon_bo_references(brw->batch.bo, bo)) {
perf_debug("Flushing before mapping a referenced bo.\n");
intel_batchbuffer_flush(brw);
}
mem_copy
);
- drm_intel_bo_unmap(bo);
+ drm_bacon_bo_unmap(bo);
return true;
}
#include "intel_batchbuffer.h"
#include "intel_buffers.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include "intel_fbo.h"
#include "intel_mipmap_tree.h"
#include "intel_screen.h"
intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
{
uint32_t tiling, swizzle;
- drm_intel_bo_get_tiling(image->bo, &tiling, &swizzle);
+ drm_bacon_bo_get_tiling(image->bo, &tiling, &swizzle);
if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) {
_mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary",
&image->tile_x,
&image->tile_y);
- drm_intel_bo_unreference(image->bo);
+ drm_bacon_bo_unreference(image->bo);
image->bo = mt->bo;
- drm_intel_bo_reference(mt->bo);
+ drm_bacon_bo_reference(mt->bo);
}
static __DRIimage *
image->width = width;
image->height = height;
image->pitch = pitch * cpp;
- image->bo = drm_intel_bo_gem_create_from_name(screen->bufmgr, "image",
+ image->bo = drm_bacon_bo_gem_create_from_name(screen->bufmgr, "image",
name);
if (!image->bo) {
free(image);
image->format = rb->Format;
image->offset = 0;
image->data = loaderPrivate;
- drm_intel_bo_unreference(image->bo);
+ drm_bacon_bo_unreference(image->bo);
image->bo = irb->mt->bo;
- drm_intel_bo_reference(irb->mt->bo);
+ drm_bacon_bo_reference(irb->mt->bo);
image->width = rb->Width;
image->height = rb->Height;
image->pitch = irb->mt->pitch;
static void
intel_destroy_image(__DRIimage *image)
{
- drm_intel_bo_unreference(image->bo);
+ drm_bacon_bo_unreference(image->bo);
free(image);
}
return NULL;
cpp = _mesa_get_format_bytes(image->format);
- image->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, "image",
+ image->bo = drm_bacon_bo_alloc_tiled(screen->bufmgr, "image",
width, height, cpp, &tiling,
&pitch, 0);
if (image->bo == NULL) {
*value = image->bo->handle;
return true;
case __DRI_IMAGE_ATTRIB_NAME:
- return !drm_intel_bo_flink(image->bo, (uint32_t *) value);
+ return !drm_bacon_bo_flink(image->bo, (uint32_t *) value);
case __DRI_IMAGE_ATTRIB_FORMAT:
*value = image->dri_format;
return true;
*value = image->planar_format->components;
return true;
case __DRI_IMAGE_ATTRIB_FD:
- return !drm_intel_bo_gem_export_to_prime(image->bo, value);
+ return !drm_bacon_bo_gem_export_to_prime(image->bo, value);
case __DRI_IMAGE_ATTRIB_FOURCC:
return intel_lookup_fourcc(image->dri_format, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
if (image == NULL)
return NULL;
- drm_intel_bo_reference(orig_image->bo);
+ drm_bacon_bo_reference(orig_image->bo);
image->bo = orig_image->bo;
image->internal_format = orig_image->internal_format;
image->planar_format = orig_image->planar_format;
size = end;
}
- image->bo = drm_intel_bo_gem_create_from_prime(screen->bufmgr,
+ image->bo = drm_bacon_bo_gem_create_from_prime(screen->bufmgr,
fds[0], size);
if (image->bo == NULL) {
free(image);
}
image->bo = parent->bo;
- drm_intel_bo_reference(parent->bo);
+ drm_bacon_bo_reference(parent->bo);
image->width = width;
image->height = height;
{
struct intel_screen *screen = sPriv->driverPrivate;
- drm_intel_bufmgr_destroy(screen->bufmgr);
+ drm_bacon_bufmgr_destroy(screen->bufmgr);
driDestroyOptionInfo(&screen->optionCache);
ralloc_free(screen);
screen->no_hw = getenv("INTEL_NO_HW") != NULL;
- screen->bufmgr = drm_intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
+ screen->bufmgr = drm_bacon_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
static bool
intel_detect_swizzling(struct intel_screen *screen)
{
- drm_intel_bo *buffer;
+ drm_bacon_bo *buffer;
unsigned long flags = 0;
unsigned long aligned_pitch;
uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
- buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test",
+ buffer = drm_bacon_bo_alloc_tiled(screen->bufmgr, "swizzle test",
64, 64, 4,
&tiling, &aligned_pitch, flags);
if (buffer == NULL)
return false;
- drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode);
- drm_intel_bo_unreference(buffer);
+ drm_bacon_bo_get_tiling(buffer, &tiling, &swizzle_mode);
+ drm_bacon_bo_unreference(buffer);
if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE)
return false;
* More recent kernels offer an interface to read the full 36bits
* everywhere.
*/
- if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
+ if (drm_bacon_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
return 3;
/* Determine if we have a 32bit or 64bit kernel by inspecting the
* upper 32bits for a rapidly changing timestamp.
*/
- if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last))
+ if (drm_bacon_reg_read(screen->bufmgr, TIMESTAMP, &last))
return 0;
upper = lower = 0;
/* The TIMESTAMP should change every 80ns, so several round trips
* through the kernel should be enough to advance it.
*/
- if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
+ if (drm_bacon_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
return 0;
upper += (dummy >> 32) != (last >> 32);
intel_detect_pipelined_register(struct intel_screen *screen,
int reg, uint32_t expected_value, bool reset)
{
- drm_intel_bo *results, *bo;
+ drm_bacon_bo *results, *bo;
uint32_t *batch;
uint32_t offset = 0;
bool success = false;
/* Create a zero'ed temporary buffer for reading our results */
- results = drm_intel_bo_alloc(screen->bufmgr, "registers", 4096, 0);
+ results = drm_bacon_bo_alloc(screen->bufmgr, "registers", 4096, 0);
if (results == NULL)
goto err;
- bo = drm_intel_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0);
+ bo = drm_bacon_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0);
if (bo == NULL)
goto err_results;
- if (drm_intel_bo_map(bo, 1))
+ if (drm_bacon_bo_map(bo, 1))
goto err_batch;
batch = bo->virtual;
/* Save the register's value back to the buffer. */
*batch++ = MI_STORE_REGISTER_MEM | (3 - 2);
*batch++ = reg;
- drm_intel_bo_emit_reloc(bo, (char *)batch -(char *)bo->virtual,
+ drm_bacon_bo_emit_reloc(bo, (char *)batch -(char *)bo->virtual,
results, offset*sizeof(uint32_t),
I915_GEM_DOMAIN_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION);
*batch++ = MI_BATCH_BUFFER_END;
- drm_intel_bo_mrb_exec(bo, ALIGN((char *)batch - (char *)bo->virtual, 8),
+ drm_bacon_bo_mrb_exec(bo, ALIGN((char *)batch - (char *)bo->virtual, 8),
NULL, 0, 0,
I915_EXEC_RENDER);
/* Check whether the value got written. */
- if (drm_intel_bo_map(results, false) == 0) {
+ if (drm_bacon_bo_map(results, false) == 0) {
success = *((uint32_t *)results->virtual + offset) == expected_value;
- drm_intel_bo_unmap(results);
+ drm_bacon_bo_unmap(results);
}
err_batch:
- drm_intel_bo_unreference(bo);
+ drm_bacon_bo_unreference(bo);
err_results:
- drm_intel_bo_unreference(results);
+ drm_bacon_bo_unreference(results);
err:
return success;
}
if (!intel_init_bufmgr(screen))
return NULL;
- screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr);
+ screen->deviceID = drm_bacon_bufmgr_gem_get_devid(screen->bufmgr);
if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
return NULL;
brw_process_intel_debug_variable();
if (INTEL_DEBUG & DEBUG_BUFMGR)
- drm_intel_bufmgr_set_debug(screen->bufmgr, true);
+ drm_bacon_bufmgr_set_debug(screen->bufmgr, true);
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
fprintf(stderr,
* Currently the entire (global) address space for all GTT maps is
* limited to 64bits. That is all objects on the system that are
* setup for GTT mmapping must fit within 64bits. An attempt to use
- * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
+ * one that exceeds the limit with fail in drm_bacon_bo_map_gtt().
*
* Long before we hit that limit, we will be practically limited by
* that any single object must fit in physical memory (RAM). The upper
struct intel_buffer {
__DRIbuffer base;
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
};
static __DRIbuffer *
uint32_t tiling = I915_TILING_X;
unsigned long pitch;
int cpp = format / 8;
- intelBuffer->bo = drm_intel_bo_alloc_tiled(screen->bufmgr,
+ intelBuffer->bo = drm_bacon_bo_alloc_tiled(screen->bufmgr,
"intelAllocateBuffer",
width,
height,
return NULL;
}
- drm_intel_bo_flink(intelBuffer->bo, &intelBuffer->base.name);
+ drm_bacon_bo_flink(intelBuffer->bo, &intelBuffer->base.name);
intelBuffer->base.attachment = attachment;
intelBuffer->base.cpp = cpp;
{
struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer;
- drm_intel_bo_unreference(intelBuffer->bo);
+ drm_bacon_bo_unreference(intelBuffer->bo);
free(intelBuffer);
}
#include <GL/internal/dri_interface.h>
#include "dri_util.h"
-#include "intel_bufmgr.h"
+#include "brw_bufmgr.h"
#include "common/gen_device_info.h"
#include "i915_drm.h"
#include "xmlconfig.h"
#define KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3 (1<<3)
#define KERNEL_ALLOWS_COMPUTE_DISPATCH (1<<4)
- drm_intel_bufmgr *bufmgr;
+ drm_bacon_bufmgr *bufmgr;
/**
* A unique ID for shader programs.
assert(intel_texobj->mt == NULL);
- drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
+ drm_bacon_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
buffer_offset,
row_stride * image->Height);
intel_texobj->mt =
struct intel_texture_image *intelImage = intel_texture_image(texImage);
bool ok;
- bool tex_busy = intelImage->mt && drm_intel_bo_busy(intelImage->mt->bo);
+ bool tex_busy = intelImage->mt && drm_bacon_bo_busy(intelImage->mt->bo);
DBG("%s mesa_format %s target %s format %s type %s level %d %dx%dx%d\n",
__func__, _mesa_get_format_name(texImage->TexFormat),
int dst_pitch;
/* The miptree's buffer. */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
int error = 0;
bo = image->mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo)) {
+ if (drm_bacon_bo_references(brw->batch.bo, bo)) {
perf_debug("Flushing before mapping a referenced bo.\n");
intel_batchbuffer_flush(brw);
}
mem_copy
);
- drm_intel_bo_unmap(bo);
+ drm_bacon_bo_unmap(bo);
return true;
}
int src_pitch;
/* The miptree's buffer. */
- drm_intel_bo *bo;
+ drm_bacon_bo *bo;
int error = 0;
bo = image->mt->bo;
- if (drm_intel_bo_references(brw->batch.bo, bo)) {
+ if (drm_bacon_bo_references(brw->batch.bo, bo)) {
perf_debug("Flushing before mapping a referenced bo.\n");
intel_batchbuffer_flush(brw);
}
mem_copy
);
- drm_intel_bo_unmap(bo);
+ drm_bacon_bo_unmap(bo);
return true;
}
struct intel_mipmap_tree *mt = intel_texture_image(texImage)->mt;
bool ok;
- bool tex_busy = mt && drm_intel_bo_busy(mt->bo);
+ bool tex_busy = mt && drm_bacon_bo_busy(mt->bo);
if (mt && mt->format == MESA_FORMAT_S_UINT8)
mt->r8stencil_needs_update = true;
if (!brw->upload.bo)
return;
- drm_intel_bo_unmap(brw->upload.bo);
- drm_intel_bo_unreference(brw->upload.bo);
+ drm_bacon_bo_unmap(brw->upload.bo);
+ drm_bacon_bo_unreference(brw->upload.bo);
brw->upload.bo = NULL;
brw->upload.next_offset = 0;
}
intel_upload_space(struct brw_context *brw,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ drm_bacon_bo **out_bo,
uint32_t *out_offset)
{
uint32_t offset;
}
if (!brw->upload.bo) {
- brw->upload.bo = drm_intel_bo_alloc(brw->bufmgr, "streamed data",
+ brw->upload.bo = drm_bacon_bo_alloc(brw->bufmgr, "streamed data",
MAX2(INTEL_UPLOAD_SIZE, size), 4096);
if (brw->has_llc)
- drm_intel_bo_map(brw->upload.bo, true);
+ drm_bacon_bo_map(brw->upload.bo, true);
else
- drm_intel_gem_bo_map_gtt(brw->upload.bo);
+ drm_bacon_gem_bo_map_gtt(brw->upload.bo);
}
brw->upload.next_offset = offset + size;
*out_offset = offset;
if (*out_bo != brw->upload.bo) {
- drm_intel_bo_unreference(*out_bo);
+ drm_bacon_bo_unreference(*out_bo);
*out_bo = brw->upload.bo;
- drm_intel_bo_reference(brw->upload.bo);
+ drm_bacon_bo_reference(brw->upload.bo);
}
return brw->upload.bo->virtual + offset;
const void *data,
uint32_t size,
uint32_t alignment,
- drm_intel_bo **out_bo,
+ drm_bacon_bo **out_bo,
uint32_t *out_offset)
{
void *dst = intel_upload_space(brw, size, alignment, out_bo, out_offset);
#include "config.h"
#endif
-#if HAVE_LIBDRM_ATOMIC_PRIMITIVES
-
#define HAS_ATOMIC_OPS 1
typedef struct {
c = old;
return c == unless;
}
-
-#endif
projects / mesa.git / commitdiff