#include "arch/alpha/max_inst_regs.hh"
#include "arch/alpha/types.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class StaticInstPtr;
#include "arch/alpha/ipr.hh"
#include "arch/alpha/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
class Checkpoint;
#include "arch/alpha/types.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#ifndef __ARCH_ALPHA_TYPES_HH__
#define __ARCH_ALPHA_TYPES_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
namespace AlphaISA {
#define __ARCH_ARM_ISA_TRAITS_HH__
#include "arch/arm/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
namespace LittleEndianGuest {};
#include "arch/arm/types.hh"
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#ifndef __ARCH_ARM_TYPES_HH__
#define __ARCH_ARM_TYPES_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
namespace ArmISA
{
#include "base/misc.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "arch/mips/types.hh"
#include "arch/mips/mips_core_specific.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
namespace LittleEndianGuest {};
#include "arch/mips/types.hh"
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#ifndef __ARCH_MIPS_TYPES_HH__
#define __ARCH_MIPS_TYPES_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
namespace MipsISA
{
#include "config/full_system.hh"
//XXX This is needed for size_t. We should use something other than size_t
//#include "kern/linux/linux.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "cpu/thread_context.hh"
#include "arch/sparc/max_inst_regs.hh"
#include "arch/sparc/sparc_traits.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class StaticInstPtr;
#include "arch/sparc/types.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/miscregfile.hh"
#include "arch/sparc/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <string>
#ifndef __ARCH_X86_BIOS_ACPI_HH__
#define __ARCH_X86_BIOS_ACPI_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
#include <vector>
#include "params/X86E820Entry.hh"
#include "params/X86E820Table.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
#include <vector>
#include "base/misc.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
// Config entry types
#include "params/X86IntelMPBaseConfigEntry.hh"
#include "params/X86SMBiosSMBiosStructure.hh"
#include "params/X86SMBiosSMBiosTable.hh"
#include "sim/byteswap.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
#include "enums/Characteristic.hh"
#include "enums/ExtCharacteristic.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
class FunctionalPort;
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
namespace X86ISA
{
#include "arch/x86/max_inst_regs.hh"
#include "arch/x86/types.hh"
#include "arch/x86/x86_traits.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class StaticInstPtr;
#include "arch/x86/faults.hh"
#include "arch/x86/miscregs.hh"
#include "arch/x86/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <string>
#include <iostream>
#include <string>
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "params/X86PagetableWalker.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
namespace X86ISA
{
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "arch/x86/isa_traits.hh"
#include "arch/x86/miscregfile.hh"
#include "arch/x86/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <string>
#include "base/misc.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "arch/x86/isa_traits.hh"
#include "arch/x86/pagetable.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
class FunctionalPort;
#include <assert.h>
-#include "sim/host.hh"
+#include "base/types.hh"
namespace X86ISA
{
#include "base/loader/symtab.hh"
#include "config/cp_annotate.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
#include "sim/startup.hh"
#include "sim/system.hh"
#include <string>
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/crc.hh"
#define ETHER_CRC_POLY_LE 0xedb88320
#ifndef __BASE_CRC_HH__
#define __BASE_CRC_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
uint32_t crc32be(const uint8_t *buf, size_t len);
uint32_t crc32le(const uint8_t *buf, size_t len);
#else
#if FAST_ALLOC_DEBUG
-#include "sim/host.hh" // for Tick
+#include "base/types.hh"
#endif
class FastAlloc
#include <string>
-#include "sim/host.hh"
+#include "base/types.hh"
#if defined(__GNUC__) && __GNUC__ >= 3
#define __hash_namespace __gnu_cxx
#include <string>
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
#include <string>
-#include "sim/host.hh"
+#include "base/types.hh"
std::string &hostname();
#include <string>
#include "base/cprintf.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/inet.hh"
using namespace std;
#include "base/range.hh"
#include "dev/etherpkt.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "dnet/os.h"
#include "dnet/eth.h"
#include <assert.h>
-#include "sim/host.hh"
+#include "base/types.hh"
// Returns the prime number one less than n.
int prevPrime(int n);
#include <limits>
#include <string>
-#include "sim/host.hh" // for Addr
+#include "base/types.hh"
class Port;
#include <limits>
#include <string>
-#include "sim/host.hh" // for Addr
+#include "base/types.hh"
class Port;
class SymbolTable;
#include "base/loader/symtab.hh"
#include "base/misc.hh"
#include "base/str.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
using namespace std;
#include <map>
#include <string>
-#include "sim/host.hh" // for Addr
+#include "base/types.hh"
class Checkpoint;
class SymbolTable
#include "base/output.hh"
#include "base/trace.hh"
#include "base/varargs.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/core.hh"
using namespace std;
#include <unistd.h>
#include "sim/async.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/misc.hh"
#include "base/pollevent.hh"
#include "sim/core.hh"
#include <string>
#include "base/range.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class Checkpoint;
#include <errno.h>
#include <unistd.h>
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/misc.hh"
#include "base/socket.hh"
#include "base/stats/info.hh"
#include "base/stats/types.hh"
#include "base/stats/visit.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class Callback;
#include "base/stats/events.hh"
#include "base/stats/output.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
#include "base/stats/types.hh"
#include "base/str.hh"
#include "base/userinfo.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
#include <string>
#include "base/mysql.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
namespace Stats {
#include "base/statistics.hh"
#include "base/stats/output.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
#include <limits>
#include <vector>
-#include "sim/host.hh"
+#include "base/types.hh"
namespace Stats {
#include <string>
#include "base/time.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
namespace Stats {
#include "base/cprintf.hh"
#include "base/match.hh"
#include "base/traceflags.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/core.hh"
namespace Trace {
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+/**
+ * @file
+ * Defines global host-dependent types:
+ * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
+ */
+
+#ifndef __BASE_TYPES_HH__
+#define __BASE_TYPES_HH__
+
+#include <inttypes.h>
+
+/** uint64_t constant */
+#define ULL(N) ((uint64_t)N##ULL)
+/** int64_t constant */
+#define LL(N) ((int64_t)N##LL)
+
+/** Statistics counter type. Not much excuse for not using a 64-bit
+ * integer here, but if you're desperate and only run short
+ * simulations you could make this 32 bits.
+ */
+typedef int64_t Counter;
+
+/**
+ * Clock cycle count type.
+ * @note using an unsigned breaks the cache.
+ */
+typedef int64_t Tick;
+
+const Tick MaxTick = LL(0x7fffffffffffffff);
+
+/**
+ * Address type
+ * This will probably be moved somewhere else in the near future.
+ * This should be at least as big as the biggest address width in use
+ * in the system, which will probably be 64 bits.
+ */
+typedef uint64_t Addr;
+
+const Addr MaxAddr = (Addr)-1;
+
+#endif // __BASE_TYPES_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
#include "params/ExeTracer.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/** Struct that defines the information passed from in between stages */
/** This information mainly goes forward through the pipeline. */
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
#include "params/InOrderTrace.hh"
#include "cpu/exetrace.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "params/IntelTrace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
class ThreadContext;
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "params/LegionTrace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
class ThreadContext;
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
#include "arch/x86/intregs.hh"
#include "arch/x86/floatregs.hh"
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
#include "cpu/o3/sat_counter.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <vector>
#include "cpu/o3/ras.hh"
#include "cpu/o3/tournament_pred.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <list>
#define __CPU_O3_BTB_HH__
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class DefaultBTB
{
#include "sim/faults.hh"
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
// Typedef for physical register index type. Although the Impl would be the
// most likely location for this, there are a few classes that need this
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/core.hh"
#if FULL_SYSTEM
#include "cpu/o3/dep_graph.hh"
#include "cpu/op_class.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class DerivO3CPUParams;
class FUPool;
#ifndef __CPU_O3_RAS_HH__
#define __CPU_O3_RAS_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
#include <vector>
/** Return address stack class, implements a simple RAS. */
#define __CPU_O3_SAT_COUNTER_HH__
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/**
* Private counter class for the internal saturating counters.
#include <vector>
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
struct ltseqnum {
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
#define __CPU_O3_TOURNAMENT_PRED_HH__
#include "cpu/o3/sat_counter.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <vector>
/**
#include <utility>
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/**
* Simple class to hold onto a list of pairs, each pair having a memory
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class FUPool;
class MemInterface;
#define __CPU_OZONE_NULL_PREDICTOR_HH__
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
template <class Impl>
class NullPredictor
#include <vector>
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
class PCEventQueue;
#include "arch/stacktrace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
class BaseCPU;
#include "base/refcnt.hh"
#include "cpu/op_class.hh"
#include "sim/faults.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
// forward declarations
struct AlphaSimpleImpl;
#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
#include "sim/byteswap.hh"
#include "dev/alpha/access.h"
#include "dev/io_device.hh"
#include "params/AlphaBackdoor.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
class BaseCPU;
#include "dev/etherpkt.hh"
#include "params/EtherLink.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
#include "params/EtherLink.hh"
#include <assert.h>
#include "base/refcnt.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/*
* Reference counted class containing ethernet packet data
#include "base/bitunion.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
/** Programmable Interval Timer (Intel 8254) */
#include "dev/mips/access.h"
#include "dev/io_device.hh"
#include "params/MipsBackdoor.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
class BaseCPU;
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/NSGigE.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/system.hh"
const char *NsRxStateStrings[] =
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/stats.hh"
using namespace std;
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/mbuf.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/system.hh"
#include "sim/arguments.hh"
#include "arch/isa_traits.hh"
#ifndef __MBUF_HH__
#define __MBUF_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
#include "arch/isa_traits.hh"
namespace tru64 {
#include "arch/vtophys.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/arguments.hh"
using namespace std;
* Cache definitions.
*/
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/fast_alloc.hh"
#include "base/misc.hh"
#include "base/range.hh"
#include "mem/cache/mshr.hh"
#include "sim/core.hh" // for curTick
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/misc.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/tags/iic.hh"
#include "mem/cache/tags/iic_repl/gen.hh"
#include "params/GenRepl.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
#include <list>
#include "cpu/smt.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
#include "base/misc.hh"
#include "base/printable.hh"
#include "mem/request.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/core.hh"
#include "arch/tlb.hh"
#include "base/hashmap.hh"
#include "mem/request.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
class Process;
#include "mem/packet_access.hh"
#include "mem/physical.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
using namespace TheISA;
#include "base/fast_alloc.hh"
#include "base/flags.hh"
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/core.hh"
class Request;
#include "arch/isa_traits.hh"
#include "mem/rubymem.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/output.hh"
// Ruby includes
if not cls.cxx_predecls:
# most derived types require this, so we just do it here once
- cls.cxx_predecls = ['#include "sim/host.hh"']
+ cls.cxx_predecls = ['#include "base/types.hh"']
if not cls.swig_predecls:
# most derived types require this, so we just do it here once
cls.swig_predecls = ['%import "stdint.i"\n' +
- '%import "sim/host.hh"']
+ '%import "base/types.hh"']
if not (hasattr(cls, 'min') and hasattr(cls, 'max')):
if not (hasattr(cls, 'size') and hasattr(cls, 'unsigned')):
class TickParamValue(NumericParamValue):
cxx_type = 'Tick'
- cxx_predecls = ['#include "sim/host.hh"']
+ cxx_predecls = ['#include "base/types.hh"']
swig_predecls = ['%import "stdint.i"\n' +
- '%import "sim/host.hh"']
+ '%import "base/types.hh"']
def getValue(self):
return long(self.value)
# An explicit conversion to a Latency or Frequency must be made first.
class Clock(ParamValue):
cxx_type = 'Tick'
- cxx_predecls = ['#include "sim/host.hh"']
+ cxx_predecls = ['#include "base/types.hh"']
swig_predecls = ['%import "stdint.i"\n' +
- '%import "sim/host.hh"']
+ '%import "base/types.hh"']
def __init__(self, value):
if isinstance(value, (Latency, Clock)):
self.ticks = value.ticks
#include "base/misc.hh"
#include "base/socket.hh"
#include "sim/core.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/startup.hh"
extern const char *compileDate;
%include "stdint.i"
%include "std_string.i"
-%include "sim/host.hh"
+%include "base/types.hh"
void setOutputDir(const std::string &dir);
void SimStartup();
%module debug
%{
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/debug.hh"
%}
%include "stdint.i"
-%include "sim/host.hh"
+%include "base/types.hh"
%include "sim/debug.hh"
%wrapper %{
%{
#include "python/swig/pyevent.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/eventq.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
%include "stdint.i"
%include "std_string.i"
-%include "sim/host.hh"
+%include "base/types.hh"
%include "sim/eventq.hh"
%include "python/swig/pyevent.hh"
#include <Python.h>
#include "cpu/base.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
%{
#include <cstdlib>
-#include "sim/host.hh"
+#include "base/types.hh"
inline void
seed(uint64_t seed)
%rename(assign) *::operator=;
%include "base/range.hh"
-%include "sim/host.hh"
+%include "base/types.hh"
%template(AddrRange) Range<Addr>;
%template(TickRange) Range<Tick>;
// import these files for SWIG to wrap
%include "stdint.i"
%include "std_string.i"
-%include "sim/host.hh"
+%include "base/types.hh"
class BaseCPU;
%{
#include "base/trace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
inline void
output(const char *filename)
#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "mem/vport.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
#include "base/bigint.hh"
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
// This lets us figure out what the byte order of the host system is
#if defined(linux)
#include <string>
-#include "sim/host.hh"
+#include "base/types.hh"
/// The universal simulation clock.
extern Tick curTick;
#ifndef __SIM_DEBUG_HH__
#define __SIM_DEBUG_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
void schedBreakCycle(Tick when);
#include "base/misc.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class EventQueue; // forward declaration
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-/**
- * @file
- * Defines host-dependent types:
- * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
- */
-
-#ifndef __HOST_HH__
-#define __HOST_HH__
-
-#include <inttypes.h>
-
-/** uint64_t constant */
-#define ULL(N) ((uint64_t)N##ULL)
-/** int64_t constant */
-#define LL(N) ((int64_t)N##LL)
-
-/** Statistics counter type. Not much excuse for not using a 64-bit
- * integer here, but if you're desperate and only run short
- * simulations you could make this 32 bits.
- */
-typedef int64_t Counter;
-
-/**
- * Clock cycle count type.
- * @note using an unsigned breaks the cache.
- */
-typedef int64_t Tick;
-
-const Tick MaxTick = LL(0x7fffffffffffffff);
-
-/**
- * Address type
- * This will probably be moved somewhere else in the near future.
- * This should be at least as big as the biggest address width in use
- * in the system, which will probably be 64 bits.
- */
-typedef uint64_t Addr;
-
-const Addr MaxAddr = (Addr)-1;
-
-#endif // __HOST_H__
#include "base/misc.hh"
#include "sim/async.hh"
#include "sim/core.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/init.hh"
using namespace std;
#include "base/trace.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
class ThreadContext;
#include "arch/types.hh"
#include "base/statistics.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
#include "sim/syscallreturn.hh"
class ThreadContext;
//We need the "Tick" and "Addr" data types from here
-#include "sim/host.hh"
+#include "base/types.hh"
namespace PseudoInst {
#include <iostream>
#include <map>
-#include "sim/host.hh"
+#include "base/types.hh"
class IniFile;
class Serializable;
#include <string>
-#include "sim/host.hh"
+#include "base/types.hh"
// forward declaration
class Callback;
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/stats/events.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "sim/stat_control.hh"
#include "sim/async.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/simulate.hh"
* Steve Reinhardt
*/
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_events.hh"
SimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
#include <fcntl.h>
#include <sys/uio.h>
-#include "sim/host.hh" // for Addr
+#include "base/types.hh"
#include "base/chunk_generator.hh"
#include "base/intmath.hh" // for RoundUp
#include "base/misc.hh"
#include <iostream>
#include <cassert>
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/range_map.hh"
using namespace std;
#include <cassert>
#include <iostream>
-#include "sim/host.hh"
+#include "base/types.hh"
#include "base/range_map.hh"
using namespace std;
#include "base/statistics.hh"
#include "base/stats/text.hh"
#include "base/stats/mysql.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
using namespace std;
using namespace Stats;