radv: switch from nir_bcsel to nir_b32csel
authorRhys Perry <pendingchaos02@gmail.com>
Mon, 17 Dec 2018 13:51:09 +0000 (13:51 +0000)
committerRhys Perry <pendingchaos02@gmail.com>
Mon, 17 Dec 2018 14:52:39 +0000 (14:52 +0000)
Fixes: 191a1dce928 ('nir: Add 1-bit Boolean opcodes')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/amd/vulkan/radv_query.c

index 3c62b71dd6d28a4b139fac5ff72aae7e57ec879e..9797d156c882efbb699ad899e970f82f4e8d130b 100644 (file)
@@ -216,7 +216,7 @@ build_occlusion_query_shader(struct radv_device *device) {
 
        nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
                                                nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
-       nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
+       nir_ssa_def *result_size = nir_b32csel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
 
        nir_if *store_if = nir_if_create(b.shader);
        store_if->condition = nir_src_for_ssa(nir_ior(&b, nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)), nir_load_var(&b, available)));
@@ -371,7 +371,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device) {
 
        nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
                                                nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
-       nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
+       nir_ssa_def *elem_size = nir_b32csel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
        nir_ssa_def *elem_count = nir_ushr(&b, stats_mask, nir_imm_int(&b, 16));
 
        /* Store the availability bit if requested. */
@@ -669,8 +669,8 @@ build_tfb_query_shader(struct radv_device *device)
        nir_ssa_def *result_is_64bit =
                nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
        nir_ssa_def *result_size =
-               nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 16),
-                         nir_imm_int(&b, 8));
+               nir_b32csel(&b, result_is_64bit, nir_imm_int(&b, 16),
+                           nir_imm_int(&b, 8));
 
        /* Store the result if complete or partial results have been requested. */
        nir_if *store_if = nir_if_create(b.shader);