util: add cpu detection for sse 4.2 and avx
authorBrian Paul <brianp@vmware.com>
Thu, 7 Apr 2011 19:41:52 +0000 (13:41 -0600)
committerBrian Paul <brianp@vmware.com>
Thu, 7 Apr 2011 19:41:52 +0000 (13:41 -0600)
src/gallium/auxiliary/util/u_cpu_detect.c
src/gallium/auxiliary/util/u_cpu_detect.h

index c9d5a9e6dd1836a2ddb543dc03c5cd2770a60387..e0c8f73c7d32d8852037d39bd3267f9dbc001465 100644 (file)
@@ -277,6 +277,8 @@ util_cpu_detect(void)
          util_cpu_caps.has_sse3   = (regs2[2] >>  0) & 1; /* 0x0000001 */
          util_cpu_caps.has_ssse3  = (regs2[2] >>  9) & 1; /* 0x0000020 */
          util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
+         util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
+         util_cpu_caps.has_avx    = (regs2[2] >> 28) & 1;
          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 
          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
@@ -329,6 +331,8 @@ util_cpu_detect(void)
       debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
       debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
       debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
+      debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
+      debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
       debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
       debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
       debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
index f3bef0993c71f181bf9c5a455380b53af3a030ea..856e8d7a0efd6f31eeea4bcc2c5e73a8b14133ba 100644 (file)
@@ -53,6 +53,8 @@ struct util_cpu_caps {
    unsigned has_sse3:1;
    unsigned has_ssse3:1;
    unsigned has_sse4_1:1;
+   unsigned has_sse4_2:1;
+   unsigned has_avx:1;
    unsigned has_3dnow:1;
    unsigned has_3dnow_ext:1;
    unsigned has_altivec:1;