int ir3_compile_shader_nir(struct ir3_compiler *compiler,
struct ir3_shader_variant *so);
+/* gpu pointer size in units of 32bit registers/slots */
+static inline
+unsigned ir3_pointer_size(struct ir3_compiler *compiler)
+{
+ return (compiler->gpu_id >= 500) ? 2 : 1;
+}
+
enum ir3_shader_debug {
IR3_DBG_SHADER_VS = 0x01,
IR3_DBG_SHADER_FS = 0x02,
* account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
* is the uniforms: */
unsigned ubo = regid(ctx->so->constbase.ubo, 0) - 2;
- const unsigned ptrsz = ir3_pointer_size(ctx);
+ const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
int off = 0;
*/
debug_assert((ctx->so->shader->ubo_state.size % 16) == 0);
unsigned constoff = align(ctx->so->shader->ubo_state.size / 16, 4);
- unsigned ptrsz = ir3_pointer_size(ctx);
+ unsigned ptrsz = ir3_pointer_size(ctx->compiler);
memset(&so->constbase, ~0, sizeof(so->constbase));
struct ir3_shader_variant *so);
void ir3_context_free(struct ir3_context *ctx);
-/* gpu pointer size in units of 32bit registers/slots */
-static inline
-unsigned ir3_pointer_size(struct ir3_context *ctx)
-{
- return (ctx->compiler->gpu_id >= 500) ? 2 : 1;
-}
-
struct ir3_instruction ** ir3_get_dst_ssa(struct ir3_context *ctx, nir_ssa_def *dst, unsigned n);
struct ir3_instruction ** ir3_get_dst(struct ir3_context *ctx, nir_dest *dst, unsigned n);
struct ir3_instruction * const * ir3_get_src(struct ir3_context *ctx, nir_src *src);