gallium/radeon: add radeon_surf::macro_tile_index

for indexing cik_macrotile_mode_array

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 1612c13552069376ee4a793c8bb6dd08b3086726..defa67d8bc76f061d35646385214acf996a7f617 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -388,6 +388,7 @@ struct radeon_surf {
     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
     uint32_t                    pipe_config;
     uint32_t                    num_banks;
+    uint32_t                    macro_tile_index;
 
     uint64_t                    dcc_size;
     uint64_t                    dcc_alignment;

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 5ee6be490ed82fd5ceeed94e74afd85f1ec2f308..13c1c3eefc8296f7cae56296d49b5c4320f8d21f 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -422,6 +422,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
             surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
             surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
             surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
+            surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
+         } else {
+            surf->macro_tile_index = 0;
          }
       }
    }

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 29d346727653755f6f6a550668717e57135a3948..6fb877490ea4a62138e2eaafdda744ed05968b23 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -31,6 +31,20 @@
 
 #include <radeon_surface.h>
 
+static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
+{
+       unsigned index, tileb;
+
+       tileb = 8 * 8 * surf->bpe;
+       tileb = MIN2(surf->tile_split, tileb);
+
+       for (index = 0; tileb > 64; index++)
+               tileb >>= 1;
+
+       assert(index < 16);
+       return index;
+}
+
 static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
                                      const struct radeon_surf_level *level_ws)
 {
@@ -129,6 +143,8 @@ static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
     surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
     surf_ws->stencil_offset = surf_drm->stencil_offset;
 
+    surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
+
     for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
         surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
         surf_level_drm_to_winsys(&surf_ws->stencil_level[i],