add SUBVL CSR set

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 934a6b0eeadb5ed233e87dcc5db41492d1acd399..19ebffcb26c2174f58611da2961463bc4c78350e 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -507,10 +507,17 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
       set_csr(CSR_USVMVL, get_field(val, SV_STATE_VL )+1);
       set_csr(CSR_USVVL , get_field(val, SV_STATE_MVL)+1);
+      set_csr(CSR_USVSUBVL , get_field(val, SV_STATE_SUBVL)+1);
+      // decode (and limit) src/dest VL offsets
       reg_t srcoffs = get_field(val, SV_STATE_SRCOFFS);
       reg_t destoffs = get_field(val, SV_STATE_DESTOFFS);
       state.sv().srcoffs  = std::min(srcoffs , state.sv().vl-1);
       state.sv().destoffs = std::min(destoffs, state.sv().vl-1);
+      // decode (and limit) src/dest SUBVL offsets
+      reg_t subsrcoffs = get_field(val, SV_STATE_SSVOFFS);
+      reg_t subdestoffs = get_field(val, SV_STATE_DSVOFFS);
+      state.sv().ssvoffs  = std::min(subsrcoffs , state.sv().subvl-1);
+      state.sv().dsvoffs = std::min(subdestoffs, state.sv().subvl-1);
       //int state_bank = get_field(val, SV_STATE_BANK);
       //int state_size = get_field(val, SV_STATE_SIZE);
       //set_csr(CSR_USVCFG, state_bank | (state_size << 3));
@@ -521,7 +528,7 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       int old_bank = state.sv().state_bank;
       int old_size = state.sv().state_size;
       state.sv().state_bank = get_field(val, SV_CFG_BANK);
-      state.sv().state_size = get_field(val, SV_CFG_SIZE) >> 3;
+      state.sv().state_size = get_field(val, SV_CFG_SIZE);
       if (old_bank != state.sv().state_bank ||
           old_size != state.sv().state_size)
       {