| SVP64_9 | `9` | `1` | Indicates this is a SVP64 instruction |
| TBD | `10:31` | | |
+# Register Naming
+
+SV Registers are numbered using the notation `SV[F]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.
+
+## Integer Registers
+
+Standard PowerISA Integer registers are aliased to some of the SV integer registers:
+
+| Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register |
+|---------------------:|-------------------------|---------------------:|-------------------------|---------------------:|-------------------------|---------------------:|-------------------------|
+| R0 | SVR0_00 | R8 | SVR8_00 | R16 | SVR16_00 | R24 | SVR24_00 |
+| | SVR0_01 | | SVR8_01 | | SVR16_01 | | SVR24_01 |
+| | SVR0_10 | | SVR8_10 | | SVR16_10 | | SVR24_10 |
+| | SVR0_11 | | SVR8_11 | | SVR16_11 | | SVR24_11 |
+| R1 | SVR1_00 | R9 | SVR9_00 | R17 | SVR17_00 | R25 | SVR25_00 |
+| | SVR1_01 | | SVR9_01 | | SVR17_01 | | SVR25_01 |
+| | SVR1_10 | | SVR9_10 | | SVR17_10 | | SVR25_10 |
+| | SVR1_11 | | SVR9_11 | | SVR17_11 | | SVR25_11 |
+| R2 | SVR2_00 | R10 | SVR10_00 | R18 | SVR18_00 | R26 | SVR26_00 |
+| | SVR2_01 | | SVR10_01 | | SVR18_01 | | SVR26_01 |
+| | SVR2_10 | | SVR10_10 | | SVR18_10 | | SVR26_10 |
+| | SVR2_11 | | SVR10_11 | | SVR18_11 | | SVR26_11 |
+| R3 | SVR3_00 | R11 | SVR11_00 | R19 | SVR19_00 | R27 | SVR27_00 |
+| | SVR3_01 | | SVR11_01 | | SVR19_01 | | SVR27_01 |
+| | SVR3_10 | | SVR11_10 | | SVR19_10 | | SVR27_10 |
+| | SVR3_11 | | SVR11_11 | | SVR19_11 | | SVR27_11 |
+| R4 | SVR4_00 | R12 | SVR12_00 | R20 | SVR20_00 | R28 | SVR28_00 |
+| | SVR4_01 | | SVR12_01 | | SVR20_01 | | SVR28_01 |
+| | SVR4_10 | | SVR12_10 | | SVR20_10 | | SVR28_10 |
+| | SVR4_11 | | SVR12_11 | | SVR20_11 | | SVR28_11 |
+| R5 | SVR5_00 | R13 | SVR13_00 | R21 | SVR21_00 | R29 | SVR29_00 |
+| | SVR5_01 | | SVR13_01 | | SVR21_01 | | SVR29_01 |
+| | SVR5_10 | | SVR13_10 | | SVR21_10 | | SVR29_10 |
+| | SVR5_11 | | SVR13_11 | | SVR21_11 | | SVR29_11 |
+| R6 | SVR6_00 | R14 | SVR14_00 | R22 | SVR22_00 | R30 | SVR30_00 |
+| | SVR6_01 | | SVR14_01 | | SVR22_01 | | SVR30_01 |
+| | SVR6_10 | | SVR14_10 | | SVR22_10 | | SVR30_10 |
+| | SVR6_11 | | SVR14_11 | | SVR22_11 | | SVR30_11 |
+| R7 | SVR7_00 | R15 | SVR15_00 | R23 | SVR23_00 | R31 | SVR31_00 |
+| | SVR7_01 | | SVR15_01 | | SVR23_01 | | SVR31_01 |
+| | SVR7_10 | | SVR15_10 | | SVR23_10 | | SVR31_10 |
+| | SVR7_11 | | SVR15_11 | | SVR23_11 | | SVR31_11 |
+
+## Floating-Point Registers
+
+Standard PowerISA floating-point and VSX registers are aliased to some of the SV floating-point registers:
+| FP<br/>Register | VSX Register | SV FP<br/>Register | FP<br/>Register | VSX Register | SV FP<br/>Register | FP<br/>Register | VSX Register | SV FP<br/>Register | FP<br/>Register | VSX Register | SV FP<br/>Register |
+|----------------:|------------------|--------------------|----------------:|------------------|--------------------|----------------:|------------------|--------------------|----------------:|------------------|--------------------|
+| FPR[0] | VSR[0].dword[0] | SVFR0_00 | FPR[8] | VSR[8].dword[0] | SVFR8_00 | FPR[16] | VSR[16].dword[0] | SVFR16_00 | FPR[24] | VSR[24].dword[0] | SVFR24_00 |
+| | VSR[0].dword[1] | SVFR0_01 | | VSR[8].dword[1] | SVFR8_01 | | VSR[16].dword[1] | SVFR16_01 | | VSR[24].dword[1] | SVFR24_01 |
+| | VSR[32].dword[0] | SVFR0_10 | | VSR[40].dword[0] | SVFR8_10 | | VSR[48].dword[0] | SVFR16_10 | | VSR[56].dword[0] | SVFR24_10 |
+| | VSR[32].dword[1] | SVFR0_11 | | VSR[40].dword[1] | SVFR8_11 | | VSR[48].dword[1] | SVFR16_11 | | VSR[56].dword[1] | SVFR24_11 |
+| FPR[1] | VSR[1].dword[0] | SVFR1_00 | FPR[9] | VSR[9].dword[0] | SVFR9_00 | FPR[17] | VSR[17].dword[0] | SVFR17_00 | FPR[25] | VSR[25].dword[0] | SVFR25_00 |
+| | VSR[1].dword[1] | SVFR1_01 | | VSR[9].dword[1] | SVFR9_01 | | VSR[17].dword[1] | SVFR17_01 | | VSR[25].dword[1] | SVFR25_01 |
+| | VSR[33].dword[0] | SVFR1_10 | | VSR[41].dword[0] | SVFR9_10 | | VSR[49].dword[0] | SVFR17_10 | | VSR[57].dword[0] | SVFR25_10 |
+| | VSR[33].dword[1] | SVFR1_11 | | VSR[41].dword[1] | SVFR9_11 | | VSR[49].dword[1] | SVFR17_11 | | VSR[57].dword[1] | SVFR25_11 |
+| FPR[2] | VSR[2].dword[0] | SVFR2_00 | FPR[10] | VSR[10].dword[0] | SVFR10_00 | FPR[18] | VSR[18].dword[0] | SVFR18_00 | FPR[26] | VSR[26].dword[0] | SVFR26_00 |
+| | VSR[2].dword[1] | SVFR2_01 | | VSR[10].dword[1] | SVFR10_01 | | VSR[18].dword[1] | SVFR18_01 | | VSR[26].dword[1] | SVFR26_01 |
+| | VSR[34].dword[0] | SVFR2_10 | | VSR[42].dword[0] | SVFR10_10 | | VSR[50].dword[0] | SVFR18_10 | | VSR[58].dword[0] | SVFR26_10 |
+| | VSR[34].dword[1] | SVFR2_11 | | VSR[42].dword[1] | SVFR10_11 | | VSR[50].dword[1] | SVFR18_11 | | VSR[58].dword[1] | SVFR26_11 |
+| FPR[3] | VSR[3].dword[0] | SVFR3_00 | FPR[11] | VSR[11].dword[0] | SVFR11_00 | FPR[19] | VSR[19].dword[0] | SVFR19_00 | FPR[27] | VSR[27].dword[0] | SVFR27_00 |
+| | VSR[3].dword[1] | SVFR3_01 | | VSR[11].dword[1] | SVFR11_01 | | VSR[19].dword[1] | SVFR19_01 | | VSR[27].dword[1] | SVFR27_01 |
+| | VSR[35].dword[0] | SVFR3_10 | | VSR[43].dword[0] | SVFR11_10 | | VSR[51].dword[0] | SVFR19_10 | | VSR[59].dword[0] | SVFR27_10 |
+| | VSR[35].dword[1] | SVFR3_11 | | VSR[43].dword[1] | SVFR11_11 | | VSR[51].dword[1] | SVFR19_11 | | VSR[59].dword[1] | SVFR27_11 |
+| FPR[4] | VSR[4].dword[0] | SVFR4_00 | FPR[12] | VSR[12].dword[0] | SVFR12_00 | FPR[20] | VSR[20].dword[0] | SVFR20_00 | FPR[28] | VSR[28].dword[0] | SVFR28_00 |
+| | VSR[4].dword[1] | SVFR4_01 | | VSR[12].dword[1] | SVFR12_01 | | VSR[20].dword[1] | SVFR20_01 | | VSR[28].dword[1] | SVFR28_01 |
+| | VSR[36].dword[0] | SVFR4_10 | | VSR[44].dword[0] | SVFR12_10 | | VSR[52].dword[0] | SVFR20_10 | | VSR[60].dword[0] | SVFR28_10 |
+| | VSR[36].dword[1] | SVFR4_11 | | VSR[44].dword[1] | SVFR12_11 | | VSR[52].dword[1] | SVFR20_11 | | VSR[60].dword[1] | SVFR28_11 |
+| FPR[5] | VSR[5].dword[0] | SVFR5_00 | FPR[13] | VSR[13].dword[0] | SVFR13_00 | FPR[21] | VSR[21].dword[0] | SVFR21_00 | FPR[29] | VSR[29].dword[0] | SVFR29_00 |
+| | VSR[5].dword[1] | SVFR5_01 | | VSR[13].dword[1] | SVFR13_01 | | VSR[21].dword[1] | SVFR21_01 | | VSR[29].dword[1] | SVFR29_01 |
+| | VSR[37].dword[0] | SVFR5_10 | | VSR[45].dword[0] | SVFR13_10 | | VSR[53].dword[0] | SVFR21_10 | | VSR[61].dword[0] | SVFR29_10 |
+| | VSR[37].dword[1] | SVFR5_11 | | VSR[45].dword[1] | SVFR13_11 | | VSR[53].dword[1] | SVFR21_11 | | VSR[61].dword[1] | SVFR29_11 |
+| FPR[6] | VSR[6].dword[0] | SVFR6_00 | FPR[14] | VSR[14].dword[0] | SVFR14_00 | FPR[22] | VSR[22].dword[0] | SVFR22_00 | FPR[30] | VSR[30].dword[0] | SVFR30_00 |
+| | VSR[6].dword[1] | SVFR6_01 | | VSR[14].dword[1] | SVFR14_01 | | VSR[22].dword[1] | SVFR22_01 | | VSR[30].dword[1] | SVFR30_01 |
+| | VSR[38].dword[0] | SVFR6_10 | | VSR[46].dword[0] | SVFR14_10 | | VSR[54].dword[0] | SVFR22_10 | | VSR[62].dword[0] | SVFR30_10 |
+| | VSR[38].dword[1] | SVFR6_11 | | VSR[46].dword[1] | SVFR14_11 | | VSR[54].dword[1] | SVFR22_11 | | VSR[62].dword[1] | SVFR30_11 |
+| FPR[7] | VSR[7].dword[0] | SVFR7_00 | FPR[15] | VSR[15].dword[0] | SVFR15_00 | FPR[23] | VSR[23].dword[0] | SVFR23_00 | FPR[31] | VSR[31].dword[0] | SVFR31_00 |
+| | VSR[7].dword[1] | SVFR7_01 | | VSR[15].dword[1] | SVFR15_01 | | VSR[23].dword[1] | SVFR23_01 | | VSR[31].dword[1] | SVFR31_01 |
+| | VSR[39].dword[0] | SVFR7_10 | | VSR[47].dword[0] | SVFR15_10 | | VSR[55].dword[0] | SVFR23_10 | | VSR[63].dword[0] | SVFR31_10 |
+| | VSR[39].dword[1] | SVFR7_11 | | VSR[47].dword[1] | SVFR15_11 | | VSR[55].dword[1] | SVFR23_11 | | VSR[63].dword[1] | SVFR31_11 |
+
+
# Operation
## CR fields as inputs/outputs of vector operations
## SVP64-A-FORM
-Suffix is an A-FORM Instruction
-
+Suffix is an A-FORM Instruction.
+Prefix Fields:
+| | PO (0:5) | | | |
+|--|----------|--|--|--|
+| | 1 | | | |
TBD
\ No newline at end of file
projects / libreriscv.git / commitdiff