#include "case-cfn-macros.h"
#include "sbitmap.h"
#include "stringpool.h"
+#include "arm-builtins.h"
#define SIMD_MAX_BUILTIN_ARGS 7
qualifier_unsigned_immediate };
#define CX_TERNARY_QUALIFIERS (arm_cx_ternary_qualifiers)
+/* T (immediate, T, unsigned immediate). */
+static enum arm_type_qualifiers
+arm_cx_unary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_immediate, qualifier_none,
+ qualifier_unsigned_immediate,
+ qualifier_unsigned };
+#define CX_UNARY_UNONE_QUALIFIERS (arm_cx_unary_unone_qualifiers)
+
+/* T (immediate, T, T, unsigned immediate). */
+static enum arm_type_qualifiers
+arm_cx_binary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_immediate,
+ qualifier_none, qualifier_none,
+ qualifier_unsigned_immediate,
+ qualifier_unsigned };
+#define CX_BINARY_UNONE_QUALIFIERS (arm_cx_binary_unone_qualifiers)
+
+/* T (immediate, T, T, T, unsigned immediate). */
+static enum arm_type_qualifiers
+arm_cx_ternary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_immediate,
+ qualifier_none, qualifier_none, qualifier_none,
+ qualifier_unsigned_immediate,
+ qualifier_unsigned };
+#define CX_TERNARY_UNONE_QUALIFIERS (arm_cx_ternary_unone_qualifiers)
+
/* The first argument (return type) of a store should be void type,
which we represent with qualifier_void. Their first operand will be
a DImode pointer to the location to store to, so we must use
ARM_CDE_CONST_COPROC);
}
else
- error ("%Kargument %d must be a constant immediate "
+ /* Here we mention the builtin name to follow the same
+ format that the C/C++ frontends use for referencing
+ a given argument index. */
+ error ("%Kargument %d to %qE must be a constant immediate "
"in range [0-%d]", exp, argc + 1,
+ arm_builtin_decls[fcode],
cde_builtin_data[fcode -
ARM_BUILTIN_CDE_PATTERN_START].imm_max);
}
return true;
}
-/* Implement TARGET_RESOLVE_OVERLOADED_BUILTIN. This is currently only
- used for the MVE related builtins for the CDE extension.
- Here we ensure the type of arguments is such that the size is correct, and
- then return a tree that describes the same function call but with the
- relevant types cast as necessary. */
-tree
-arm_resolve_overloaded_builtin (location_t loc, tree fndecl, void *arglist)
+enum resolver_ident
+arm_describe_resolver (tree fndecl)
{
- if (DECL_MD_FUNCTION_CODE (fndecl) <= ARM_BUILTIN_vcx1qv16qi
- || DECL_MD_FUNCTION_CODE (fndecl) >= ARM_BUILTIN_MVE_BASE)
- return NULL_TREE;
-
- vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (arglist);
- unsigned param_num = params ? params->length() : 0;
- unsigned num_args = list_length (TYPE_ARG_TYPES (TREE_TYPE (fndecl))) - 1;
- /* Ensure this function has the correct number of arguments.
- This won't happen when using the intrinsics defined by the ACLE, since
- they're exposed to the user via a wrapper in the arm_cde.h header that has
- the correct number of arguments ... hence the compiler would already catch
- an incorrect number of arguments there.
-
- It is still possible to get here if the user tries to call the __bulitin_*
- functions directly. We could print some error message in this function,
- but instead we leave it to the rest of the code to catch this problem in
- the same way that other __builtin_* functions catch it.
-
- This does mean an odd error message, but it's consistent with the rest of
- the builtins. */
- if (param_num != num_args)
- return NULL_TREE;
-
- tree to_return = NULL_TREE;
- /* Take the functions return type since that's the same type as the arguments
- this function needs (the types of the builtin function all come from the
- machine mode of the RTL pattern, and they're all the same and calculated
- in the same way). */
- tree pattern_type = TREE_TYPE (TREE_TYPE (fndecl));
-
- unsigned i;
- for (i = 1; i < (param_num - 1); i++)
- {
- tree this_param = (*params)[i];
- if (TREE_CODE (this_param) == ERROR_MARK)
- return NULL_TREE;
- tree param_type = TREE_TYPE (this_param);
-
- /* Return value is cast to type that second argument originally was.
- All non-constant arguments are cast to the return type calculated from
- the RTL pattern.
-
- Set the return type to an unqualified version of the type of the first
- parameter. The first parameter since that is how the intrinsics are
- defined -- to always return the same type as the first polymorphic
- argument. Unqualified version of the type since we don't want passing
- a constant parameter to mean that the return value of the builtin is
- also constant. */
- if (i == 1)
- to_return = build_qualified_type (param_type, 0 MEM_STAT_INFO);
-
- /* The only requirement of these intrinsics on the type of the variable
- is that it's 128 bits wide. All other types are valid and we simply
- VIEW_CONVERT_EXPR them to the type of the underlying builtin. */
- tree type_size = TYPE_SIZE (param_type);
- if (! tree_fits_shwi_p (type_size)
- || tree_to_shwi (type_size) != 128)
- {
- error_at (loc,
- "argument %u to function %qE is of type %qT which is not "
- "known to be 128 bits wide",
- i, fndecl, param_type);
- return NULL_TREE;
- }
-
- /* Only convert the argument if we actually need to. */
- if (! check_base_type (pattern_type, param_type))
- (*params)[i] = build1 (VIEW_CONVERT_EXPR, pattern_type, this_param);
- }
- tree call_expr = build_call_expr_loc_array (loc, fndecl, param_num,
- params->address());
+ if (DECL_MD_FUNCTION_CODE (fndecl) >= ARM_BUILTIN_vcx1qv16qi
+ && DECL_MD_FUNCTION_CODE (fndecl) < ARM_BUILTIN_MVE_BASE)
+ return arm_cde_resolver;
+ return arm_no_resolver;
+}
- gcc_assert (to_return != NULL_TREE);
- if (! check_base_type (to_return, pattern_type))
- return build1 (VIEW_CONVERT_EXPR, to_return, call_expr);
- return call_expr;
+unsigned
+arm_cde_end_args (tree fndecl)
+{
+ return DECL_MD_FUNCTION_CODE (fndecl) >= ARM_BUILTIN_vcx1q_p_v16qi ? 2 : 1;
}
#include "gt-arm-builtins.h"
--- /dev/null
+/* Declarations for determining resolver for a given builtin.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_ARM_BUILTINS_H
+#define GCC_ARM_BUILTINS_H
+
+enum resolver_ident {
+ arm_cde_resolver,
+ arm_no_resolver
+};
+enum resolver_ident arm_describe_resolver (tree);
+unsigned arm_cde_end_args (tree);
+
+#endif /* GCC_ARM_BUILTINS_H */
#include "tm_p.h"
#include "c-family/c-pragma.h"
#include "stringpool.h"
+#include "arm-builtins.h"
-tree arm_resolve_overloaded_builtin (location_t, tree, void*);
+tree
+arm_resolve_cde_builtin (location_t loc, tree fndecl, void *arglist)
+{
+ vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (arglist);
+ unsigned param_num = params ? params->length() : 0;
+ unsigned num_args = list_length (TYPE_ARG_TYPES (TREE_TYPE (fndecl))) - 1;
+ /* Ensure this function has the correct number of arguments.
+ This won't happen when using the intrinsics defined by the ACLE, since
+ they're exposed to the user via a wrapper in the arm_cde.h header that has
+ the correct number of arguments ... hence the compiler would already catch
+ an incorrect number of arguments there.
+
+ It is still possible to get here if the user tries to call the __bulitin_*
+ functions directly. We could print some error message in this function,
+ but instead we leave it to the rest of the code to catch this problem in
+ the same way that other __builtin_* functions catch it.
+
+ This does mean an odd error message, but it's consistent with the rest of
+ the builtins. */
+ if (param_num != num_args)
+ return NULL_TREE;
+
+ tree to_return = NULL_TREE;
+ /* Take the functions return type since that's the same type as the arguments
+ this function needs (the types of the builtin function all come from the
+ machine mode of the RTL pattern, and they're all the same and calculated
+ in the same way). */
+ tree pattern_type = TREE_TYPE (TREE_TYPE (fndecl));
+
+ unsigned i;
+ /* Hard coding the number of parameters we don't want to cast at the end of
+ the builtin. This is the easiest approach for the CDE intrinsics, and
+ introducing a parameter to store in the builtins.def macros seems overkill
+ when they're only relevant here. */
+ unsigned end_args = arm_cde_end_args (fndecl);
+ unsigned cast_param_end = param_num - end_args;
+ /* For the vcx1q patterns that don't need any casts. */
+ if (cast_param_end == 1)
+ return NULL_TREE;
+
+ /* In order to check all arguments rather than complaining on the first
+ invalid one we record whether *any* arguments are invalid using this
+ boolean variable. */
+ bool invalid = false;
+ for (i = 1; i < cast_param_end; i++)
+ {
+ tree this_param = (*params)[i];
+ if (TREE_CODE (this_param) == ERROR_MARK)
+ {
+ invalid = true;
+ continue;
+ }
+ tree param_type = TREE_TYPE (this_param);
+
+ /* Return value is cast to type that second argument originally was.
+ All non-constant arguments are cast to the return type calculated from
+ the RTL pattern.
+
+ Set the return type to an unqualified version of the type of the first
+ parameter. The first parameter since that is how the intrinsics are
+ defined -- to always return the same type as the first polymorphic
+ argument. Unqualified version of the type since we don't want passing
+ a constant parameter to mean that the return value of the builtin is
+ also constant. */
+ if (i == 1)
+ to_return = build_qualified_type (param_type, 0 MEM_STAT_INFO);
+
+ /* The only requirement of these intrinsics on the type of the variable
+ is that it's 128 bits wide. All other types are valid and we simply
+ VIEW_CONVERT_EXPR them to the type of the underlying builtin. */
+ tree type_size = TYPE_SIZE (param_type);
+ if (! tree_fits_shwi_p (type_size)
+ || tree_to_shwi (type_size) != 128)
+ {
+ error_at (loc,
+ "argument %u to function %qE is of type %qT which is not "
+ "known to be 128 bits wide",
+ i + 1, fndecl, param_type);
+ invalid = true;
+ continue;
+ }
+
+ /* Only convert the argument if we actually need to. */
+ if (! check_base_type (pattern_type, param_type))
+ (*params)[i] = build1 (VIEW_CONVERT_EXPR, pattern_type, this_param);
+ }
+ if (invalid)
+ return NULL_TREE;
+
+ /* We know it's safe to call this since this builtin is here to implement an
+ ACLE function, and those functions are only for C/C++. */
+ tree call_expr = build_function_call_vec (loc, vNULL, fndecl, params,
+ NULL, fndecl);
+
+ gcc_assert (to_return != NULL_TREE);
+ if (! check_base_type (to_return, pattern_type))
+ return build1 (VIEW_CONVERT_EXPR, to_return, call_expr);
+ return call_expr;
+}
+
+/* Implement TARGET_RESOLVE_OVERLOADED_BUILTIN. This is currently only
+ used for the MVE related builtins for the CDE extension.
+ Here we ensure the type of arguments is such that the size is correct, and
+ then return a tree that describes the same function call but with the
+ relevant types cast as necessary. */
+tree
+arm_resolve_overloaded_builtin (location_t loc, tree fndecl, void *arglist)
+{
+ if (arm_describe_resolver (fndecl) == arm_cde_resolver)
+ return arm_resolve_cde_builtin (loc, fndecl, arglist);
+ return NULL_TREE;
+}
/* Output C specific EABI object attributes. These cannot be done in
arm.c because they require information from the C frontend. */
#define __arm_vcx3qa(coproc, acc, n, m, imm) \
__builtin_arm_vcx3qav16qi(coproc, acc, n, m, imm)
+#define __arm_vcx1q_m(coproc, inactive, imm, pred) \
+ __builtin_arm_vcx1q_p_v16qi(coproc, inactive, imm, pred)
+#define __arm_vcx1qa_m(coproc, acc, imm, pred) \
+ __builtin_arm_vcx1qa_p_v16qi(coproc, acc, imm, pred)
+
+#define __arm_vcx2q_m(coproc, inactive, n, imm, pred) \
+ __builtin_arm_vcx2q_p_v16qi(coproc, inactive, n, imm, pred)
+#define __arm_vcx2qa_m(coproc, acc, n, imm, pred) \
+ __builtin_arm_vcx2qa_p_v16qi(coproc, acc, n, imm, pred)
+
+#define __arm_vcx3q_m(coproc, inactive, n, m, imm, pred) \
+ __builtin_arm_vcx3q_p_v16qi(coproc, inactive, n, m, imm, pred)
+#define __arm_vcx3qa_m(coproc, acc, n, m, imm, pred) \
+ __builtin_arm_vcx3qa_p_v16qi(coproc, acc, n, m, imm, pred)
+
#endif
#ifdef __cplusplus
CDE_VAR2 (CX_TERNARY, vcx3a, si, di, ARM_VCDE_CONST_3, ECF_CONST)
/* NOTE: The MVE intrinsics must be defined at the end of this file, and with
- vcx1q first.
+ vcx1q first. Amongst the MVE intrinsics, the predicated ones are
+ defined last.
These restrictions are relied on to determine which intrinsics need
overload resolution in `arm_resolve_overloaded_builtin`. */
VAR1 (CX_IMM, vcx1q, v16qi, ARM_MVE_CDE_CONST_1, ECF_CONST)
VAR1 (CX_BINARY, vcx3q, v16qi, ARM_MVE_CDE_CONST_3, ECF_CONST)
VAR1 (CX_TERNARY, vcx3qa, v16qi, ARM_MVE_CDE_CONST_3, ECF_CONST)
+VAR1 (CX_UNARY_UNONE, vcx1q_p_, v16qi, ARM_MVE_CDE_CONST_1, ECF_CONST)
+VAR1 (CX_UNARY_UNONE, vcx1qa_p_, v16qi, ARM_MVE_CDE_CONST_1, ECF_CONST)
+VAR1 (CX_BINARY_UNONE, vcx2q_p_, v16qi, ARM_MVE_CDE_CONST_2, ECF_CONST)
+VAR1 (CX_BINARY_UNONE, vcx2qa_p_, v16qi, ARM_MVE_CDE_CONST_2, ECF_CONST)
+VAR1 (CX_TERNARY_UNONE, vcx3q_p_, v16qi, ARM_MVE_CDE_CONST_3, ECF_CONST)
+VAR1 (CX_TERNARY_UNONE, vcx3qa_p_, v16qi, ARM_MVE_CDE_CONST_3, ECF_CONST)
#undef CDE_VAR2
return __a + __b;
}
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u8 (void)
-{
- uint8x16_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u16 (void)
-{
- uint16x8_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u32 (void)
-{
- uint32x4_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u64 (void)
-{
- uint64x2_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s8 (void)
-{
- int8x16_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s16 (void)
-{
- int16x8_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s32 (void)
-{
- int32x4_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s64 (void)
-{
- int64x2_t __uninit;
- __asm__ ("": "=w"(__uninit));
- return __uninit;
-}
-
__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vddupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p)
return __a + __b;
}
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_f16 (void)
-{
- float16x8_t __uninit;
- __asm__ ("": "=w" (__uninit));
- return __uninit;
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_f32 (void)
-{
- float32x4_t __uninit;
- __asm__ ("": "=w" (__uninit));
- return __uninit;
-}
-
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset)
return __arm_vaddq_u32 (__a, __b);
}
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (uint8x16_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_u8 ();
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (uint16x8_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_u16 ();
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (uint32x4_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_u32 ();
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (uint64x2_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_u64 ();
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (int8x16_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_s8 ();
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (int16x8_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_s16 ();
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (int32x4_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_s32 ();
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (int64x2_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_s64 ();
-}
-
__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vddupq_m (uint8x16_t __inactive, uint32_t __a, const int __imm, mve_pred16_t __p)
return __arm_vaddq_f32 (__a, __b);
}
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (float16x8_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_f16 ();
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq (float32x4_t /* __v ATTRIBUTE UNUSED */)
-{
- return __arm_vuninitializedq_f32 ();
-}
-
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vstrwq_scatter_base_wb (uint32x4_t * __addr, const int __offset, float32x4_t __value)
return (uint8x16_t) __a;
}
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_u8 (void)
+{
+ uint8x16_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_u16 (void)
+{
+ uint16x8_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_u32 (void)
+{
+ uint32x4_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_u64 (void)
+{
+ uint64x2_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_s8 (void)
+{
+ int8x16_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_s16 (void)
+{
+ int16x8_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_s32 (void)
+{
+ int32x4_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_s64 (void)
+{
+ int64x2_t __uninit;
+ __asm__ ("": "=w"(__uninit));
+ return __uninit;
+}
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline int32x4_t
return (float32x4_t) __a;
}
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_f16 (void)
+{
+ float16x8_t __uninit;
+ __asm__ ("": "=w" (__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_f32 (void)
+{
+ float32x4_t __uninit;
+ __asm__ ("": "=w" (__uninit));
+ return __uninit;
+}
+
#endif
#ifdef __cplusplus
return __arm_vreinterpretq_u8_u64 (__a);
}
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (uint8x16_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_u8 ();
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (uint16x8_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_u16 ();
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (uint32x4_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_u32 ();
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (uint64x2_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_u64 ();
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (int8x16_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_s8 ();
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (int16x8_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_s16 ();
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (int32x4_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_s32 ();
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (int64x2_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_s64 ();
+}
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
{
return __arm_vreinterpretq_f32_u8 (__a);
}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (float16x8_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_f16 ();
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq (float32x4_t /* __v ATTRIBUTE UNUSED */)
+{
+ return __arm_vuninitializedq_f32 ();
+}
#endif /* __ARM_FEATURE_MVE & 2 (MVE floating point) */
#endif /* __cplusplus */
(define_int_iterator BF_MA [UNSPEC_BFMAB UNSPEC_BFMAT])
+(define_int_iterator CDE_VCX [UNSPEC_VCDE UNSPEC_VCDEA])
+
;;----------------------------------------------------------------------------
;; Mode attributes
;;----------------------------------------------------------------------------
;; An iterator for VFMA<bt>
(define_int_attr bt [(UNSPEC_BFMAB "b") (UNSPEC_BFMAT "t")])
+
+;; An iterator for CDE MVE accumulator/non-accumulator versions.
+(define_int_attr a [(UNSPEC_VCDE "") (UNSPEC_VCDEA "a")])
"vcx3a\\tp%c1, %q0, %q3, %q4, #%c5"
[(set_attr "type" "coproc")]
)
+
+(define_insn "arm_vcx1q<a>_p_v16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=t")
+ (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
+ (match_operand:V16QI 2 "register_operand" "0")
+ (match_operand:SI 3 "const_int_mve_cde1_operand" "i")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ CDE_VCX))]
+ "TARGET_CDE && TARGET_HAVE_MVE"
+ "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3"
+ [(set_attr "type" "coproc")
+ (set_attr "length" "8")]
+)
+
+(define_insn "arm_vcx2q<a>_p_v16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=t")
+ (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
+ (match_operand:V16QI 2 "register_operand" "0")
+ (match_operand:V16QI 3 "register_operand" "t")
+ (match_operand:SI 4 "const_int_mve_cde2_operand" "i")
+ (match_operand:HI 5 "vpr_register_operand" "Up")]
+ CDE_VCX))]
+ "TARGET_CDE && TARGET_HAVE_MVE"
+ "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4"
+ [(set_attr "type" "coproc")
+ (set_attr "length" "8")]
+)
+
+(define_insn "arm_vcx3q<a>_p_v16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=t")
+ (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
+ (match_operand:V16QI 2 "register_operand" "0")
+ (match_operand:V16QI 3 "register_operand" "t")
+ (match_operand:V16QI 4 "register_operand" "t")
+ (match_operand:SI 5 "const_int_mve_cde3_operand" "i")
+ (match_operand:HI 6 "vpr_register_operand" "Up")]
+ CDE_VCX))]
+ "TARGET_CDE && TARGET_HAVE_MVE"
+ "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5"
+ [(set_attr "type" "coproc")
+ (set_attr "length" "8")]
+)
case 8:
return "vmov%?.f32\t%0, %1\t%@ int";
case 9:
- return "vmsr%?\tP0, %1\t%@ movhi";
+ return "vmsr%?\t P0, %1\t%@ movhi";
case 10:
return "vmrs%?\t%0, P0\t%@ movhi";
default:
accum += __arm_cx3da (8, accum, n, m, 0); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
/* `imm` out of range. */
- accum += __arm_cx1 (0, 8192); /* { dg-error {argument 2 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx1a (0, (uint32_t)accum, 8192); /* { dg-error {argument 3 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx2 (0, n, 512); /* { dg-error {argument 3 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx2a (0, (uint32_t)accum, n, 512); /* { dg-error {argument 4 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx3 (0, n, m, 64); /* { dg-error {argument 4 must be a constant immediate in range \[0-63\]} } */
- accum += __arm_cx3a (0, (uint32_t)accum, n, m, 64); /* { dg-error {argument 5 must be a constant immediate in range \[0-63\]} } */
-
- accum += __arm_cx1d (0, 8192); /* { dg-error {argument 2 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx1da (0, accum, 8192); /* { dg-error {argument 3 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx2d (0, n, 512); /* { dg-error {argument 3 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx2da (0, accum, n, 512); /* { dg-error {argument 4 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx3d (0, n, m, 64); /* { dg-error {argument 4 must be a constant immediate in range \[0-63\]} } */
- accum += __arm_cx3da (0, accum, n, m, 64); /* { dg-error {argument 5 must be a constant immediate in range \[0-63\]} } */
-
- /* `imm` is not an immediate. */
- accum += __arm_cx1 (0, n); /* { dg-error {argument 2 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx1a (0, (uint32_t)accum, n); /* { dg-error {argument 3 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx2 (0, n, n); /* { dg-error {argument 3 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx2a (0, (uint32_t)accum, n, n); /* { dg-error {argument 4 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx3 (0, n, m, n); /* { dg-error {argument 4 must be a constant immediate in range \[0-63\]} } */
- accum += __arm_cx3a (0, (uint32_t)accum, n, m, n); /* { dg-error {argument 5 must be a constant immediate in range \[0-63\]} } */
-
- accum += __arm_cx1d (0, n); /* { dg-error {argument 2 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx1da (0, accum, n); /* { dg-error {argument 3 must be a constant immediate in range \[0-8191\]} } */
- accum += __arm_cx2d (0, n, n); /* { dg-error {argument 3 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx2da (0, accum, n, n); /* { dg-error {argument 4 must be a constant immediate in range \[0-511\]} } */
- accum += __arm_cx3d (0, n, m, n); /* { dg-error {argument 4 must be a constant immediate in range \[0-63\]} } */
- accum += __arm_cx3da (0, accum, n, m, n); /* { dg-error {argument 5 must be a constant immediate in range \[0-63\]} } */
+ accum += __arm_cx1 (0, 8192); /* { dg-error {argument 2 to '__builtin_arm_cx1si' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx1a (0, (uint32_t)accum, 8192); /* { dg-error {argument 3 to '__builtin_arm_cx1asi' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx2 (0, n, 512); /* { dg-error {argument 3 to '__builtin_arm_cx2si' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx2a (0, (uint32_t)accum, n, 512); /* { dg-error {argument 4 to '__builtin_arm_cx2asi' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx3 (0, n, m, 64); /* { dg-error {argument 4 to '__builtin_arm_cx3si' must be a constant immediate in range \[0-63\]} } */
+ accum += __arm_cx3a (0, (uint32_t)accum, n, m, 64); /* { dg-error {argument 5 to '__builtin_arm_cx3asi' must be a constant immediate in range \[0-63\]} } */
+
+ accum += __arm_cx1d (0, 8192); /* { dg-error {argument 2 to '__builtin_arm_cx1di' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx1da (0, accum, 8192); /* { dg-error {argument 3 to '__builtin_arm_cx1adi' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx2d (0, n, 512); /* { dg-error {argument 3 to '__builtin_arm_cx2di' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx2da (0, accum, n, 512); /* { dg-error {argument 4 to '__builtin_arm_cx2adi' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx3d (0, n, m, 64); /* { dg-error {argument 4 to '__builtin_arm_cx3di' must be a constant immediate in range \[0-63\]} } */
+ accum += __arm_cx3da (0, accum, n, m, 64); /* { dg-error {argument 5 to '__builtin_arm_cx3adi' must be a constant immediate in range \[0-63\]} } */
+
+ /* `imm` must be an immediate. */
+ accum += __arm_cx1 (0, n); /* { dg-error {argument 2 to '__builtin_arm_cx1si' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx1a (0, (uint32_t)accum, n); /* { dg-error {argument 3 to '__builtin_arm_cx1asi' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx2 (0, n, n); /* { dg-error {argument 3 to '__builtin_arm_cx2si' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx2a (0, (uint32_t)accum, n, n); /* { dg-error {argument 4 to '__builtin_arm_cx2asi' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx3 (0, n, m, n); /* { dg-error {argument 4 to '__builtin_arm_cx3si' must be a constant immediate in range \[0-63\]} } */
+ accum += __arm_cx3a (0, (uint32_t)accum, n, m, n); /* { dg-error {argument 5 to '__builtin_arm_cx3asi' must be a constant immediate in range \[0-63\]} } */
+
+ accum += __arm_cx1d (0, n); /* { dg-error {argument 2 to '__builtin_arm_cx1di' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx1da (0, accum, n); /* { dg-error {argument 3 to '__builtin_arm_cx1adi' must be a constant immediate in range \[0-8191\]} } */
+ accum += __arm_cx2d (0, n, n); /* { dg-error {argument 3 to '__builtin_arm_cx2di' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx2da (0, accum, n, n); /* { dg-error {argument 4 to '__builtin_arm_cx2adi' must be a constant immediate in range \[0-511\]} } */
+ accum += __arm_cx3d (0, n, m, n); /* { dg-error {argument 4 to '__builtin_arm_cx3di' must be a constant immediate in range \[0-63\]} } */
+ accum += __arm_cx3da (0, accum, n, m, n); /* { dg-error {argument 5 to '__builtin_arm_cx3adi' must be a constant immediate in range \[0-63\]} } */
/* `coproc` is not an immediate. */
accum += __arm_cx1 ((int)m, 0); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx3q (0, n, m); /* { dg-error {macro "__arm_vcx3q" requires 4 arguments, but only 3 given} } */
accum += __arm_vcx3qa (0, accum, n, m); /* { dg-error {macro "__arm_vcx3qa" requires 5 arguments, but only 4 given} } */
+ accum += __arm_vcx1q_m (0, accum, 33, 1, 4); /* { dg-error {macro "__arm_vcx1q_m" passed 5 arguments, but takes just 4} } */
+ accum += __arm_vcx1qa_m (0, accum, 33, 1, 4); /* { dg-error {macro "__arm_vcx1qa_m" passed 5 arguments, but takes just 4} } */
+ accum += __arm_vcx2q_m (0, accum, n, 33, 1, 4); /* { dg-error {macro "__arm_vcx2q_m" passed 6 arguments, but takes just 5} } */
+ accum += __arm_vcx2qa_m (0, accum, n, 33, 1, 4); /* { dg-error {macro "__arm_vcx2qa_m" passed 6 arguments, but takes just 5} } */
+ accum += __arm_vcx3q_m (0, accum, n, m, 33, 1, 4); /* { dg-error {macro "__arm_vcx3q_m" passed 7 arguments, but takes just 6} } */
+ accum += __arm_vcx3qa_m (0, accum, n, m, 33, 1, 4); /* { dg-error {macro "__arm_vcx3qa_m" passed 7 arguments, but takes just 6} } */
+ accum += __arm_vcx1q_m (0, accum, 4); /* { dg-error {macro "__arm_vcx1q_m" requires 4 arguments, but only 3 given} } */
+ accum += __arm_vcx1qa_m (0, accum, 4); /* { dg-error {macro "__arm_vcx1qa_m" requires 4 arguments, but only 3 given} } */
+ accum += __arm_vcx2q_m (0, accum, n, 4); /* { dg-error {macro "__arm_vcx2q_m" requires 5 arguments, but only 4 given} } */
+ accum += __arm_vcx2qa_m (0, accum, n, 4); /* { dg-error {macro "__arm_vcx2qa_m" requires 5 arguments, but only 4 given} } */
+ accum += __arm_vcx3q_m (0, accum, n, m, 4); /* { dg-error {macro "__arm_vcx3q_m" requires 6 arguments, but only 5 given} } */
+ accum += __arm_vcx3qa_m (0, accum, n, m, 4); /* { dg-error {macro "__arm_vcx3qa_m" requires 6 arguments, but only 5 given} } */
+
/* The preprocessor complains that the macro was given an invalid number of
arguments, and because of that ends up not expanding the macro but
rather just leaving the macro name in the source code. That macro name
/* { dg-error {'__arm_vcx3q' undeclared \(first use in this function\)} "" { target { *-*-* } } 17 } */
/* { dg-error {'__arm_vcx3qa' undeclared \(first use in this function\)} "" { target { *-*-* } } 18 } */
+ /* { dg-error {'__arm_vcx1q_m' undeclared \(first use in this function\)} "" { target { *-*-* } } 28 } */
+ /* { dg-error {'__arm_vcx1qa_m' undeclared \(first use in this function\)} "" { target { *-*-* } } 29 } */
+ /* { dg-error {'__arm_vcx2q_m' undeclared \(first use in this function\)} "" { target { *-*-* } } 30 } */
+ /* { dg-error {'__arm_vcx2qa_m' undeclared \(first use in this function\)} "" { target { *-*-* } } 31 } */
+ /* { dg-error {'__arm_vcx3q_m' undeclared \(first use in this function\)} "" { target { *-*-* } } 32 } */
+ /* { dg-error {'__arm_vcx3qa_m' undeclared \(first use in this function\)} "" { target { *-*-* } } 33 } */
+
return accum;
}
/* { dg-require-effective-target arm_v8_1m_main_cde_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_main_cde_mve_fp } */
-/* This file and cde-mve-error-tests.c are split since there are two kinds of
- errors happening here. The errors in the other file cause the compiler to
- not reach the errors found here, hence they need to be in a different file
- so we can inspect these ones. */
+/* The error checking files are split since there are three kinds of
+ errors happening here. Different error types cause errors at different
+ times, which means the compiler stops and doesn't produce messages about the
+ later errors. Hence they need to be in a different file so we can inspect
+ these ones. */
-uint8x16_t test_bad_immediates (uint8x16_t n, uint8x16_t m, int someval)
+uint8x16_t test_bad_immediates (uint8x16_t n, uint8x16_t m, int someval,
+ mve_pred16_t pred)
{
uint8x16_t accum = (uint8x16_t)(uint32x4_t){0, 0, 0, 0};
accum += __arm_vcx3q (1, n, m, 15); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
accum += __arm_vcx3qa (1, accum, n, m, 15); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+ accum += __arm_vcx1q_m (1, accum, 4094, pred); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+ accum += __arm_vcx1qa_m (1, accum, 4095, pred); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+ accum += __arm_vcx2q_m (1, accum, n, 126, pred); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+ accum += __arm_vcx2qa_m (1, accum, n, 127, pred); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+ accum += __arm_vcx3q_m (1, accum, n, m, 15, pred); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+ accum += __arm_vcx3qa_m (1, accum, n, m, 15, pred); /* { dg-error {coprocessor 1 is not enabled with \+cdecp1} } */
+
/* `coproc' out of range. */
accum += __arm_vcx1q_u8 (8, 4095); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx1qa (8, accum, 4095); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx3q (8, n, m, 15); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx3qa (8, accum, n, m, 15); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx1q_m (8, accum, 4094, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx1qa_m (8, accum, 4095, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx2q_m (8, accum, n, 126, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx2qa_m (8, accum, n, 127, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx3q_m (8, accum, n, m, 15, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx3qa_m (8, accum, n, m, 15, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+
/* `imm' out of range. */
- accum += __arm_vcx1q_u8 (0, 4096); /* { dg-error {argument 2 must be a constant immediate in range \[0-4095\]} } */
- accum += __arm_vcx1qa (0, accum, 4096); /* { dg-error {argument 3 must be a constant immediate in range \[0-4095\]} } */
- accum += __arm_vcx2q (0, n, 128); /* { dg-error {argument 3 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx2q_u8 (0, n, 129); /* { dg-error {argument 3 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx2qa (0, accum, n, 128); /* { dg-error {argument 4 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx3q_u8 (0, n, m, 16); /* { dg-error {argument 4 must be a constant immediate in range \[0-15\]} } */
- accum += __arm_vcx3q (0, n, m, 17); /* { dg-error {argument 4 must be a constant immediate in range \[0-15\]} } */
- accum += __arm_vcx3qa (0, accum, n, m, 16); /* { dg-error {argument 5 must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx1q_u8 (0, 4096); /* { dg-error {argument 2 to '__builtin_arm_vcx1qv16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx1qa (0, accum, 4096); /* { dg-error {argument 3 to '__builtin_arm_vcx1qav16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx2q (0, n, 128); /* { dg-error {argument 3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx2q_u8 (0, n, 129); /* { dg-error {argument 3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx2qa (0, accum, n, 128); /* { dg-error {argument 4 to '__builtin_arm_vcx2qav16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx3q_u8 (0, n, m, 16); /* { dg-error {argument 4 to '__builtin_arm_vcx3qv16qi' must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx3q (0, n, m, 17); /* { dg-error {argument 4 to '__builtin_arm_vcx3qv16qi' must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx3qa (0, accum, n, m, 16); /* { dg-error {argument 5 to '__builtin_arm_vcx3qav16qi' must be a constant immediate in range \[0-15\]} } */
+
+ accum += __arm_vcx1q_m (0, accum, 4097, pred); /* { dg-error {argument 3 to '__builtin_arm_vcx1q_p_v16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx1qa_m (0, accum, 4096, pred); /* { dg-error {argument 3 to '__builtin_arm_vcx1qa_p_v16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx2q_m (0, accum, n, 128, pred); /* { dg-error {argument 4 to '__builtin_arm_vcx2q_p_v16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx2qa_m (0, accum, n, 128, pred); /* { dg-error {argument 4 to '__builtin_arm_vcx2qa_p_v16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx3q_m (0, accum, n, m, 17, pred); /* { dg-error {argument 5 to '__builtin_arm_vcx3q_p_v16qi' must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx3qa_m (0, accum, n, m, 16, pred); /* { dg-error {argument 5 to '__builtin_arm_vcx3qa_p_v16qi' must be a constant immediate in range \[0-15\]} } */
/* `imm' is not an immediate. */
- accum += __arm_vcx1q_u8 (0, someval); /* { dg-error {argument 2 must be a constant immediate in range \[0-4095\]} } */
- accum += __arm_vcx1qa (0, accum, someval); /* { dg-error {argument 3 must be a constant immediate in range \[0-4095\]} } */
- accum += __arm_vcx2q (0, n, someval); /* { dg-error {argument 3 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx2q_u8 (6, n, someval); /* { dg-error {argument 3 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx2qa (0, accum, n, someval); /* { dg-error {argument 4 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx3q_u8 (0, n, m, someval); /* { dg-error {argument 4 must be a constant immediate in range \[0-15\]} } */
- accum += __arm_vcx3q (6, n, m, someval); /* { dg-error {argument 4 must be a constant immediate in range \[0-15\]} } */
- accum += __arm_vcx3qa (0, accum, n, m, someval); /* { dg-error {argument 5 must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx1q_u8 (6, someval); /* { dg-error {argument 2 to '__builtin_arm_vcx1qv16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx1qa (0, accum, someval); /* { dg-error {argument 3 to '__builtin_arm_vcx1qav16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx2q (0, n, someval); /* { dg-error {argument 3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx2q_u8 (6, n, someval); /* { dg-error {argument 3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx2qa (0, accum, n, someval); /* { dg-error {argument 4 to '__builtin_arm_vcx2qav16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx3q_u8 (0, n, m, someval); /* { dg-error {argument 4 to '__builtin_arm_vcx3qv16qi' must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx3q (6, n, m, someval); /* { dg-error {argument 4 to '__builtin_arm_vcx3qv16qi' must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx3qa (0, accum, n, m, someval); /* { dg-error {argument 5 to '__builtin_arm_vcx3qav16qi' must be a constant immediate in range \[0-15\]} } */
+
+ accum += __arm_vcx1q_m (6, accum, someval, pred); /* { dg-error {argument 3 to '__builtin_arm_vcx1q_p_v16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx1qa_m (0, accum, someval, pred); /* { dg-error {argument 3 to '__builtin_arm_vcx1qa_p_v16qi' must be a constant immediate in range \[0-4095\]} } */
+ accum += __arm_vcx2q_m (0, accum, n, someval, pred); /* { dg-error {argument 4 to '__builtin_arm_vcx2q_p_v16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx2qa_m (0, accum, n, someval, pred); /* { dg-error {argument 4 to '__builtin_arm_vcx2qa_p_v16qi' must be a constant immediate in range \[0-127\]} } */
+ accum += __arm_vcx3q_m (6, accum, n, m, someval, pred); /* { dg-error {argument 5 to '__builtin_arm_vcx3q_p_v16qi' must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx3qa_m (0, accum, n, m, someval, pred); /* { dg-error {argument 5 to '__builtin_arm_vcx3qa_p_v16qi' must be a constant immediate in range \[0-15\]} } */
/* `coproc' is not an immediate. */
accum += __arm_vcx1q_u8 (someval, 4095); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx3q (someval, n, m, 15); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx3qa (someval, accum, n, m, 15); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx1q_m (someval, accum, 4096, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx1qa_m (someval, accum, 4095, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx2q_m (someval, accum, n, 126, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx2qa_m (someval, accum, n, 127, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx3q_m (someval, accum, n, m, 15, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ accum += __arm_vcx3qa_m (someval, accum, n, m, 15, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+
/* `imm' is of wrong type. */
- accum += __arm_vcx1q_u8 (0, ""); /* { dg-error {argument 2 must be a constant immediate in range \[0-4095\]} } */
- accum += __arm_vcx1qa (0, accum, ""); /* { dg-error {argument 3 must be a constant immediate in range \[0-4095\]} } */
- accum += __arm_vcx2q (0, n, ""); /* { dg-error {argument 3 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx2q_u8 (0, n, "x"); /* { dg-error {argument 3 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx2qa (0, accum, n, ""); /* { dg-error {argument 4 must be a constant immediate in range \[0-127\]} } */
- accum += __arm_vcx3q_u8 (0, n, m, ""); /* { dg-error {argument 4 must be a constant immediate in range \[0-15\]} } */
- accum += __arm_vcx3q (0, n, m, "x"); /* { dg-error {argument 4 must be a constant immediate in range \[0-15\]} } */
- accum += __arm_vcx3qa (0, accum, n, m, ""); /* { dg-error {argument 5 must be a constant immediate in range \[0-15\]} } */
+ accum += __arm_vcx1q_u8 (0, ""); /* { dg-error {argument 2 to '__builtin_arm_vcx1qv16qi' must be a constant immediate in range \[0-4095\]} } */
+ /* { dg-warning {passing argument 2 of '__builtin_arm_vcx1qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 117 } */
+ accum += __arm_vcx1qa (0, accum, ""); /* { dg-error {argument 3 to '__builtin_arm_vcx1qav16qi' must be a constant immediate in range \[0-4095\]} } */
+ /* { dg-warning {passing argument 3 of '__builtin_arm_vcx1qav16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 119 } */
+ accum += __arm_vcx2q (0, n, ""); /* { dg-error {argument 3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range \[0-127\]} } */
+ /* { dg-warning {passing argument 3 of '__builtin_arm_vcx2qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 121 } */
+ accum += __arm_vcx2q_u8 (0, n, "x"); /* { dg-error {argument 3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range \[0-127\]} } */
+ /* { dg-warning {passing argument 3 of '__builtin_arm_vcx2qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 123 } */
+ accum += __arm_vcx2qa (0, accum, n, ""); /* { dg-error {argument 4 to '__builtin_arm_vcx2qav16qi' must be a constant immediate in range \[0-127\]} } */
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx2qav16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 125 } */
+ accum += __arm_vcx3q_u8 (0, n, m, ""); /* { dg-error {argument 4 to '__builtin_arm_vcx3qv16qi' must be a constant immediate in range \[0-15\]} } */
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx3qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 127 } */
+ accum += __arm_vcx3q (0, n, m, "x"); /* { dg-error {argument 4 to '__builtin_arm_vcx3qv16qi' must be a constant immediate in range \[0-15\]} } */
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx3qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 129 } */
+ accum += __arm_vcx3qa (0, accum, n, m, ""); /* { dg-error {argument 5 to '__builtin_arm_vcx3qav16qi' must be a constant immediate in range \[0-15\]} } */
+ /* { dg-warning {passing argument 5 of '__builtin_arm_vcx3qav16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 131 } */
+
+ accum += __arm_vcx1q_m (0, accum, "", pred); /* { dg-error {argument 3 to '__builtin_arm_vcx1q_p_v16qi' must be a constant immediate in range \[0-4095\]} } */
+ /* { dg-warning {passing argument 3 of '__builtin_arm_vcx1q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 134 } */
+ accum += __arm_vcx1qa_m (0, accum, "", pred); /* { dg-error {argument 3 to '__builtin_arm_vcx1qa_p_v16qi' must be a constant immediate in range \[0-4095\]} } */
+ /* { dg-warning {passing argument 3 of '__builtin_arm_vcx1qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 136 } */
+ accum += __arm_vcx2q_m (0, accum, n, "", pred); /* { dg-error {argument 4 to '__builtin_arm_vcx2q_p_v16qi' must be a constant immediate in range \[0-127\]} } */
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx2q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 138 } */
+ accum += __arm_vcx2qa_m (0, accum, n, "", pred); /* { dg-error {argument 4 to '__builtin_arm_vcx2qa_p_v16qi' must be a constant immediate in range \[0-127\]} } */
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx2qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 140 } */
+ accum += __arm_vcx3q_m (0, accum, n, m, "x", pred); /* { dg-error {argument 5 to '__builtin_arm_vcx3q_p_v16qi' must be a constant immediate in range \[0-15\]} } */
+ /* { dg-warning {passing argument 5 of '__builtin_arm_vcx3q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 142 } */
+ accum += __arm_vcx3qa_m (0, accum, n, m, "", pred); /* { dg-error {argument 5 to '__builtin_arm_vcx3qa_p_v16qi' must be a constant immediate in range \[0-15\]} } */
+ /* { dg-warning {passing argument 5 of '__builtin_arm_vcx3qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 144 } */
/* `coproc' is of wrong type. */
- accum += __arm_vcx1q_u8 ("", 4095); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
accum += __arm_vcx1qa ("", accum, 4095); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx1qav16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 148 } */
accum += __arm_vcx2q ("", n, 126); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
- accum += __arm_vcx2q_u8 ("", n, 127); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx2qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 150 } */
accum += __arm_vcx2qa ("", accum, n, 127); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
- accum += __arm_vcx3q_u8 ("", n, m, 14); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx2qav16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 152 } */
accum += __arm_vcx3q ("", n, m, 15); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx3qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 154 } */
accum += __arm_vcx3qa ("", accum, n, m, 15); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx3qav16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 156 } */
+
+ accum += __arm_vcx1q_m ("", accum, 4094, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx1q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 159 } */
+ accum += __arm_vcx1qa_m ("", accum, 4095, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx1qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 161 } */
+ accum += __arm_vcx2q_m ("", accum, n, 126, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx2q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 163 } */
+ accum += __arm_vcx2qa_m ("", accum, n, 127, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx2qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 165 } */
+ accum += __arm_vcx3q_m ("", accum, n, m, 15, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx3q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 167 } */
+ accum += __arm_vcx3qa_m ("", accum, n, m, 15, pred); /* { dg-error {coproc must be a constant immediate in range \[0-7\] enabled with \+cdecp<N>} } */
+ /* { dg-warning {passing argument 1 of '__builtin_arm_vcx3qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 169 } */
- /* { dg-warning {passing argument 2 of '__builtin_arm_vcx1qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 80 } */
- /* { dg-warning {passing argument 1 of '__builtin_arm_vcx1qv16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 90 } */
+ /* `pred" is of wrong type. */
+ accum += __arm_vcx1q_m (0, accum, 4094, "");
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx1q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 173 } */
+ accum += __arm_vcx1qa_m (0, accum, 4095, "");
+ /* { dg-warning {passing argument 4 of '__builtin_arm_vcx1qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 175 } */
+ accum += __arm_vcx2q_m (0, accum, n, 126, "");
+ /* { dg-warning {passing argument 5 of '__builtin_arm_vcx2q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 177 } */
+ accum += __arm_vcx2qa_m (0, accum, n, 127, "");
+ /* { dg-warning {passing argument 5 of '__builtin_arm_vcx2qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 179 } */
+ accum += __arm_vcx3q_m (0, accum, n, m, 15, "");
+ /* { dg-warning {passing argument 6 of '__builtin_arm_vcx3q_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 181 } */
+ accum += __arm_vcx3qa_m (0, accum, n, m, 15, "");
+ /* { dg-warning {passing argument 6 of '__builtin_arm_vcx3qa_p_v16qi' makes integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 183 } */
return accum;
}
/* { dg-require-effective-target arm_v8_1m_main_cde_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_main_cde_mve_fp } */
-uint32_t test (int8x16_t m, int8x16_t n)
+uint32_t test (int8x16_t m, int8x16_t n, mve_pred16_t pred)
{
/* Bad types for polymophic arguments. */
- uint32_t accum = 0, n_int = 0;
+ uint32_t accum = 0, n_int = 0, m_int = 0;
accum += __arm_vcx1qa (0, accum, 4095);
accum += __arm_vcx2q (0, n_int, 126);
accum += __arm_vcx2q_u8 (0, n_int, 127);
- accum += __arm_vcx2qa (0, accum, n, 127);
- accum += __arm_vcx3q_u8 (0, n_int, m, 14);
- accum += __arm_vcx3q (0, n_int, m, 15);
- accum += __arm_vcx3qa (0, accum, n, m, 15);
+ accum += __arm_vcx2qa (0, accum, n_int, 127);
+ accum += __arm_vcx3q_u8 (0, n_int, m_int, 14);
+ accum += __arm_vcx3q (0, n_int, m_int, 15);
+ accum += __arm_vcx3qa (0, accum, n_int, m_int, 15);
- /* { dg-error {argument 1 to function '__builtin_arm_vcx1qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 11 } */
+ /* We get a at least two errors for each function since the errors are
+ checked for validity in two different ways and both are caught.
+ The resolver manually checks that each type is 128 bits wide, and only
+ casts the value if that's true.
+ After the resolver rejects the function call then the C frontend tries to
+ fit the original call to the builtin. This produces a second set of
+ error messages from the C frontend argument checking. */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx1qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 11 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx1qav16qi'} "" { target *-*-* } 11 } */
- /* { dg-error {argument 1 to function '__builtin_arm_vcx2qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 12 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx2qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 12 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx2qv16qi'} "" { target *-*-* } 12 } */
- /* { dg-error {argument 1 to function '__builtin_arm_vcx2qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 13 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx2qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 13 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx2qv16qi'} "" { target *-*-* } 13 } */
- /* { dg-error {argument 1 to function '__builtin_arm_vcx2qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 14 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx2qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 14 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx2qav16qi'} "" { target *-*-* } 14 } */
- /* { dg-error {argument 1 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 15 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx2qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 14 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx2qav16qi'} "" { target *-*-* } 14 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 15 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx3qv16qi'} "" { target *-*-* } 15 } */
- /* { dg-error {argument 1 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 16 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 15 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qv16qi'} "" { target *-*-* } 15 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 16 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx3qv16qi'} "" { target *-*-* } 16 } */
- /* { dg-error {argument 1 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 17 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 16 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qv16qi'} "" { target *-*-* } 16 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 17 } */
/* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 17 } */
- return accum;
-}
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 17 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 17 } */
+ /* { dg-error {argument 4 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 17 } */
+ /* { dg-error {incompatible type for argument 4 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 17 } */
+
+ accum += __arm_vcx1qa_m (0, accum, 4095, pred);
+ accum += __arm_vcx2q_m (0, accum, n_int, 126, pred);
+ accum += __arm_vcx2qa_m (0, accum, n_int, 127, pred);
+ accum += __arm_vcx3q_m (0, accum, n_int, m_int, 15, pred);
+ accum += __arm_vcx3qa_m (0, accum, n_int, m_int, 15, pred);
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx1qa_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 58 } */
+ /* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx1qa_p_v16qi'} "" { target *-*-* } 58 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx2q_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 59 } */
+ /* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx2q_p_v16qi'} "" { target *-*-* } 59 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx2q_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 59 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx2q_p_v16qi'} "" { target *-*-* } 59 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx2qa_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 60 } */
+ /* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx2qa_p_v16qi'} "" { target *-*-* } 60 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx2qa_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 60 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx2qa_p_v16qi'} "" { target *-*-* } 60 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx3q_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 61 } */
+ /* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx3q_p_v16qi'} "" { target *-*-* } 61 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx3q_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 61 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3q_p_v16qi'} "" { target *-*-* } 61 } */
+ /* { dg-error {argument 4 to function '__builtin_arm_vcx3q_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 61 } */
+ /* { dg-error {incompatible type for argument 4 of '__builtin_arm_vcx3q_p_v16qi'} "" { target *-*-* } 61 } */
+
+ /* { dg-error {argument 2 to function '__builtin_arm_vcx3qa_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 62 } */
+ /* { dg-error {incompatible type for argument 2 of '__builtin_arm_vcx3qa_p_v16qi'} "" { target *-*-* } 62 } */
+ /* { dg-error {argument 3 to function '__builtin_arm_vcx3qa_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 62 } */
+ /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qa_p_v16qi'} "" { target *-*-* } 62 } */
+ /* { dg-error {argument 4 to function '__builtin_arm_vcx3qa_p_v16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 62 } */
+ /* { dg-error {incompatible type for argument 4 of '__builtin_arm_vcx3qa_p_v16qi'} "" { target *-*-* } 62 } */
-int8x16_t test2 (int8x16_t m, int8x16_t n)
-{
- uint32_t n_int = 0, m_int = 0;
- int8x16_t accum = (int8x16_t)(uint64x2_t) { 0, 0 };
- accum += __arm_vcx2qa (0, accum, n_int, 127);
- accum += __arm_vcx3q_u8 (0, n, m_int, 14);
- accum += __arm_vcx3q (0, n, m_int, 15);
- accum += __arm_vcx3qa (0, accum, n_int, m, 15);
- accum += __arm_vcx3qa (0, accum, n_int, m, 15);
- accum += __arm_vcx3qa (0, accum, n, m_int, 15);
- accum += __arm_vcx3qa (0, accum, n, m_int, 15);
-
- /* { dg-error {argument 2 to function '__builtin_arm_vcx2qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 40 } */
- /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx2qav16qi'} "" { target *-*-* } 40 } */
- /* { dg-error {argument 2 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 41 } */
- /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qv16qi'} "" { target *-*-* } 41 } */
- /* { dg-error {argument 2 to function '__builtin_arm_vcx3qv16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 42 } */
- /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qv16qi'} "" { target *-*-* } 42 } */
- /* { dg-error {argument 2 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 43 } */
- /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 43 } */
- /* { dg-error {argument 2 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 44 } */
- /* { dg-error {incompatible type for argument 3 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 44 } */
- /* { dg-error {argument 3 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 45 } */
- /* { dg-error {incompatible type for argument 4 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 45 } */
- /* { dg-error {argument 3 to function '__builtin_arm_vcx3qav16qi' is of type 'uint32_t' {aka '(?:long )?unsigned int'} which is not known to be 128 bits wide} "" { target *-*-* } 46 } */
- /* { dg-error {incompatible type for argument 4 of '__builtin_arm_vcx3qav16qi'} "" { target *-*-* } 46 } */
return accum;
}
accum += __arm_vcx3qa (0, accum, n_int, m, 15);
accum += __arm_vcx3qa (0, accum, n_int, m_int, 15);
- /* { dg-error {'accum_int' undeclared \(first use in this function\)} "" { target *-*-* } 70 } */
- /* { dg-error {'n_int' undeclared \(first use in this function\)} "" { target *-*-* } 71 } */
- /* { dg-error {'m_int' undeclared \(first use in this function\)} "" { target *-*-* } 75 } */
+ /* { dg-error {'accum_int' undeclared \(first use in this function\)} "" { target *-*-* } 99 } */
+ /* { dg-error {'n_int' undeclared \(first use in this function\)} "" { target *-*-* } 100 } */
+ /* { dg-error {'m_int' undeclared \(first use in this function\)} "" { target *-*-* } 104 } */
return accum;
}
** vmov q0, \2
** bx lr
*/
+
+/* Predicated MVE intrinsics. */
+/* Merging lane predication types.
+ NOTE: Depending on the target, the setup instructions (vldr's and vmsr) can
+ be in a different order. Here we just check that all the expected setup
+ instructions are there. We don't check that the setup instructions are
+ different since the likelyhood of the compiler generating repeated versions
+ of one rather than one and the other is very low and it's difficult to apply
+ such a constraint in TCL regexps (lookahead/lookbehind constraints may not
+ contain back references). */
+/*
+** test_cde_vcx1q_mfloat16x8_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_mfloat32x4_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_muint8x16_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_muint16x8_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_muint32x4_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_muint64x2_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_mint8x16_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_mint16x8_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_mint32x4_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1q_mint64x2_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1t p0, q0, #32
+** bx lr
+*/
+
+
+/*
+** test_cde_vcx1qa_mfloat16x8_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_mfloat32x4_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_muint8x16_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_muint16x8_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_muint32x4_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_muint64x2_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_mint8x16_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_mint16x8_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_mint32x4_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+/*
+** test_cde_vcx1qa_mint64x2_tintint:
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
+** vpst
+** vcx1at p0, q0, #32
+** bx lr
+*/
+
+
+/*
+** test_cde_vcx2q_mfloat16x8_tuint16x8_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_mfloat32x4_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_mint64x2_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_mint8x16_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_muint16x8_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_muint8x16_tint64x2_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_muint8x16_tint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_muint8x16_tuint16x8_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2q_muint8x16_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2t p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+
+
+/*
+** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_mint64x2_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_mint8x16_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_muint16x8_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tint64x2_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tuint16x8_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tuint8x16_tint:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
+** vpst
+** vcx2at p0, (q[0-7]), q0, #32
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+
+
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3t p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+
+
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t:
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
+** vpst
+** vcx3at p0, (q[0-7]), q0, q1, #15
+** vmov q0, \1([[:space:]]+@ [^\n]*)?
+** bx lr
+*/
/* { dg-require-effective-target arm_v8_1m_main_cde_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_main_cde_mve_fp } */
/* { dg-final { check-function-bodies "**" "" } } */
-
+/* { dg-additional-options "-mfpu=auto" } */
/* Test that the assembly is produced as expected.
Test that the same thing happens for each valid type.
type combination, just checking "all same type" and "different types",
also want to check every valid type at least once) */
-#define TEST_CDE_MVE_INTRINSIC_SPECIFIED_TYPE(name, accum_type, n_type, m_type, arguments) \
- accum_type test_cde_##name##accum_type##n_type##m_type ( \
- __attribute__ ((unused)) n_type n, \
- __attribute__ ((unused)) m_type m) \
- { \
- accum_type accum = (accum_type)(uint32x4_t){0,0,0,0}; \
- accum += (accum_type) __arm_##name arguments; \
- return accum; \
- }
-
/* Use every valid type for the output -- demonstrate can use any 128 bit value
(which is a requirement for these intrinsics). */
#define TEST_CDE_MVE_INTRINSIC_1(name, arguments) \
TEST_CDE_MVE_INTRINSIC_SPECIFIED_TYPE(name, uint8x16_t, uint8x16_t, int64x2_t, arguments) \
TEST_CDE_MVE_INTRINSIC_SPECIFIED_TYPE(name, uint8x16_t, int64x2_t, int64x2_t, arguments)
+
+#define TEST_CDE_MVE_INTRINSIC_SPECIFIED_TYPE(name, accum_type, n_type, m_type, arguments) \
+ accum_type test_cde_##name##accum_type##n_type##m_type ( \
+ __attribute__ ((unused)) n_type n, \
+ __attribute__ ((unused)) m_type m) \
+ { \
+ accum_type accum = (accum_type)(uint32x4_t){0,0,0,0}; \
+ accum += (accum_type) __arm_##name arguments; \
+ return accum; \
+ }
+
TEST_CDE_MVE_INTRINSIC_1(vcx1q_u8, (0, 33))
TEST_CDE_MVE_INTRINSIC_1(vcx1qa, (0, accum, 33))
TEST_CDE_MVE_INTRINSIC_3(vcx3q, (0, n, m, 12))
TEST_CDE_MVE_INTRINSIC_3(vcx3qa, (0, accum, n, m, 12))
+#undef TEST_CDE_MVE_INTRINSIC_SPECIFIED_TYPE
+#define TEST_CDE_MVE_INTRINSIC_SPECIFIED_TYPE(name, accum_type, n_type, m_type, arguments) \
+ accum_type test_cde_##name##accum_type##n_type##m_type ( \
+ __attribute__ ((unused)) n_type n, \
+ __attribute__ ((unused)) m_type m, \
+ mve_pred16_t pred) \
+ { \
+ accum_type accum = (accum_type)(uint32x4_t){0,0,0,0}; \
+ accum += (accum_type) __arm_##name arguments; \
+ return accum; \
+ }
+
+TEST_CDE_MVE_INTRINSIC_1(vcx1q_m, (0, accum, 32, pred))
+TEST_CDE_MVE_INTRINSIC_1(vcx1qa_m, (0, accum, 32, pred))
+
+TEST_CDE_MVE_INTRINSIC_2(vcx2q_m, (0, accum, n, 32, pred))
+TEST_CDE_MVE_INTRINSIC_2(vcx2qa_m, (0, accum, n, 32, pred))
+
+TEST_CDE_MVE_INTRINSIC_3(vcx3q_m, (0, accum, n, m, 15, pred))
+TEST_CDE_MVE_INTRINSIC_3(vcx3qa_m, (0, accum, n, m, 15, pred))
+
/* This testcase checks that in all compilations this C code produces the
expected CDE instructions from the above intrinsics.
/* { dg-final { scan-assembler-times "\tvcx3\t" 30 } } */
/* { dg-final { scan-assembler-times "\tvcx3a\t" 15 } } */
+/* { dg-final { scan-assembler-times "\tvcx1t\t" 11 } } */
+/* { dg-final { scan-assembler-times "\tvcx1at\t" 11 } } */
+/* { dg-final { scan-assembler-times "\tvcx2t\t" 12 } } */
+/* { dg-final { scan-assembler-times "\tvcx2at\t" 12 } } */
+/* { dg-final { scan-assembler-times "\tvcx3t\t" 15 } } */
+/* { dg-final { scan-assembler-times "\tvcx3at\t" 15 } } */
+
/*
** test_cde_vcx1q_u8__builtin_neon_tiintint:
** ...
** ...
*/
+/*
+** test_cde_vcx1q_m__builtin_neon_tiintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_mfloat16x8_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_mfloat32x4_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_muint8x16_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_muint16x8_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_muint32x4_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_muint64x2_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_mint8x16_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_mint16x8_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_mint32x4_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1q_mint64x2_tintint:
+** ...
+** vpst
+** vcx1t p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_m__builtin_neon_tiintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_mfloat16x8_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_mfloat32x4_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_muint8x16_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_muint16x8_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_muint32x4_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_muint64x2_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_mint8x16_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_mint16x8_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_mint32x4_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx1qa_mint64x2_tintint:
+** ...
+** vpst
+** vcx1at p0, q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_m__builtin_neon_tiuint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_muint8x16_t__builtin_neon_tiint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_mfloat16x8_tuint16x8_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_mfloat32x4_tuint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_mint64x2_tuint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_mint8x16_tuint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_muint16x8_tuint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_muint8x16_tint64x2_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_muint8x16_tint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_muint8x16_tuint16x8_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2q_muint8x16_tuint8x16_tint:
+** ...
+** vpst
+** vcx2t p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_m__builtin_neon_tiuint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_muint8x16_t__builtin_neon_tiint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_mint64x2_tuint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_mint8x16_tuint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_muint16x8_tuint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tint64x2_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tuint16x8_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx2qa_muint8x16_tuint8x16_tint:
+** ...
+** vpst
+** vcx2at p0, q[0-7], q[0-7], #32
+** ...
+*/
+/*
+** test_cde_vcx3q_m__builtin_neon_tiuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_t__builtin_neon_ti:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t:
+** ...
+** vpst
+** vcx3t p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_m__builtin_neon_tiuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_t__builtin_neon_ti:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
+/*
+** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t:
+** ...
+** vpst
+** vcx3at p0, q[0-7], q[0-7], q[0-7], #15
+** ...
+*/
uint64_t test_imm_range (uint32_t a, uint64_t b)
{
uint64_t res = 0;
- res += __arm_vcx1_u32 (0, 2048); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-2047\]} } */
- res += __arm_vcx1a_u32 (0, a, 2048); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-2047\]} } */
- res += __arm_vcx2_u32 (0, a, 64); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-63\]} } */
- res += __arm_vcx2a_u32 (0, a, a, 64); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-63\]} } */
- res += __arm_vcx3_u32 (0, a, a, 8); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-7\]} } */
- res += __arm_vcx3a_u32 (0, a, a, a, 8); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-7\]} } */
- res += __arm_vcx1d_u64 (0, 2048); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-2047\]} } */
- res += __arm_vcx1da_u64 (0, a, 2048); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-2047\]} } */
- res += __arm_vcx2d_u64 (0, a, 64); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-63\]} } */
- res += __arm_vcx2da_u64 (0, a, a, 64); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-63\]} } */
- res += __arm_vcx3d_u64 (0, a, a, 8); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-7\]} } */
- res += __arm_vcx3da_u64 (0, a, a, a, 8); /* { dg-error {argument [2-5] must be a constant immediate in range \[0-7\]} } */
+ res += __arm_vcx1_u32 (0, 2048); /* { dg-error {argument [2-5] to '__builtin_arm_vcx1si' must be a constant immediate in range \[0-2047\]} } */
+ res += __arm_vcx1a_u32 (0, a, 2048); /* { dg-error {argument [2-5] to '__builtin_arm_vcx1asi' must be a constant immediate in range \[0-2047\]} } */
+ res += __arm_vcx2_u32 (0, a, 64); /* { dg-error {argument [2-5] to '__builtin_arm_vcx2si' must be a constant immediate in range \[0-63\]} } */
+ res += __arm_vcx2a_u32 (0, a, a, 64); /* { dg-error {argument [2-5] to '__builtin_arm_vcx2asi' must be a constant immediate in range \[0-63\]} } */
+ res += __arm_vcx3_u32 (0, a, a, 8); /* { dg-error {argument [2-5] to '__builtin_arm_vcx3si' must be a constant immediate in range \[0-7\]} } */
+ res += __arm_vcx3a_u32 (0, a, a, a, 8); /* { dg-error {argument [2-5] to '__builtin_arm_vcx3asi' must be a constant immediate in range \[0-7\]} } */
+ res += __arm_vcx1d_u64 (0, 2048); /* { dg-error {argument [2-5] to '__builtin_arm_vcx1di' must be a constant immediate in range \[0-2047\]} } */
+ res += __arm_vcx1da_u64 (0, a, 2048); /* { dg-error {argument [2-5] to '__builtin_arm_vcx1adi' must be a constant immediate in range \[0-2047\]} } */
+ res += __arm_vcx2d_u64 (0, a, 64); /* { dg-error {argument [2-5] to '__builtin_arm_vcx2di' must be a constant immediate in range \[0-63\]} } */
+ res += __arm_vcx2da_u64 (0, a, a, 64); /* { dg-error {argument [2-5] to '__builtin_arm_vcx2adi' must be a constant immediate in range \[0-63\]} } */
+ res += __arm_vcx3d_u64 (0, a, a, 8); /* { dg-error {argument [2-5] to '__builtin_arm_vcx3di' must be a constant immediate in range \[0-7\]} } */
+ res += __arm_vcx3da_u64 (0, a, a, a, 8); /* { dg-error {argument [2-5] to '__builtin_arm_vcx3adi' must be a constant immediate in range \[0-7\]} } */
return res;
}
}
/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tP0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
projects / gcc.git / commitdiff