Build top module as 'dut' in Verilator and set it as top-level.

When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 0388cdda05a970b244a6a8407015e01a3ede8fe8..8ccb4ff0e897a2ecd39a56a386e42eff33436b8f 100644 (file)
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
 sim: mkdir $(OBJS_SIM)
        verilator -Wno-fatal -O3 --cc dut.v --exe \
                $(SRCS_SIM_CPP) $(OBJS_SIM) \
+               --top-module dut \
                -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
                -LDFLAGS "$(LDFLAGS)" \
                -trace $(INC_DIR)

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 312d51e3fe38b7ea8b3b28467905bc191f12c380..d4092b65843408a69b042ec5375bcdb73057a431 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -146,7 +146,7 @@ class SimVerilatorToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_output.write("dut.v")